Tutorial 5 - Sequential Circuits - Finite State Machines

Tutorial 5

Sequential Circuits - Finite State Machines

THINGS TO LOOK FOR

The extension of sequential systems to include input and output capability. Guidelines for the design of finite state machines. The Mealy and Moore machines and their differences. Assigning values to state variables several approaches. Developing the defining equations for a finite state machine. Modeling FSMs using RTL and structural models. Optimizing finite state machines using row reduction and implication charts.

5.0

INTRODUCTION
In this tutorial, we assume a background in basic memory devices and how such devices can be utilized in the design and implementation of elementary sequential circuits such as counters, dividers, and timers. We now build on that background as we examine the development of general purpose sequential machines. Such machines find application in controlling and coordinating the activity of most modern microprocessors, microcontrollers, and microcomputers as well as more complex digital systems. We will also develop both RTL and structural level models in Verilog for the FSM. Design is one step in the process of developing embedded applications. Equally important as an integral part of that process is the optimization of the system to increase reliability, and to reduce power, cost, and weight. In this tutorial we will introduce and examine several different approaches for reducing the complexity of sequential machines.

counters dividers timers sequential machines

5.1

Finite State Machines

Normally, the input and output capabilities of counting, timing, and dividing sequential machines are limited to a few control lines, an output frequency, or a signaling event. To be able to perform the complex computation and control necessary in modern digital systems, we must accept a greater variety of input signals and develop a richer set of output capability.

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Tutorial 5 - Sequential Circuits - Finite State Machines

In our studies, we will use the model for the finite state machine given by the 5-tuple,
M = (I, O, S, , ) I - Finite nonempty set or vector of inputs O - Finite nonempty set or vector of outputs S - Finite nonempty set or vector of states - Mapping I x S S 1 - Mapping I x S O - Mealy Machine 2 - Mapping S O - Moore Machine

Lets now take a detailed look at how we can begin to apply such a model to the design of more sophisticated and capable finite state machines.

5.2

The Design of a Serial Pattern Detector

Well begin with a simple pattern or sequence detector. One finds possible uses for such a system in telecommunications systems or in other applications where it may be necessary to synchronize or lock onto a data stream containing a preamble or initial synchronizing pattern. For this design, we assume that data will enter the system, in serial, one bit at a time and that the specifications require detecting the preamble pattern 1010 in the data. If the pattern is recognized, the system is to issue an output signal, found. The detectors output signal will be a function of both the input and the current state. Thus, our design will implement a Mealy machine.

5.2.1

The High Level Design

We begin the design with a high level outside view of the system. The details of the larger system environment, which may be a complex telecommunications system, are not important; the public interface that the pattern detector presents to that environment is. The enclosing system provides a serial stream of data and expects an annunciating event if a specified pattern is detected. The system requirements are given as, Inputs One input A serial stream of data. The data is expressed in big endian format with the least significant bit received first. Outputs One output A logical 1 that will annunciate the presence of each occurrence of the sequence 1010 in the data stream. Algorithm The pattern detection is to use a sliding window algorithm. As a first step, we capture the requirements from the outside point of view in a high level block diagram as shown in Figure 5.0. In this case, the diagram is rather elementary.
serial data Pattern Detector Note: pattern must be 1010 Assume: LSB arrives at t0 found

Figure 5.0 Pattern Detector High Level Block Diagram

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We can execute a second level of decomposition or refinement, as we see in Figure 5.1, to distinguish the pattern recognition portion of the system and the output section. There is little need to decompose further.
serial data Pattern Detection Machine detected Output Generation found

Note: pattern must be 1010 Assume: LSB arrives at t0

Figure 5.1 Pattern Detector Second Level Block Diagram

5.2.2

The State Diagram

To formally capture the behavior of the system, we begin with a state diagram. The state diagram objective is to be able to express the behavior of the system in time. We must identify each legal state of the system and each of the transitions amongst those states. States Each state in the machine corresponds to a vertex, or node, in the state diagram. If the system has ten states, the state diagram will have 10 nodes. Transitions For each state or vertex in the state diagram, there will be 2p directed arcs, one for each combination of inputs. The arcs identify the state transitions caused by the input variables. These arcs express the mapping I x S S we saw in the earlier finite state machine model. If the system has three inputs, each state will have 23 arcs leaving; one arc for each of the eight possible input combinations. Its clear that such a combinational explosion is one of the limitations of the basic finite state machine. In the state diagram for either machine, we label each transition arc as shown.
Mealy: Input / Output Moore: Input

The input portion of the label identifies the causative vector of input values associated with the transition. For the Mealy machine, the label also identifies the resulting vector of output values. For the Moore machine, the output information is written inside the node, usually in square brackets. Behavior The state diagram completely describes the system. It shows the succession of states through which the sequential machine passes and the corresponding output sequence that it produces. We distinguish two of those states, Initial State State of the machine prior to the application of any input sequence. The initial state is normally the power ON state of the system; it is also called the idle state or the quiescent quiescent state. state
idle state

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Final State State of the machine after the application of the last input sequence. Prelude to the Design Before starting the design, the specification must be clarified. For the following sample sequence .10101010.there are two possible interpretations 1. The data stream can be examined in four bit groups. If the pattern is detected, the detector begins a new search starting with the next group of four bits. For the above sequence, the pattern will be detected twice, .1010 1010 . .1010 1010 . Part of the pattern can be reused. For the above data stream, the pattern will be detected three times, .1010 1010 . .101010 10. .1010 1010 .

2.

Such an interpretation is called a sliding window. For this design, as required by the dow specification, the system will implement the second interpretation. Beginning the Design The system will start in the idle state. Most of designs use an initial or idle state. This is also the state that the system enters following a power ON or other form of reset condition. In this case, we will label that state as state A. Since there is only a single input, there can only be two possible transitions from each state node. In the idle state, the system is at time t0; the input signal can be either a 0 or a 1. If the input bit is a logical 0, the state diagram will reflect that fact with a transition to a new state, state B. State B captures several pieces of information / history about the system. By virtue of being in a new state, B, we know, 1. The pattern detection process has started. 2. Based upon the specification and from the meaning of state B, it is known that 1 bit of the pattern being searched for is correct that bit is a logical 0. 3. The pattern has not yet been found; thus, the output must be false. If the input data bit is a logical 1 1. The state machine remains in state A. Again, based upon the specification and from the meaning of state A, it is known that no bits in the pattern have been correctly recognized. 2. The pattern has not yet been found; thus, the output must be false. These two possibilities cover all input combinations for state A as shown in Figure 5.2. The state diagram becomes,
1/0 0/0 A B

sliding win-

Figure 5.2 Pattern Detector State Diagram After One Bit Entered

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Observe that each transition is labeled showing causative input vector and resulting output vector. In state B, the system is at relative time t1. Again the input can be either a 0 or a 1. If the input data bit is a 0 1. The system remains in state B. The implications of state B still hold, there has only been one correct bit received. 2. The system remains at relative time t1. 3. The output of the system is false. If the input data bit is a 1, the system enters a new state, state C. By virtue of being in state C, it is known, 1. That 2 bits of the pattern are correct that subsequence is 0 1. 2. The pattern has not been found yet; thus, the output must be false. The state diagram is now show in Figure 5.3.
1/0 0/0 A B 0/0

1/0

Figure 5.3 Pattern Detector State Diagram After Two Bits Entered

In state C, the system is now at relative time t2. Once again the input can be either a 0 or a 1, If the input data bit is a 0, the system enters a new state, state D. By virtue of being in state D, it is known, 1. 2. That 3 bits of the pattern being searched for have been recognized that subsequence is 0 1 0. The pattern has not been found yet; the system is now looking for the fourth data bit, thus, the output must be false.

If the input data bit is a 1 1. The detection process has failed and must start over. The system must return to state A. 2. The system is now at relative time t0. 3. The output of the system is false. The state diagram in Figure 5.4 reflects the state of the system after the third bit is entered.
1/0 1/0 0/0 A B 0/0

1/0

0/0

Figure 5.4 Pattern Detector State Diagram After Three Bits Entered

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In state D, the system is at relative time t3. Once again the input can be either a 0 or a 1, If the input data bit is a 0, the system must return to state B. By virtue of being in state B, we know, 1. The implications of state B still hold. The two successive logical 0 bits mean that there has only been one correct bit received the last logical 0 bit. 2. The system remains at relative time t1. 3. The output of the system is false. If the input data bit is a 1, the system returns to state C and the output is a logical 1 1. It is known that 4 bits of the pattern being searched for are correct that subsequence is 0 1 0 1. 2. It is also known that the last two bits of the pattern just received correctly match the initial two bits of the second potential reception of the pattern. That information is implicit in state C. 3. The system is now at relative time t2. 4. The output of the system is true. The final state diagram is now presented in Figure 5.5,
1/0 Reset 0/0 0/0 A B

1/0

1/0

0/0 1/1

0/0

Figure 5.5 Pattern Detector State Diagram After Four Bits Entered

The master (or Power ON) reset which, on application, forces the system into the initial state is included; the complete behavior of the system has now been captured. Such a diagram can be used for further discussion and analysis. The state table is a better vehicle to begin the next stage of design

5.2.3

The State Table

The state table contains the same information as state diagram simply rewritten in tabular form. The state tables weve written in another tutorial and in the text have had two major subdivisions: one column showing the state of the system at time tn, the present present state state of the system, and a second column showing the state of the system at time tn+1, the next state next state of the system. The next state subdivision is now refined to incorporate the mapping I x S S, that is, to reflect the behavior of the system for each possible combination of system inputs. To this end, under the next state heading, the state table will contain p columns; one for each of the p combinations of the input symbols in set I. The state table will contain n rows, one for each possible state in the set S (in the system). The cross product of the columns and rows will give all possible combinations of

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inputs and states. To implement the state machine will require k memory elements; k is smallest integer value such that k log2 p. For the current design, the next state category will have two columns: one for the input data taking a value of logical 0 and one for the input data taking a value of logical 1. The state machine will have 4 rows, one for each state. Taking the information directly from the state diagram in Figure 5.5 gives the state table in Figure 5.6.
Present State t = tn
x=0 A B C D B B D B

Next State t = tn+1

x=1 A C A C

Figure 5.6 Pattern Detector State Table

5.2.4

The Output Table

The next step in the process is to specify the outputs from the system; these appear in output table an output table. Once again this information can be extracted directly from the state diagram. Often the state and output tables are merged into single table. The output table for a Mealy machine also has p columns, one for each combination of input symbols in set I and n rows, one or each state in the set S. From the earlier model, the output table gives the output matrix, I x S O Mealy Machine S O Moore Machine

Each combination of the elements of the input vector with the present state specifies the output of system. If the system is to implement a Moore machine, the output entries are independent of the input. Once again reading directly from the state diagram, the output table for the current design is given in Figure 5.7. This design implements a Mealy machine.
Present State t = tn
x=0 A B C D 0 0 0 0

Next State t = tn+1

x=1 0 0 0 1

Figure 5.7 Pattern Detector Output Table

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5.2.5

The State Assignment

In the earlier finite state machines that we have designed in the text, the values for the state variables in each state were implicit in the specified counting or dividing sequence. Such is no longer the case. As designers, its now our responsibility to choose the systems state variables and assign appropriate combinations to each state in such a manner that we can uniquely identify each state in the system. Selecting a state variable assignment is an important step in the design of any finite state machine. There are a wide variety of techniques, with varying degrees of complexity, that are available for making such assignments. Lets look at several. Binary Assignment The easiest method is to simply use a binary sequence. The initial state gets the pattern of binary 0; each subsequent state gets the next binary number. The approach often works without problems. The one major limitation is building output signals as collections of combinational expressions; that is, the outputs of the combinational logic circuits are subject to race conditions and hazards. With such an approach, one always runs the risk of having decoding spikes on systems outputs. One Hot Code The one hot code makes a trade-off between increased circuit complexity and simplicity in generating output signals. With the exception of the initial state, the one hot code utilizes state assignments with only a single one bit in each. For example, a four state machine might utilize an assignment such as that given in Figure 5.8,

State 0 1 2 3

ABC
0 0 0 0 0 1 0 1 0 1 0 0

Figure 5.8 One Hot State Encoding

Certainly the four states could have been uniquely identified using only two bits. The three bit pattern, however, eliminates the need to decode any state or input combinations to produce an output signal thereby also clearly eliminating any logic hazards. When bit C is a 1, it is known that the machine must be in state 1 and vice versa. Gray Assignment The purpose of a Gray code assignment is also to address the problem of race conditions producing hazards when decoding output signals. With a Gray code assignment, the goal is to ensure that we have only a single variable change between states. The first step in the approach is to develop a table listing all states. For each state, identify the previous and the next states. Such states are then assigned state variable patterns such that, in the ideal case, pervious to present and present to next transitions involve only a single variable change. For example, the sequence
1 0 0

1 0 1 1 1 1

illustrates such a transition. By using such an assignment, one can ensure that the transitions between the three states follow a Gray code sequence and that if any of the states are decoded as an output signal, there will not be any hazards. To formulate a Gray code assignment for the current design, we perform the following sequence of steps,

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1.

Identify the adjacent state transitions. These are identified in Table 5.0,
Table 5.0 Previous - Present - Next State Relationship Previous State
C A,D B,D C

Present State
A B C D

Next State
B C A,D B,C

2.

Assign states such that there is a single variable change from present to next and previous to present. A Karnaugh map is a rather useful graphical aid. Satisfying the constraint for all states may not always be possible. In such cases, state sequences that contribute to combinational relations of output signals should be given preference. For the system under design, there are 4 states; therefore the assignment will require 2 state variables.

A common heuristic suggests assigning the all 0s pattern to the initial state. The motivation for doing so is that at Power ON, normally all storage elements (exclusive of RAM) are reset to 0. Once the initial state is specified, the rest of the states are assigned so as to meet the state adjacency requirements identified earlier as we see in the adjacent Karnaugh map. From the map in Figure 5.9, one such assignment is now given as that in Figure 5.10.

M
0 1

0
A C

1
B D

Figure 5.9 A Gray Code State Assignment

5.2.6

The Transition Table

Once the state assignment is determined, the next step is to use that assignment to construct a transition table. The transition table combines the state table with the state assignment by substituting the state variable combination for each state back into the state table. For the current design the transition table is given in Figure 5.11.

M N A 0 0 B 0 1 C 1 1 D 1 0

transition table

Figure 5.10 A Gray Code State Assignment

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Present State t = tn
x=0 M N A B C D 0 0 0 1 1 1 1 0 B B D B

Next State t = tn+1

x=1 M N A C A C 0 0 1 1 0 0 1 1 M N 0 1 0 1 1 0 0 1

Figure 5.11 Pattern Detector Transition Table

5.2.7

The Input Equations

Using information from the transition table, the K Maps given in Figure 5.12 are now written for the flip-flop input equations.
MN
00 01 11 10

0
0 0 1

1
0

MN
00 01 11

1
0 1

1 M map

N map

10

Figure 5.12 Pattern Detector Flip-Flop K Maps

As discussed in the text, the and notation reflects a 0 to 1 and a 1 to 0 transition of the state variable respectively. If the system is to be implemented using JK flip flops, the logic equations can be written directly from the maps as given in Figure 5.13.
M
JM = N X KM = (N X)

N
JN = M + X KN = M

Figure 5.13 JK Flip Flop Input Equations

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5.2.8

The Output Equations

The output equations follow in a similar manner; once again, a K Map used. For the current design we have the K Map and output equation given in Figure 5.14.
MN
00 01 11 10

0
0 0 0 0

1
0 0 0 1

x found = M N X

found

Figure 5.14 Pattern Detector Output Equation

The JK flip-flop is first implemented using a behavioral model in Figure 5.15.

module JKFF(q, qBar, J, K, clk, por); input J, K, clk, por; output q, qBar; parameter delay0 = 2; // delay reset to q parameter delay1 = 3; // delay clock to q parameter delay2 = 2; // delay for qBar // with respect to q reg q; not #delay2 n1 (qBar, q); always@ (negedge por or posedge clk) begin if(por==0) #delay0 q = 0; else if ((J == 0) && (K==1)) #delay1 q = 0; else if ((J == 1) & (K==0)) #delay1 q = 1; else if ((J == 1) & (K==1)) #delay1 q = qBar; end Figure 5.15 endmodule J K Flip Flop Behavioral Model

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Next, the structural model for the design using JK flip-flops follows in Figure 5.16.
module PatternRecog0(foundIt, qm, qn, dataIn, clk, por); // build the pattern recognizer // declare the inputs and outputs input dataIn, clk, por; output foundIt, qm, qn; // implement the state machine and and0(jm, qn, dataIn); xnor xnor0(km, qn, dataIn); JKFF M(qm, qmBar, jm, km, clk, por); not inv0(ndataIn, dataIn); or or0(jn, qm, ndataIn); JKFF N(qn, qnBar, jn, qm, clk, por); // output equation and and1(foundIt, qm, qnBar,dataIn); endmodule

Figure 5.16

Pattern Detector Structural Model

The code module in Figure 5.17 provides an RTL- behavioral implementation of the pattern detector.
module PatternRecog0(foundIt, state, dataIn, clk, por); // declare the inputs and outputs input dataIn, clk, por; output foundIt; output[1:0] state; reg foundIt; reg[1:0] state; //define parameter or name of each state parameter A = 2'b00; parameter B = 2'b01; parameter C = 2'b11; parameter D = 2'b10; // build the pattern recognizer always@ (negedge por or posedge clk) begin // reset the machine if(por==0) begin assign state = A; assign foundIt = 1'b0; end else // continued Figure 5.17 Pattern Detector Behavioral Model

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// implement the state machine begin case(state) // initial state 0 correct pattern xxxx A: begin if(dataIn == 1'b0) assign state = B; else assign state = A; assign foundIt = 1'b0; end// one correct pattern xxx0 B: begin if(dataIn == 1'b0) assign state = B; else assign state = C; assign foundIt = 1'b0; end // two correct pattern xx10 C: begin if(dataIn == 1'b0) assign state = D; else assign state = A; assign foundIt = 1'b0; end // three correct pattern x010 D: begin if(dataIn == 1'b1) begin // four correct pattern 1010 assign state = C; assign foundIt = 1'b1; end else assign state = B; end endcase end end endmodule

Figure 5.17 cont. Pattern Detector Behavioral Model

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5.3

Design Guidelines
A general set of guidelines for designing finite state machines is now presented in Figure 5.18. 1. 2. 3. 4. 5. 6. 7. 8. 9. From a word description of the problem, form a state diagram. From the state diagram develop the state table. Check for redundant states. Select a state assignment. Develop the transition and output tables. Develop a Karnaugh map for each state variable. Select a memory device and develop the input equations from the Karnaugh map. Develop a Karnaugh map for each output variable. Develop the output equations from the Karnaugh map.
Figure 5.18 Design Guidelines for Finite State Machine Design

Example 5.0

Lets look at another pattern recognition problem. The specification requires the design of a system that accepts a serial bit stream on the input and searches for either of the patterns: 011 or 110 in the input data stream. If, following the reception of three input data bits, the first pattern 011 is found, the output found0 is asserted high and if the second pattern 110 is found the output found1 is asserted high. Both outputs are to be in the low state otherwise. The outside view of the system as expressed in the high level block diagram is given in Figure 5.19. In the block diagram, all inputs and outputs are identified.
match0 serial data Pattern Detection Machine Output Generation match1

found0 found1

Note: pattern must be 011 or 110 Assume: LSB arrives at t0

Figure 5.19 High Level Block Diagram System Detecting Two Patterns

From the design specification, the desired behavior of the system is captured in a state diagram. This is an essential first step.

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Step 1 Figure 5.20 gives the state diagram for the detection system.
Reset 0 [0] 0 1

1 [0] 0 1 0

2 [0] 1

3 [0]

1 0

4 [0]

0 1

5 [0] 0 1

6 [0]

No Match

7 [0]

8 [1]

Match

9 [1]

0 [0]

Figure 5.20 Pattern Detector State Diagram

The two paths for which the input sequence will yield a match are highlighted. After three input bits have been received, the system returns to the initial state. Step 2 The state table, combined with the output table, is written from the state diagram and presented in Figure 5.21.
Present State t = tn Next State t = tn+1
x=0 0 1 2 3 4 5 6 7 8 9 1 3 5 7 7 7 9 0 0 0 x=1 2 4 6 7 8 7 7 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1

Outputs found0 found1

Figure 5.21 Pattern Detector State and Output Table

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Observe that the design is a Moore machine. The output signals for all of the states are only a function of the present state, not the input: S O. Step 3 We are skipping Step 3 for the moment. Step 4 Select a state assignment. For this example, there are 10 states which require four state variables. Such an assignment will also give seven dont care combinations. A Gray assignment will be used to specify the values of the state variables. We begin by identifying the previous, present, and next state relationships. These are tabulated in Table 5.1.
Table 5.1 Previous - Present - Next State Relationship Previous State
0 0 1 1 2 2 3,4,5 4 6

Present State
0 1 2 3 4 5 6 7 8 9

Next State
1,2 3,4 5,6 7 7,8 7 7,9 0 0 0

Based upon the transitions identified, we draw the K Map for the state assignment in Figure 5.22. Observe that the assignment is not unique. Further, we cannot completely ensure that all transitions have only a single variable change.
A B C D

MN
00 01 11 10

00
0 2 5 3

01
1 6 7

11
4 9

10
8

CD

0 1 2 3 4 5 6 7 8 9

0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 1 1 1

Figure 5.22 Pattern Detector State Assignment

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Step 5 Specify the transition and output tables. We accomplish this in Figure 5.23.
Present State t = tn
ABC D 0 0000 1 0001 2 0100 3 1000 4 0011 5 1100 6 0101 7 1101 8 0010 9 0111

Next State t = tn+1

x=0 ABCD 1 0000 3 0001 5 0100 7 1000 7 0011 7 1100 9 0101 0 1101 0 0010 0 0111 x=1 ABCD 2 0000 4 0001 6 0100 7 1000 8 0011 7 1100 7 0101 0 1101 0 0010 0 0111

Outputs

found0
0 0 0 0 0 0 0 0 1 0

found1
0 0 0 0 0 0 0 0 0 1

Figure 5.23 Pattern Detector Transition and Output Table

Step 6 Develop Karnaugh maps for each state variable. The K Map for state variable A is given in Figure 5.24.
ABC
000 001 011 010 110 111 101 100

00
0 0 X

01
0 0 X 0 1 X X X

11
1 0 0

10

Dx

0 0

1 X X X

X X 1

X X 1 A map

Figure 5.24 K Map for State Variable A

The equation for DA follows, DA = A D + B D X + B D X + B C D + A B C D X

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Example 5.1

Lets now look at a system with more than one input. The system is designed to permit access to a restricted area if the user properly enters the correct access code. The access code for the system is the sequence 3 2 2 1 to open. All four digits must be entered correctly, in order, to allow access. The high level block diagram for the system is given in Figure 5.25.
bit 0 Lock bit 1 correct Output Generation open

Encoder

keypad

Note: the lock will only open for the pattern 3 2 2 1

Figure 5.25 High Level Block Diagram for a Simple Combination Lock

From the specification, the state diagram is drawn in Figure 5.26,

Reset
00/0 01/0 10/0

0
11/0 01/1 00/0 01/0 10/0

00/0 01/0 10/0

00/0 01/0 10/0

10/0

10/0

Figure 5.26 Combination Lock State Diagram

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From the state diagram, the state and output tables follow naturally in Figure 5.27.
Next State t = tn+1 X2 X1
00 01 11 10 00

Present State t = tn
0 1 2 3

Outputs
01 11 10

0 0 0 0

0 2 3 0

1 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 1

Figure 5.27 Combination Lock State and Output Table

For this problem, well use a basic Gray sequence for the state assignment. Such an assignment gives the transition table in Figure 5.28.

Present State t = tn AB
0 00 1 01 2 11 3 10

Next State t = tn+1 X2 X1

00 01 11 10 00

Outputs
01 11 10

AB 0 00 0 01 0 11 0 10

AB 0 00 2 01 3 11 3 10

AB 1 00 0 01 0 11 0 10

AB 0 00 0 01 0 11 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Figure 5.28 Combination Lock Transition Table

The K Maps for the two state variables then follow in Figure 5.29,
AB
00 01 11 10

00
0 0

01
0 0

11
0 0

10
0

X2 X1

A map

Figure 5.29a Combination Lock State Variable K Maps

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AB
00 01 11 10

00
0

01
0

11

10
0 1

X2 X1

0 B map

Figure 5.29b Combination Lock State Variable K Maps

From which the flip-flop equations are given as,

D A = B X1 X2 D B = A X2 ( B X1 )

The RTL implementation of the circuit is given in the code module in Figure 5.30,
module ComboLock0(open, state, comboIn, clk, por); // declare the inputs and outputs input clk, por; input[1:0] comboIn; output open; output[1:0] state; reg open; reg[1:0] state; //define parameter or name of each state parameter s0 = 2'b00; parameter s1 = 2'b01; parameter s2 = 2'b11; parameter s3 = 2'b10; parameter true = 1'b1; parameter false = 1'b0; parameter zero = 2'b00; parameter one = 2'b01; parameter two = 2'b10; parameter three = 2'b11; // build the combination lock Figure 5.30 Combination Lock RTL Model

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// build the combination lock always@ (negedge por or posedge clk) begin // reset the lock if(por==0) begin assign state = s0; assign open = false; end // implement the combination lock else begin case(state) // initial state 0 correct combination xxxx s0: begin assign open = false; if(comboIn == three) assign state = s1; else assign state = s0; end // one correct combination xxx3 s1: begin if(comboIn == two) assign state = s2; else assign state = s0; assign open = false; end // two correct combination xx23 s2: begin if(comboIn == two) assign state = s3; else assign state = s0; assign open = false; end Figure 5.30 cont. Combination Lock RTL Model

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Tutorial 5 - Sequential Circuits - Finite State Machines

// build the combination lock continued // three correct s3: combination x223

begin if(comboIn == one) begin // four correct combination 1223 assign state = s0; assign open = true; end else assign state = s0; end endcase end end endmodule Figure 5.30 cont. Combination Lock RTL Model

5.4

State Machine Reduction

So far in the designs that have been presented, not much attention has been paid to optimization. Certainly, one could argue that with VLSI, FPGAs, Systems on a Chip, or large memory devices etc., why waste time trying to reduce or simplify a design. First, not all designs have such luxuries. Many consumer products stress simplification; the major reason is to save power. The fewer transistors the design uses, the lower the power consumption. Second, even with VLSI and the companion implementation technologies, if a design can be simpler, it is then possible to incorporate more functionality or features in the same real estate. A simpler design is easier to manufacture; even for VLSI. A third motivation is reliability; less complexity means fewer things to fail. A fourth consideration is weight. Whether the design is targeted to be flown in an aircraft or in a satellite or towards a consumer product, additional weight is generally considered to be a cost rather than a benefit. We introduce several different simplification/optimization approaches. Well illustrate how the techniques are applied manually; however, they can be easily written as software design tools. Our focus will be on reducing the complexity of finite state machines. The basic goal when trying to simplify such circuits and systems is to identify and to combine states that have equivalent behavior. Since the number of memory devices is directly related to the number of states, reducing the number of states can help to reduce the number of flip-flops. Its important to keep in mind as we execute the process that the objective is to simplify the design; we are not making trade-offs. When we make trade-

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Tutorial 5 - Sequential Circuits - Finite State Machines

offs, we are potentially eliminating functionality. When we optimize, we are keeping the functionality and improving the design. Equivalent States are defined as those states which, for all input combinations, have States the same set of output values and transition to the same or equivalent states under the same input values. Well examine two alternative algorithms Row matching Implication charts Well begin with row matching.
Equivalent

5.4.1

The Row Matching Algorithm

The general approach under the row matching algorithm is rather straight forward, 1. 2. 3. 4. 5. Start with the state transition table. Identify states with same output behavior. If such states transition to the same next state, they are equivalent. Combine into a single new renamed state. Repeat until no new states are combined.
row matching

To illustrate the technique, we will use an application often found in telecommunications systems for error management, the generation of a parity check bit. The scheme is rather straight forward. A single logical 0 or logical 1 bit is appended to each data word or odd parity block. If odd parity is being used, the total number of one bits (including the parity bit) must be odd. If the data word has odd number of one bits a logical 0 is added; if the data even parity word has an even number of one bits a logical 1 is added. If even parity is being used, the total number of one bits (including the parity bit) must even. If the data word has odd number of one bits a logical 1 is added; if the data word has an even number of one bits a logical 0 is added. Table 5.2 illustrates the odd and even parity bits for a three bit data word.
Table 5.2 Odd and Even Parity for a Three Bit Word Original Data
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Odd Data Parity

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 1 0 1 1 0

Even Data Parity

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1

Well implement the design of a system that accepts a serial data stream as input. On receipt, each incoming data bit is read from the stream and transferred to the output stream. After three data bits have been read and transferred, an even parity bit over the

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Tutorial 5 - Sequential Circuits - Finite State Machines

three bits will be sent to the output and the cycle will repeat for the remainder of the message. Typical incoming and outgoing message streams (with even parity bits inserted) will appear as in Figure 5.31.
B8 B7 B6 B5 B4 B3 B2 B1 B0

Incoming Message Stream P2 B8 B7 B6 P1 B5 B4 B3 P0 B2 B1 B0

Bi = Data Pi = Parity

Outgoing Message Stream

Figure 5.31 Typical Data Stream With Even Parity Bits Inserted

With any design, its important to understand the requirements, scope, and complexity of the design before starting. Understanding the scope enables one to rapidly assess the solution at the end of the process and to identify potential problems along the path if the design appears to be becoming too complex. For this system, there are two basic tasks: 1. Counting to three to know when to insert the parity bit and 2. Keeping track of whether an odd or even number of bits have come in. Counting to three requires two flip-flops and keeping track of incoming bits requires one. Thus, the complexity of the design should be no worse than three flip-flops. The full state diagram for such a system is given in Figure 5.32. With fifteen states and therefore four flip-flops, the design appears to exceed the initial complexity estimate.
0 0/0 1/0

1 0/0 1/0 0/0

2 1/0

3 0/0 1/0 0/0

4 1/0 0/0

5 1/0 0/0

6 2 1/0

7 -/0

8 -/1

9 -/1

10 -/0

11 -/1

12 -/0 -/0

13 -/1

14

Figure 5.32 Full State Diagram for an Even Parity Generator

From the state diagram, our first cut at the state table is given in Figure 5.33. In the state table, the rows are segregated into transitions that occur at t0, t1, t2, and t3. We now apply Steps 2..4 of the algorithm. We begin at time t3 and work backwards. States that

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Tutorial 5 - Sequential Circuits - Finite State Machines

occur at different times cannot combined otherwise the inherent history associated with each state in the machine will be lost. This means that states at times t2, and t3, cannot be combined, for example. For the parity generation system, each of the states in the set {7, 10, 12, and 13} and each of the states in the set {8, 9, 11, and 14} have the same next state and same output. The states within each set can be combined into a single state without loosing any information. All references to any states in the first set are replaced by 7a and all references to any states in the second set replaced by 8a.
Present State t = tn Next State t = tn+1 x=0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 3 5 7 9 11 13 0 0 0 0 0 0 0 0

Output Parity x=0

0 0 0 0 0 0 0 0 1 1 0 1 0 0 1

Time

x=1
2 4 6 8 10 12 14 0 0 0 0 0 0 0 0

x=1
0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 t3 t2 t0 t1

Figure 5.33 Full State Diagram for an Even Parity Generator

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Tutorial 5 - Sequential Circuits - Finite State Machines

The state table now reduces to that given in Figure 5.34.

Present State t = tn Next State t = tn+1 x= 0
0 1 2 3 4 5 6 7a 8a 1 3 5 7a 8a 8a 7a 0 0

Output Parity x=0

0 0 0 0 0 0 0 0 1

Time

x=1
2 4 6 8a 7a 7a 8a 0 0

x=1
0 0 0 0 0 0 0 0 1 t3 t2 t0 t1

Figure 5.34 Partially Reduced State Diagram for an Even Parity Generator

The process is repeated for states at time t2. In this case, states in the set {3, 6} and in the set {4, 5} have the same next states and outputs. Thus, they can also be combined. The new state table is now given in Figure 5.35.
Present State t = tn Next State t = tn+1 x=0
0 1 2 3a 4a 7a 8a 1 3a 4a 7a 8a 0 0

Output Parity x=0

0 0 0 0 0 0 1

Time

x=1
2 4a 3a 8a 7a 0 0

x=1
0 0 0 0 0 0 1 t3 t2 t0 t1

Figure 5.35 Partially Reduced State Diagram for an Even Parity Generator

The process is repeated once again at time t1. Nothing can be combined here and thus the process terminates.

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Tutorial 5 - Sequential Circuits - Finite State Machines

The final state table was given in Figure 5.35. The parity system has been reduced from original fifteen states to seven states and the number of flip flops has been reduced from four to three. Both figures are consistent with the initial estimate of the scope of the solution. The functionality of the system remains the same. Put another way, the original design has been replaced by a simpler version yet; the public interface to the system has remained unchanged.

5.4.2

Implication Chart
The second approach that well discuss is called the implication chart algorithm. Well use the same problem that was used for the row matching algorithm. The implication chart algorithm says, 1. 2. 3. Construct the implication chart. There is one square for each pair of states. For each square labeled Si, Sj. If systems outputs for those states differ enter an X in that square. Otherwise write down implied state pairs that must also be merged if Si and Sj are merged. Advance through chart top-to-bottom and left-to-right. If square Si, Sj contains an implied merger between state pair Sm, Sn and that pair labels a square already labeled "X". Then Si, Sj is labeled "X" the implied merger is not allowed. Continue until no new squares are marked with "X". For each remaining unmarked square Si, Sj, these states are equivalent and be merged.
implication chart row matching

4. 5. 6. 7. 8.

Step 1 For the parity generation system, from the states identified in the state table, the impli- implication cation chart in Figure 5.36 elaborates all of the present state pairs. chart
1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 8 9 10 11 12 13

Figure 5.36 Implication Chart for a Sixteen State FSM

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Tutorial 5 - Sequential Circuits - Finite State Machines

Step 2a The reduction begins by first marking all state pairs with incompatible outputs. That is, for example, one output set may require the output to be {0 0} for the two different values of the input data bit as in the case of state 0 and another output set may require the output to be {1 1} as in the case of state 8. Clearly the output cannot satisfy both output values simultaneously, thus, state 0 and state 8 cannot be merged. Their behavior is not equivalent for the same inputs. After completing step 2, the initial set of incompatible states has been identified. These are now reflected in the implication chart in Figure 5.37. Step 2b
1 2 3 4 5 6 7 8 9 10 11 12 13 14

X X

X X

X X

X X

X X

X X

X X

X X

X
0

X
1

X
2

X
3

X
4

X
5

X
6

X
7 8 9

X
10 11

X
12

X
13

Figure 5.37 Implication Chart with Incompatible States Identified

Next all pairs of states are examined and the implications of merging them are identified and noted. That is, additional states, if any, that must also be merged are identified. For example, consider states 0 and 1. If these two states are merged into a single state, the next state entries demand that states (1 and 3) and (2 and 4) must also be merged. Note is made of this by entering the implication into the square 0-1 for states 0 and 1. The step is repeated with all remaining combinations to give the following complete implication chart. The resulting implication chart follows in Figure 5.38. Step 3 Next, all state pairs are examined and the consequences of the implied mergers are assessed. If any of the implied / required mergers has been disallowed, the merger is not permitted. For example, if states (6 and 13) are merged, states (0 and 13) and (0 and 14) must also be merged. The square for (0 and 14) contains an X indicating that such a merger is not allowed; thus, the square for (6 and 13) gets marked with an X.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1,3 2,4 1,5 2,6 1,7 2,8 1,9 2,10 1,11 2,12 1,13 2,14 0,1 0,2 3,5 4,6 3,7 4,8 3,9 4,10 3,11 4,12 3,13 4,14 0,3 0,4 5,7 6,8 5,9 6,10 5,11 6,12 5,13 6,14 0,5 0,6 7,9 8,10 7,11 8,12 7,13 8,14 0,7 0,8 9,11 10,12 9,13 11,13 10,14 12,14 0,9 0,10 0,11 0,12 0,13 0,14

X X
0,1 0,2

X X
0,3 0,4

X X
0,5 0,6

X X
0,7 0,8

X X
0,9 0,10

X X
0,11 0,12

X X
0,13 0,14

X X

X
0,1 0,2 0,1 0,2

X
0,3 0,4 0,3 0,4

X
0,5 0,6 0,5 0,6

X
0,7 0,8 0,7 0,8

X
0,9 0,10 0,9 0,10

X
0,11 0,12 0,11 0,12

X
0,13 0,14 0,13 0,14

X
0

X
1

X
2

X
3

X
4

X
5

X
6

X
7 8 9

X
10 11

X
12

X
13

Figure 5.38 Implication Chart with all Implications Identified

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Tutorial 5 - Sequential Circuits - Finite State Machines

The process is repeated for all squares and associated implications. The completed implication chart now appears in Figure 5.39.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1,3 X 2,4 1,5 X 2,6 1,7 X 2,8 1,9 X 2,10 1,11 X 2,12 1,13 X 2,14 0,1 X 0,2 3,5 X 4,6 3,7 X 4,8 3,9 X 4,10 3,11 X 4,12 3,13 X 4,14 5,7 X 6,8 5,9 X 6,10 5,11 X 6,12 5,13 X 6,14 0,5 X 0,6 7,9 X 8,10 7,11 X 8,12 7,13 8,14 0,7 X 0,8 9,11 10,12 9,13 11,13 X 12,14 X 10,14 0,9 X 0,10 0,11 X 0,12 0,13 X 0,14

X 0,4 X X
0,3 X 0,4

0,3

X X
0,1 X 0,2

X X
0,5 X 0,6

X X
0,7 X 0,8

X X
0,9 X 0,10

X X
0,11 X 0,12

X X
0,13 X 0,14

X X

X
0,1 X 0,2 0,1 X 0,2

X
0,3 X 0,4 0,3 X 0,4

X
0,5 X 0,6 0,5 X 0,6

X
0,7 X 0,8 0,7 X 0,8

X
0,9 X 0,10 0,9 X 0,10

X
0,11 X 0,12 0,11 X 0,12

X
0,13 X 0,14 0,13 X 0,14

X
0

X
1

X
2

X
3

X
4

X
5

X
6

X
7 8 9

X
10 11

X
12

X
13

Figure 5.39 Final Implication Chart

From the chart, its evident that states (4 and 5) can be merged the square is not marked with an X but, if merged, then (9 and 11) and (10 and 12) must also be merged. Similarly, states (3 and 6) can be merged, but, if merged, then (7 and 13) and (8 and 14) must also be merged. Following the mergers, the initial reduced set of states is given as
State 0 State 1 State 2 States (3 and 6) State 3a

State 4a States (7, and 13) State 7a States (8, and 14) State 8a States (10 and 12) State 10a States (9 and11) State 9a
States (4 and 5)

Observe that the following additional mergers are also possible with no implications.
States (7a and 10a) State 7b States (8a and 9a)

State 8b

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The final reduced set of states is given as,

State 0 State 1 State 2 State 3a State 4a State 7b State 8b

Which gives the same reduced state table we found using the row matching algorithm.

5.5

Summary
In this tutorial, we built on the basic concept of the sequential circuit by including input and output capabilities to the designs we studied previously. We examined the state assignment problem and presented several different schemes for assigning values to state variables. Such schemes included binary, Gray, and One Hot encoding. We studied both RTL and structural level models in Verilog for the FSM. We introduced the row matching and implication chart methods for reducing the complexity sequential machines.

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References
Balabanian, N., Carlson, B., Digital Logic Design Principles, John Wiley & Sons, 2001. Brown, S., Vranesic, Z., Fundamentals of Digital Logic with Verilog Design, McGrawHill, 2003. Cheung, J. Bredeson, J., Modern Digital Systems Design, West Publishing Company, 1990. Givonne, D., Digital Principles and Design, McGraw-Hill, 2003. Katz, R. Borriello, G., Contemporary Logic Design, 2nd ed., Pearson Prentice-Hall, Inc., 2005. Mano, M., Digital Design, 3rd ed., Pearson Prentice-Hall, Inc., 2002. Marcovitz, A., Introduction to Logic Design, 2nd ed., McGraw-Hill, 2005. Nelson, V., Nagle, H., Carroll, B., Irwin, J., Digital Circuit Analysis & Design, PrenticeHall, Inc., 1995. Roth, C., Fundamentals of Logic Design, 5th ed., Thomson Brooks/Cole, 2004. Salcic, Z., Smailaglic, A. Digital Systems Design and Prototyping Using Field Programmable Logic, Kluwer Academic Publishers, 1997. Sandige, R., Digital Design Essentials, Prentice-Hall, Inc., 2002. Shiva, S., Introduction to Logic Design, 2nd ed., Marcel Dekker, 1998 Tinder, R., Engineering Digital Design, 2nd ed., Academic Press, 2000. Vahid, F. Digital Design, John Wiley & Sons, 2006. Wakerly, J. Digital Design Principles and Practices, 4th ed., Pearson Prentice-Hall, Inc., 2006.

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