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Lab 1

This document provides instructions for an electrical engineering lab on getting started with an FPGA development board and VHDL coding. The objectives are to become familiar with the FPGA board and software, build and simulate a logic gate using VHDL, and create a macro file for simulation. The procedures outline how to create a new project library, develop a 2-bit AND gate design in VHDL, simulate the design in ModelSim, and save the simulation settings as a macro file for future use.

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Rana Badran
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48 views

Lab 1

This document provides instructions for an electrical engineering lab on getting started with an FPGA development board and VHDL coding. The objectives are to become familiar with the FPGA board and software, build and simulate a logic gate using VHDL, and create a macro file for simulation. The procedures outline how to create a new project library, develop a 2-bit AND gate design in VHDL, simulate the design in ModelSim, and save the simulation settings as a macro file for future use.

Uploaded by

Rana Badran
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Electrical Engineering Department

Module; [ELEC14I02] Digital Design Lab 1 Getting Started with FPGA Advantage Semester 1 (2013/2014)

Objectives:
Become familiar with FPGA Advantage and VHDL coding Build and compile a logic gate and simulate it using modelsim Learn how to create a macro file for the simulation

Equipment:
A computer with FPGAdv installed.

Procedure: A. Getting Started


1) Create new folder in your directory and name it projects 2) Open FGPAdv and create a new library: file new library library name year2_2013browse for you newly created folder ok

B. Creating Required Design Units I. AND gate


1) Select the newly created library from the left pane: file new VHDL Architecture/Entity Design unit and_2bit View name rtl OK

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2) A vhdl file should open for you to code the entity and the architecture of your design. Your final code should look like this:
ENTITY and_2 IS -- Declarations port ( a, b : in std_logic; y : out std_logic); END and_2 ; -- hds interface_end ARCHITECTURE rtl OF and_2 IS BEGIN y <= a AND b; END rtl;

3) Save your file, and close it. Then build it by selecting the simulation flow icon. 4) If the file was successfully built, you should get a screen prompting to start modelsim simulation press OK

C. ModelSim Simulation
1) In the ModelSim window click: View Signals 2) In the signals window, a. Click on the a signal: Edit Force Value: 1, Delay For: 0 Ok b. Click on the b signal: Edit Force Value: 1, Delay For: 0 Ok c. Click on the b signal: Edit Force Value: 0, Delay For: 100 Ok d. Click on the b signal: Edit Force Value: 1, Delay For: 200 Ok Page 2 of 3

e. ViewWaveSignals in region. A window titles wave will open up 3) In the wave window a. Press run several times till u reach about 2400ns b. Press zoom full to see the whole wave c. Your wave should look like the figure below.

4) To save your forces in a macro file: a. Copy set of instructions from the ModelSim force -freeze sim:/and_2/a 0 0 force -freeze sim:/and_2/a 1 200 force -freeze sim:/and_2/b 0 0 force -freeze sim:/and_2/b 1 400 force -freeze sim:/and_2/b 0 800 b. Open the work folder from your library directory and create a new text file (E:\Projects\year2_2013\work) c. Paste the instruction set in the file and save it under the name forces.do If the extension name does not change do the following: i. Open Folder options by clicking the Start buttoncontrol panelappearance and personalizationfolder options ii. Click the view tab and then under advanced settings clear the Hide extensions for known file types check box and then click OK 5) To execute the macro file, restart the simulation by pressing the restart button in the Wave - default window In the modelsim window do the following: click Macro Execute Macro select the forces.do file. Then view the signals and run the simulation.

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