Sensors 2012, 12, 3587-3604; doi:10.

3390/s120303587

sensors
ISSN 1424-8220
www.mdpi.com/journal/sensors
Article
A Voltage Mode Memristor Bridge Synaptic Circuit with
Memristor Emulators
Maheshwar Pd. Sah
1
, Changju Yang
1
, Hyongsuk Kim
1,
* and Leon Chua
2

1
Division of Electronics and Information Engineering, Chonbuk National University,
Jeonju 561-756, Korea; E-Mails: maheshwarsah@hotmail.com (M.P.S.);
ychangju@jbnu.ac.kr (C.Y.)
2
Department of Electrical Engineering and Computer Sciences, University of California,
Berkeley, CA 94720, USA; E-Mail: chua@eecs.berkeley.edu
* Author to whom correspondence should be addressed; E-Mail: hskim@jbnu.ac.kr;
Tel.: +82-63-270-2477; Fax: +82-63-270-3988.
Received: 21 January 2012; in revised form: 12 February 2012 / Accepted: 7 March 2012 /
Published: 14 March 2012

Abstract: A memristor bridge neural circuit which is able to perform signed synaptic
weighting was proposed in our previous study, where the synaptic operation was verified via
software simulation of the mathematical model of the HP memristor. This study is an
extension of the previous work advancing toward the circuit implementation where the
architecture of the memristor bridge synapse is built with memristor emulator circuits. In
addition, a simple neural network which performs both synaptic weighting and summation is
built by combining memristor emulators-based synapses and differential amplifier circuits.
The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.
Keywords: memristor bridge; non-volatile programming weight; neuron; synapse;
synaptic multiplication

1. Introduction
Synaptic multiplications between input signals and weights are key operations in neural networks,
programmable analog vector matrix multiplication and cellular neural networks. Most of the previous
synaptic multiplications are based on the software models [14]. While the flexibility of the
software-based model is excellent, its processing speed represents a serious bottleneck. The digital
OPEN ACCESS
Sensors 2012, 12


3588
accelerating board on which the software version of neural network is a practical option representing a
compromise between limited flexibility and a high speed processing [5,6]. However, this approach
may not be the solution for the problem of bigger size of neural networks.
There have been some research efforts to build artificial synapses (weights) in neural network chip
and analog programmable vector matrix multiplication using CMOS technologies [711]. To
implement the immense amount of neural processing on a chip, extremely high density of integration
technology is needed. This is a very challenging goal and not many successful cases of neural
implementations have been reported so far. The cellular neural network [1216] is one of the
successful implementations of analog multiplication circuits.
Most of the synaptic weights implemented with the conventional technologies are volatile. Also,
synaptic multiplication between input signal and weight is non-linear. Therefore, introducing a new
weighting technology which is nonvolatile and linear is very important for the further development of
neuromorphic engineering.
In 2008, HP announced a successful fabrication of a very compact and non-volatile nano scale
memory called the memristor [17]. It was originally postulated by Chua [18,19] as the fourth basic
circuit elements in electrical circuits. It is based on the nonlinear characteristics of charge and flux. By
supplying a voltage or current to the memristor, its resistance can be altered. In this way, the memristor
remembers information.
Many of recent researches showed the great potential of memristors in the application of
memory, and artificial synapses [2024]. Cantley et al. presented an application of memristor synapse
for the Hebbian learning in spiking neural network [21]. Snider demonstrated a memristor-based self
organized network employing dedicated connections for inhibitory (negative) weighting [22]. For such
application in neural network or cellular neural network, every connection has to be weighted either
positively or negatively.
In [24], we demonstrated the architecture of the memristor bridge circuit which is able to perform
signed synaptic operations. The study was conducted with the mathematical model of the HP
memristor, where the operation of the memristor bridge circuit was verified via software simulation.
This study is an extension of the previous research advancing toward the circuit implementation where
the architecture of the memristor bridge neuron is built with our memristor emulator circuits [25].
Also, a simple neural network which performs both synaptic weighting and summation is built by
combining memristor emulators-based synapses and differential amplifier circuits.
In this paper, the HP TiO
2
memristor model is introduced in Section 2. In Section 3, a memristor
emulator circuit is proposed. Memristor bridge synapses built with memristor emulator circuits are
described in Section 4. Simulation results are presented in Section 5. In Section 6 we present
our conclusions.
2. HP Memristor Models
In HP TiO
2
memristor model [17], an undoped region with highly resistive TiO
2
and doped region
with highly conductive oxygen vacancies TiO
2x
layer are sandwiched between two platinum
electrodes as shown in Figure 1(a). When a voltage or current signal is applied to the device, the
border line between the doped and undoped layers shifts as a function of the applied voltage or current.
Sensors 2012, 12


3589
In consequence, the resistance between the two electrodes is altered. Figure 1(b,c) is the equivalent
circuit and the symbol whose polarity is indicated by a black bar at one end. The defined polarity
indicates that the memristance is decreased (or increased) when current flows from the left (right) side
to the right (left) side of the memristor symbol in Figure 1(c).
Figure 1. (a) Structure of TiO
2
memristor, TiO
2x
and TiO
2
layers are sandwiched between
two platinum electrodes. When a voltage/current is applied, its memristance (resistance of
the memristor) is altered; (b) equivalent circuit and (c) symbol of the memristor.
D
w
TiO2-x TiO2
A
V
R
ON
R
OFF

(a) (b) (c)
Let w be the thickness of the doped area, D be the thickness of the two layers of TiO
2
memristor.
Let
ON
R
and
OFF
R
denote the minimum resistance and the maximum resistance values, respectively.
Then, the relation between the voltage and the current is given by:
( ) ( )
( ) 1 ( )
ON OFF
w t w t
v t R R i t
D D
| | | |
= +
| |
\ . \ .

(1)
where memristance
( ) ( )
( ) 1
ON OFF
w t w t
M t R R
D D
| |
= +
|
\ .
and w(t)/D is defined as the state variable. In the
TiO
2
memristor [17], the rate of change of the state variable is defined as a function of current i; namely:
( )
( )
ON
V
R dw t
i t
dt D
=
(2)
where
v

is the dopant mobility. This model is called a linear drift model, since the velocity of the
width is linearly proportional to the current. Integrating Equation (2):
0 0
0
( ) ( ) ( ).
t
ON ON
V V
R R
w t w i t dt w q t
D D
= + = +
}

(3)
From Equations (1) and (3), the memristance M(t) can be written as:
0
( ) 1 1 1 ( )
2
OFF
R
w R R
ON v ON ON
M t q t
D R R
OFF D
OFF
R


| | ( | |

| + ( ` |
|
|
(
\ . \ . )
=

(4)
If w
0
/D<<1 and R
ON
<<R
OFF
the expression of M(t) is simplified as :
1 ( ) .
2
( )
OFF
R
v ON
q t
D
M t R



`

)
~

( ) ( ),
OFF
M t R Kq t =
where 2
.
v ON
OFF
K
R
R
D

=

(5)
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3590
From Equation (1):
( ) ( ) ( ) ( ).
OFF
v t R Kq t i t =
(6)
It follows from Equation (6) that the memristance M(t) decreases when higher voltage is applied to
the non-black bar side than that of black bar side in Figure 1(c). Similarly, the memristor is called
incrementally biased when a higher voltage is applied at the black bar side than that of non-black bar
side in Figure 1(c). With this bias, the current-voltage relationship is given by:
( )
0
( ) ( ) ( ) v t R Kq t i t = +
(7)
and the memristance M(t) increases as
( ) ( ).
o
M t R Kq t = +

Detailed descriptions of incremental and decremental memristors using our emulators circuits are
provided in Section 3.
3. HP Memristor Emulator Circuit
As of today, memristors are not yet available on the market. In order to study memristor-based
circuit, building memristor emulators is necessary. Two different approaches to build the memristor
emulators are the pure analog circuit-based [25] and the analog-digital mixed-based [26,27]. The
memristor emulator circuit adopted for this work is from [25]. The basic idea implemented to design
the memristor emulator [25] is shown in Figure 2.
Figure 2. Basic concept for implementing the memristor emulator (a) input resistance as a
function of voltage v
x
; (b) equivalent circuit.
+
-
R
f
v
x
R
s
v
in
R
in
i
in
i
in

R
s
v
x
V
m
R
in
i
in

(a) (b)

In the figure, the voltage at the input terminal is,
in s in x
v R i v = +

(8)
where i
m
is the input current, R
s
is a resistance at the inverting input terminal and v
x
is the voltage
applied to the positive terminal of the op Amp.
Assume that the voltage v
x
is proportional to input current
in
i , then:
( )
in s in in s in
v R i mi R m i = + = +
(9)
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3591
where m is a proportionality coefficient and v
x
= mi
in
. Equation (9) implies that the input resistance of
the circuit is R
s
+ m. If we can control m

so that, it is time integral of the input current i
in
, then, the
circuit in Figure 2 acts as a memristor.
To emulate v
x
in Equation (9), three devices (a capacitor, a resistor, and a voltage multiplier) are
utilized, in which the voltage from the capacitor and that from the resistor are multiplied using a voltage
multiplier.
The memristor emulator needs to be prepared in two different connections such as decremental and
incremental emulators, separately.
Figure 3 shows the schematic of the incrementally biased memristor emulator where memristance
increases when a positive voltage v
in
applied at the input terminal. The input voltage applied at a
memristor emulator is converted into an input current i
in
with a resistor R
s
and op Amp U0 via the
virtual ground constraint. Since the current i
in
is used at several places, its replicas are generated using
current mirrors. Observe that a current mirror copies single directional current only. For bi-directional
(positive and negative) currents, i
in
must be separated into a positive part and a negative part and
processed separately at different parts of the circuit. In the circuit of Figure 3, the positive part of the
current, duplicated by a current mirror MN0 and MN2 is fed into a resistor R
T
and a capacitor C by
current mirror MP3 and MP4 with couple of MP1 respectively. On the other hand, MP0 and MP2 acts
as the negative part of current mirror that flows out from resistor R
T
and capacitor C by current mirror
MN3 and MN4 which are coupled with MN1.
Figure 3. incrementally-biased memristor emulator circuit (a) memristor emulator circuit;
(b) a schematic of memristor emulator.
Vdd
Vss
Rs
RT
U0
U1
C
MN0 MP0
MP1
MP2
MP3 MP4
MN1
MN2
MN3 MN4
SW0
v
in
i
in
v
x
U3
R
AD
R
AD
R
AD
R
AD
U2

(a)

(b)

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3592
One of the distinguished features of a memristor is the capability of keeping the programmed
information for a long time until new programming inputs are presented. The charge stored at
capacitor C is for the programmed information in the memristor emulator. To avoid discharging during
the period when an input signal does not exist, the path to the output terminal is connected to a Mosfet
buffer U1. The switch S
W0
is initially closed to reset the capacitor voltage to zero. When a voltage
pulse is applied through the input terminal of the emulator circuit, the switch is opened. Therefore the
capacitor voltage starts to charge from zero voltage to certain level.
In Figure 3, the capacitor produces a voltage
C
v by integrating the current i
in
, and the resistor R
T

produces a voltage proportional to the current i
in
:
1
,
C
C in
q
v i dt
C C
= =
}

(10)
and:
.
R T in
v R i =
(11)
These two voltages are multiplied by a voltage multiplier. The output voltage v
x
of the voltage
multiplier is given by:
.
C
x T in
q
v R i
C
=
(12)
Therefore, the input voltage v
in
is:
,
C
in s T in
q
v R R i
C
| |
= +
|
\ .

(13)
where the memristance M(t) is:
( ) .
C
s T
q
M t R R
C
| |
= +
|
\ .

(14)
From Equation (14), when a positive pulse is applied at the input terminal, the resistance increases
proportional to the time integral of input current with R
s
, we call this configuration the incrementally
biased memristor which corresponds to the voltage state where the higher voltage is applied at the
black bar side of Figure 1(c).
On the contrary, if a higher voltage is applied to the non-black bar side, then, the memristance is
decreased. We call this configuration the decrementally biased memristor. By adding a voltage inverter
after the voltage multiplier as shown in Figure 4, the decrementally biased memristor can be
implemented. The input voltage in the decrementally biased memristor is given by:
'
.
C
in s T in
q
v R R i
C
| |
=
|
\ .

The resultant memristance M(t) of the decremental memristor is:
' '
'
( ) ( ) 1 ( ) .
T T
s s
s
R R
M t R q t R q t
C CR
| |
= =
|
\ .

(15)

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3593
Figure 4. Decrementally-biased memristor emulator circuit (a) memristor emulator circuit;
(b) a schematic of memristor emulator.
Vdd
Vss
R's
RT
U0
U1
C
MN0 MP0
MP1
MP2
MP3 MP4
MN1
MN2
MN3 MN4
SW0
v
in
i
in
v
x
R
AD
U3
R
AD
R
AD
R
AD
U2

(a)

(b)

4. Memristor Neural Circuit Built with Memristor Emulators
The memristor bridge synapse circuit [24] is composed of four memristors as shown in Figure 5. In
this study, the architecture of the memristor bridge synapse is built with memristor emulator circuits.
4.1. The Memristor Bridge Synapse
When a positive or negative strong pulse v
in
is applied at the input terminal of the memristor bridge
synapse in Figure 5, the memristance of each memristor is increased or decreased depending upon
its polarity.
When a positive pulse is applied at input terminal of Figure 5, the memristances of M
1
and M
4

(which are decrementally-biased) decrease. On the other hand, the memristances of M
2
and M
3
(which
are incrementally-biased) will increase. It follows that the voltage v
A
at node A (with respect to
ground) increases while the voltage v
B
at node B decreases. If the pulse width is wide enough, the
output voltage V
out
varies gradually from negative to positive voltage.
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3594
Figure 5. Memristor based synaptic circuit in [24]. It is assumed that M
1
and M
4
are
decrementally biased memristor while M
2
and M
3
are incrementally biased memristors.
v
in
Vout
+

A
B
M
1
M
2
M
3
M
4
+

V
M
2
+

V
M
4
+

V
M
1
+

V
M
3
+

On the other hand, if a negative pulse is applied, when M
1
and M
4
are minimum and M
2
and M
3
are
are their maximum state respectively, then, M
1
and M
4
vary to higher memristance and M
2
and M
3
go
to lower value. It follows that the output voltage V
out
varies gradually from positive to negative
voltage. In consequence, the weight is able to be programmed with any weights in the range from 1 to
+1 including zero using appropriate duration of pulse.
Let v
in
be the input voltage pulse. Also, let V
M1
, V
M2
, V
M3
, and V
M4
be the voltages across memristor
M
1
, M
2
, M
3
, and M
4
respectively. Then the voltage at each memristor at time t is:
1
1
1 2
,
M in
M
v v
M M
=
+

(16)
2
,
2
1 2
M in A
M
v v v
M M
= =
+

(17)
3
3
3 4
,
M in
M
v v
M M
=
+

(18)
4
4
3 4
,
M in B
M
v v v
M M
= =
+

(19)
where M
1
, M
2
, M
3
, and M
4
denote the corresponding memristance values of the memristors at time t,
as in Figure 5.

The

output voltage V
out
of the memristor bridge circuit is equal to the voltage difference between
terminal A and terminal B; namely:
2 4
1 2 3 4
in
M M
V v v v
out A B
M M M M
| |
|
= =
| + +
\ .

(20)
where v
A
and v
B
corresponds to the voltages v
M2
and v
M4
, respectively.
Equation (20) can be rewritten as a relationship:
,
in
V v
out
=
(21)
where
2 4
1 2 3 4
M M
M M M M
=
+ +
represents the synaptic weighting factor of the memristor bridge synapse.
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3595
4.2. Memristor Bridge Synaptic Circuit with Memristor Emulators
The memristor bridge circuit in Figure 5 can be built with memristor emulators which are described
in Section 3. In the memristor bridge synapse circuit, the serial connection of two memristors M
1
and
M
2
are parallel to other serially connected memristors M
3
and M
4
.
When a voltage pulse is applied at serially connected memristors, the input voltage is distributed to
every memristor according to the voltage law so that the sum of each memristor voltage is equal to the
input voltage like in ordinary resistors.
Figure 6 illustrates the memristor bridge synaptic circuit using four memristor emulators. In this
architecture, the input current of the first memristor emulator M
1
is replicated by a current mirror and
fed to the second memristor emulator M
2
to produce its voltage in the memristor emulator. The voltage
produced in the second emulator is added to the first emulator with an analog voltage adder. Therefore,
the sum of the individual voltage across each serially connected memristor equals to the input voltage.
Figure 6. Schematics of memristor emulator-based synaptic circuit corresponding to the
synaptic structure of Figure 5.
-
+
+
-
R
AD
R
AD
x
R
T
V
c2
V
R2
i
in1 i
in1
+
-
R
f
R
s
iin1
iin1
R
AD
R
AD
-
+
+
-
R
AD
R
AD
x
R
T
V
c1
V
R1
V
c1
*V
R1

i
in1 i
in1
+
-
R
f
R'
s
iin1
iin1
R
AD R
AD
V
c2
*V
R2

C
C
v
in
iin1
-
+
+
-
R
AD
R
AD
x
R
T
V
c3
V
R3
i
in2 i
in2
+
-
R
f
R
s
iin2
iin2
R
AD
R
AD
V
c2
*V
R3

C
iin1
-
+
+
-
R
AD
R
AD
x
R
T
V
c4
V
R4
V
c4
*V
R4

i
in2 i
in2
+
-
R
f
iin2
iin2
R
AD R
AD
C
iin2
M
1
M
2
M
3
M
4
iin
v
A
B
v
B
A
R'
s


Sensors 2012, 12


3596
4.3. Synaptic Multiplication
After the weight setting, the synaptic multiplication between input pulse and weight can be
performed by applying a pulse with very narrow width. If the weight is set as in Equation (21), the
synaptic multiplication (
sm
V ) between input pulse(
S
V ) and weighting factor () is:
.
sm out s
V V V = =
(22)
Note that the effect of memristance change is negligible for very narrow pulse signal V
s
. Therefore,
the weighting factor is constant and output is the linear multiplication between the input pulse and
weighting factor . Thus, the memristor bridge circuit acts as a synapse. In case that the memristance
change (drift) with weighting operation is really the problem, a doublet circuit can be used to suppress
the effect of the memristance change (drift) [28].
The differential amplifier as shown in Figure 7 is used for voltage to current converter. The output
current across differential amplifier for input signal V
s
is given as:
0
2 2
m sm m s
g V g V
I

= =
(23)
where g
m
is the transconductance of Mosfet.
Figure 7. Memristor bridge synaptic circuit. The memristor bridge on the left performs the
weighting operation while the differential amplifier on the right performs the voltage to
current conversion.
M1
vA
vB
M2
M3
M4 Vs
Vb
V+ V-
V
ss
y
+
y
-
I
0 I
0

Note that the same input terminal in Figure 7 is shared by the signal v
in
for synaptic weight
programming and the synaptic input signal V
s
for weight processing. The two different kinds of signals
are discriminated by being assigned at different time slots.
4.4. Memristor Synapse-Based Neural Circuit
The synaptic multiplication in neural network is very important in neuromorphic engineering,
programmable analog vector matrix multiplication and CNN circuits [10,11,16].
Figure 8(a) is a general single layered neural network. The circuit of the memristor synapse-based
neuron using memristor bridge and differential amplifier is shown in Figure 8(b). The synaptic
Sensors 2012, 12


3597
multiplications among input pulses and memristor-based weights are conducted in the multiple
memristor bridge circuits and the results of the multiplications are summed by simply tying the output
terminals in a neuron cell. The sum of the currents is then converted back into a voltage using the load
circuit R
L
.
Figure 8. Neural circuit (a) Block diagram of single layer neural network (b) Memristor
synapse-based neural circuit.
V
s1
Out
V
s2
V
sk
1

n
1
n
2
n
k

(a)
Vb
y
+
y
-
V+ V-
V
A1
V
B1
Vb
y
+
y
-
V+ V-
V
A2
V
B2
V
dd
V
0
V
sk
R
L
V
s2
1

A
B
M2
M4
M1
M3
A
B
M2
M4
M1
M3
I
0
I
0K
I
01

(b)


Sensors 2012, 12


3598
The total current (I
0
) at the neuron output is:
0 01 02 03 0
................ .
k
I I I I I = + + +

where I
0k,
is the output current across differential amplifier corresponding to input voltage pulse V
sk
for
k th synapse.
The final output voltage across the resistor
L
R is given as,
| |
0 0 01 02 0
......... .
L k L
V I R I I I R = = + +
(24)
From Equations (23) and (24), the output voltage across R
L
is,
| |
0 1 1 2 2
.........
2
m L
s s n sk
g R
V V V V = + +
(25)
where
k
is the weighting factor of the kth synapse.
Therefore, the output voltage of the neuron is given as:
0
1
.
2
n
m L
k sk
k
g R
V V
=
=

(26)
Equation (26) reveals that, the output voltage at load resistor R
L
, is the weighted sum of the product
of each input voltage pulse and programming weight.
5. Simulations
In this paper, the memristor bridge architecture [24], is built with memristor emulator circuit. The
parameters are chosen as realistic value as possible, so the minimum memristance R
ON
(R
S
) = 100 ,
and the maximum memristance R
OFF
(R'
s
) = 16 K, are taken from those of Stanley Williams real
memristor [17]. Also, capacitance C and resistance R
T
employed for the memristor emulator are 0.1 F
and R
T
= 4 K, respectively. The architecture has been simulated in PSPICE with input voltage pulse
1 V and power supply 5 V.
For the weight programming, strong wide pulses were applied to change the state of memristor and
very narrow pulses (3 ns) were used for synaptic multiplication. The PSPICE simulations were
conducted for the weight programming and synaptic multiplication of the memristor emulator-based
bridge synapses.
5.1. Weight Programming
Simulations for the weight programming of the memristor emulator-based synaptic circuit as in
Figure 6 have been conducted. The synaptic weights were programmed with 1 V input pulses.
Figure 9(b) and Figure 9(c) show the memristance variation and the voltage across each memristor in
the memristor bridge circuit for a positive and negative wide pulse.
We assume that the initial memristance of the memristors M
1
= M
4
and M
2
= M
3
are
16 K(maximum) and 100 (minimum) respectively. Since the polarity of M
1
and M
4
are opposite to
that of M
2
and M
3
, the memristances M
1
and M
4
decrease, while those of M
2
and M
3
increase for
positive pulse input, as shown in Figure 9(b). Thus, the voltage v
A
increases while v
B
decreases as
shown in Figure 9(c). When M
1
= M
2
= M
3
= M
4
, v
A
equals to v
B
and the output voltage becomes zero.
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At this state, the synaptic weight is zero. When M
1
or M
4
is less than M
2
or M
3
, the voltage v
A
is
greater than v
B
. If the pulse width is sufficiently wide, the voltages at v
A
and v
B
reach to +1 V and 0 V,
respectively. Note that each memristor pair (M
1
, M
4
) or (M
2
, M
3
) is with opposite polarity. Therefore,
the composite memristance of each memristor pair is constant.
Similarly, when M
1
, M
4
and M
2
, M
3
are in minimum and maximum state respectively, then a
negative wide voltage pulse is applied to the memristor bridge synapse, so that the memristance
of memristor M
1
, M
4
and M
2
, M
3
are moved to the opposite direction compare to the positive case
input pulse. In this case, voltage v
A
moves toward 0V and that of v
B
moves toward 1 V as shown
in Figure 9(c).
Figure 9. Variation of memristance and voltages (v
A
, v
B
) when positive and negative pulses
are applied to the emulator-based memristor bridge synapse (a) positive and negative input
voltage pulses; (b) memristance variations; (c) voltage variations at v
A
and v
B
.
Positive Pulse Negative Pulse
M
1
and M
4
M
2
and M
3
v
A
v
B

(a)
(b)
(c)
Time
1.0V
-1.0V
0V
20 K
10 K
0 K
1.0V
-1.0V
0V
200ms 205ms 210ms 214ms
Balanced
State
Balanced
State
Balanced
State
V
o
l
t
a
g
e
M
e
m
r
i
s
t
a
n
c
e
V
o
l
t
a
g
e

The linearity of the weight programming of the memristor emulator-based memristor bridge
synapse has been tested by applying wide positive and negative pulses. The weight values were
computed by measuring the output voltages of the memristor bridge circuit while known input voltages
were applied, as described in Section 4.1 and 4.2. The results of circuit simulations for the synaptic
weighting are shown in Figure 10.
As seen in this simulation result, synaptic weight () can be changed toward positive
(from 1 to +1) and negative direction (+1 to 1) by a positive pulse and negative pulse, respectively.
Observe that the programmed weight () is almost linearly proportional to the width of the input pulse.
The linearity of synaptic weight programming in the memristor bridge comes from the complementary
action of the back-to-back memristors at each branch of the memristor bridge circuit.
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3600
Figure 10. Weight variations of the memristor bridge circuit while positive and negative
pulses are applied (a) positive and negative input pulses; (b) weight variations during each
pulse period.
1.0
-1.0
0
(b)
Time
200ms 205ms 210ms 214ms
1.0V
0V
-1.0V
(a)
Positive Pulse Negative Pulse
Balanced
State
V
o
l
t
a
g
e
W
e
i
g
h
t
(

)

5.2. Synaptic Multiplication
Simulations of the synaptic weight processing were also conducted with our memrisor
emulator-based bridge synapse. Figure 11(b) shows the linearity of the relationship between the input
voltages, and the output of the memristor emulator-based bridge synapse. The weighting factor is in
the range [0.1,0.1] when synaptic input range is [1,1] V. The performance of the conventional
analog multiplication (synaptic weight) circuit employed in the programmable analog vector matrix
multiplication and CNN [10,16] is shown in Figure 11(a). As in the Figure 11(a), the linear region on
the function of input-output relation is quite narrow and the intervals between graphs are not quite
uniform. However, in the case of memristor bridge synapse, the linear regions are very wide and the
intervals between graphs are uniform as in Figure 11(b). The linearity of the memristor bridge synaptic
circuit comes from the linear weight assignment at the memristor bridge synapse and the operation at
the middle of the memristor dynamic range.
Figure 11. Synaptic multiplication with (a) Gilbert multiplier-based circuit [10,16];
(b) memristor based circuit.
O
u
t
p
u
t
(
V
)
5.000 8.000
Input(V)
-500.0
500.0
E-03
100.0
/div
0
.3000/div

(a)
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3601
Figure 11. Cont.

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-300
-200
-100
0
100
200
300
input(V)
O
u
t
p
u
t
(
m
V
)

(b)
5.3. Memristor Synapse-Based Neuron
A single layer neuron with two input terminals as in Figure 8(a) has been built with the proposed
memristor emulator-based synapse circuit. Two different kinds of sinusoidal voltage signals were
sampled by doublet pulses and applied to the memristor synaptic circuits. Figure 12(ae) are input
voltage signals, weighted voltage signals of Figure 12(a,b) with weighting values of = 0.25 and 0.1,
and weighted sum appeared across R
L
where R
L
was 10 K.
Figure 12. Operations of the memristor emulator-based neuron. Input signals sampled with
doublet pulses from two different sinusoidal signals were applied to the memristor bridge
synapses, (a) input voltage signal for = 0.25; (b) input voltage signal for = 0.1;
(c) weighted voltage signals with = 0.25; (d) weighted voltage signals with = 0.1 and
(e) weighted sum appeared at the output of the neuron.
0 20n 40n 60n 80n 100n
0
-1V
1V
Time
V
o
l
t
a
g
e
-1V
1V
V
o
l
t
a
g
e

0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n
0
-100m
-200m
100m
200m
Time
V
o
l
t
a
g
e
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n
0
-100m
100m
Time
V
o
l
t
a
g
e

0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n
0
-500m
500m
Time
V
o
l
t
a
g
e

(a)
(b)
(c)
(d)
(e)
0

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3602
Figure 12. Cont.
0 20n 40n 60n 80n 100n
0
-1V
1V
Time
V
o
l
t
a
g
e
-1V
1V
V
o
l
t
a
g
e

0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n
0
-100m
-200m
100m
200m
Time
V
o
l
t
a
g
e
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n
0
-100m
100m
Time
V
o
l
t
a
g
e

0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n
0
-500m
500m
Time
V
o
l
t
a
g
e

(a)
(b)
(c)
(d)
(e)
0

The use of doublet signals [28] is aimed at preventing the memristances from unwanted drifting.
For the subsequent processing with non-memristor circuits, each doublet pulse signal needs to be
converted to a singlet pulse. This can be achieved by sampling the output signal at every first pulse
period of each doublet. The simulation result shows that the proposed memristor synapse circuit
performs synaptic action excellently without significant distortion.

6. Conclusions
This paper is the extension of our previous work on memristor bridge synapses [24]. In this paper
the mathematical model-based memristor bridge synapse of the previous work is built with memristor
emulator-based synapse circuits.
Simulations for the weight programming were performed with memristor emulator-based bridge
synapse circuit. The programmed weights were almost linearly proportional to the width of the input
pulses. The linearity of weight programming in the memristor bridge synapse comes from the
complementary action of the back-to-back memristor pair of the memristor bridge synapse. The
simulations of synaptic multiplication between programmed weight and input signal also was conducted.
It showed an excellent linearity compared to that of the conventional Gilbert multiplier-based circuit. In
the simulation of a single layer neuron, the proposed memristor-based neural circuit performs both
synaptic weighting and summing actions very well without significant distortion.
There are several benefits with the proposed memristor synapse circuit over the conventional
circuits. The number of transistors required for the memristor based synaptic circuit is three, while that
of Gilbert multiplier-based synaptic circuit is seven. Considering the fact that the total size of four
memristors with the proposed circuit is less than that of a single transistor, the size benefit of the
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3603
proposed synaptic circuit is obvious. Also, non-volatility as memory and excellent linearity in synaptic
operation are additional benefits of the proposed memristor synaptic circuit.
Acknowledgments
This work was supported in part by the National Research Foundation of Korea (NRF) grant
(No. 2010-0006871) and the US Air Force grant number FA9550-10-1-0290.
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2012 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article
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(http://creativecommons.org/licenses/by/3.0/).