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VHDL Question Bank

This document contains questions and answers related to VHDL concepts. It includes definitions of terms like deferred constant, data objects, purpose of process statement in behavioral modeling. It also provides programs for logic gates like NAND, NOR, T-flip flop using behavioral and structural modeling. Programs for 4-bit down counter, multiplexer using if-then-else statement and full adder using behavioral and structural modeling are also included.

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Sugam Kataria
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586 views5 pages

VHDL Question Bank

This document contains questions and answers related to VHDL concepts. It includes definitions of terms like deferred constant, data objects, purpose of process statement in behavioral modeling. It also provides programs for logic gates like NAND, NOR, T-flip flop using behavioral and structural modeling. Programs for 4-bit down counter, multiplexer using if-then-else statement and full adder using behavioral and structural modeling are also included.

Uploaded by

Sugam Kataria
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as RTF, PDF, TXT or read online on Scribd
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QUESTION BANK DCS

Q-1 Define deferred constant. Sol-1 Deferred constant is a constant whose value is not specified & declared in a package. Q-2 Differentiate between si na! " constant. Sol-2 Signal is an object belonging to the signal class holds a list of values which include the current values of a signal & a set of possible future values that are to appear on the signal. Constant is an object of constant class & holds a single value of given type. Q-# $rite a %ro ra& for nand ate 'sin dataf!ow &ode!in . Solentity nand2 is port!a"b#in std$logic% c#out std$logic&% end nand2% architecture nand$data of nand2 is begin b'( not!a and b&% end nand$data%

Q-( Define data ob)ects. Sol-) * data object holds a value of a specified type. +t is created by ,eans of an object decalration. +t has four classes- constant" variable" signal & file. Q-* $rite a %ro ar& of nor ate 'sin Be+a,iora! &ode!in Sol-entity nor2 is port!a"b#in std$logic% c# out std$logic&% end nor2% architecture nor$beh of nor2 is begin process!a"b& begin if!!!a(./.& and !b(.1.&& or !!a(.1.& and !b(./.&& or !!a(.1.& and !b(.1.&&& then c'( 0/.% elsif!!a(./.& and !b(./.&& then c'( 01.%

end nor$beh% Q-- Define t+e %'r%ose of %rocess state&ent in Be+a,iora! &ode!in Sol-1 * process state,ent contains se2uentail state,ents that describes the functionality of a portion of an entity in se2uential ter,s. Q-. $rite a %ro ra& of /'!! Adder 'sin Be+a,iora! 0ode!in Sol-3 entity full$adder is port !a"b"c# in std$logic% su,"carry# out std$logic&% end full$adder% architecture fa$beh of full$adder is begin process!a"b"c& begin if!a(./. and b(./. and c(./.& then su,'( 0/.% carry '(./.% elsif!a(./. and b(./. and c(.1.& or !a(./. and b(.1. and c(./.& or !a(.1. and b(./. and c(./.& then su,'( 01.% carry'(./.% elsif !a(./. and b(.1. and c(.1.& or !a(.1. and b(./. and c(.1.& or !a(.1. and b(.1. and c(./.& or !a(.1. and b(.1. and c(.1.& then su,'(./.% carry'(.1.% end if% end process% end fa$beh% Q-1 $rite a %ro ra& of T f!i%-f!o% 'sin Be+a,iora! 0ode!in Sol-4 entity 566 is port !5" Clk# in std$logic% 7# buffer std$logic&% end 566% architecture 566$beh of 566 is begin process !Clk& begin if !Clk.event and Clk(.1.& then

if !5(.1.& then 7 '( not !7&% else 7 '( 7% end if% end process% end 566$beh% Q-2 $rite a %ro ra& of S3 4atc+ 'sin str'ct'ra! 0ode!in Sol-8 entity S9 is port ! S:5" 9:S:5# in bit% 7" 7;*9# inout bit&% end 9S% architecture struct of 9S is co,ponent <*<D2 port !*" ;# in bit% C# out bit&% end co,ponent% begin =1# <*<D2 port ,ap !S:5" 7;*9" 7&% =2# <*<D2 port ,ap !7" 9:S:5" 7;*9&% end struct% Q-15 $rite a %ro ra& of /'!! adder 'sin two +a!f adders and or ate Sol-1/ entity f$a is port!p"2"r# in std$logic% su,"cout# out std$logic&% end f$a% architecture f$a of f$a is co,ponent half$adder port !a"b# in std$logic% su,"carry# out std$logic&% end co,ponent% co,ponent or2 port!a"b#in std$logic% c# out std$logic&% end or2% signal s1"c1"c2# bit% begin ha1# half$adder port,ap!p"2"s1"c1&% ha2# half$adder port,ap!s1"r"su,"c2&% o1# or2 port,ap!c1"c2"cout&% end f$a%

Q-11 $rite a %ro ra& of( bit '%-down co'nter Sol-11 entity counter is
port(a, clr, up_down : in std_logic; q : out std_logic_vector(3 downto 0)); end counter; architecture beh of counter is signal tmp: std_logic_vector(3 downto 0); begin process (a, clr) begin if (clr !"!) then tmp # $0000$; elsif (%!event and % !"!) then if (up_down !"!) then tmp # tmp & "; else tmp # tmp ' "; end if; end if; end process; q # tmp; end beh;

Q-12 $rite a %ro ra& of (61 &'!ti%!e7er 'sin if t+en e!se state&ent Sol-12 entity ,u> is port !a" b" c" d # in std$logic% sel # in std$logic$vector !1 downto /&% ? # out std$logic&% end ,u>% architecture ,u>$beh of ,u> is begin process !a" b" c" d" sel& begin if !sel ( @//@& then ? '( a% elsif !sel ( @/1@& then ? '( b% elsif !sel ( @1/@& then ? '( c% else ? '( d% end if% end process% end ,u>$beh% Q-1# $rite a %ro ra& of /'!! Adder 'sin Str'ct'ra! 0ode!in Sol-1 entity full$adder is port !a"b"c# in std$logic% su,"carry# out std$logic&% end full$adder% architecture fa$struct of full$adder is

co,ponent and2 port!p"2# in bit% r# out bit&% end co,ponent% co,ponent or port!l","n# in bit% o# out bit&% end co,ponet% co,ponent >or2 port!s"t# in bit% y# out bit&% end co,ponent% signal s1"s2"s "s)# bit% begin >1# >or2 port ,ap!a"b"s1&% >2# >or2 port ,ap!s1"c"su,&% a1# and2 port ,ap!a"b"s2&% a2# and2 port ,ap!b"c"s &% a # and2 port ,ap!a"c"s)&% o1# or port ,ap! s2"s "s)"carry&% end fa$struct% Q-1( $+at is t+e %'r%ose of si na! dri,ers in 89D4. Sol-1) *signal driver holds its current value & all its future values as a se2uence of one or ,ore transactions where each transaction identifies the value to appear on the sihnal along with the ti,e at which the value is to appear. Q-1* Define b!oc: state&ent. Sol-1- * block sate,ent is a concurrent stste,ent . +t is used for three ,ajor purposes# 1. 5o disable signal drivers by using guards. 2.5o li,it scopeof declarations " includingsignal declarations. . 5o represent a portion of a design.

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