VHDL PROGRAMS COLLECTION
Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.
library ieee;
use ieee.std_logic_1164.all;
entity priority is
port ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));
end priority;
architecture archi of priority is
begin
code <= "000" when sel(0) = '1' else
"001" when sel(1) = '1' else
"010" when sel(2) = '1' else
"011" when sel(3) = '1' else
"100" when sel(4) = '1' else
"101" when sel(5) = '1' else
"110" when sel(6) = '1' else
"111" when sel(7) = '1' else
"---";
end archi;
Following is the VHDL code for a 3 to 8 line decoder.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
architecture archi of dec is
begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";
end archi;
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Following is the VHDL code for a 3 to 8 line decoder.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
architecture archi of dec is
begin
res <= "11111110" when sel = "000" else
"11111101" when sel = "001" else
"11111011" when sel = "010" else
"11110111" when sel = "011" else
"11101111" when sel = "100" else
"11011111" when sel = "101" else
"10111111" when sel = "110" else
"01111111";
end archi;
Following is the VHDL code for a 4-to-1 1-bit MUX using an If statement.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
if (s = "00") then o <= a;
elsif (s = "01") then o <= b;
elsif (s = "10") then o <= c;
else o <= d;
end if;
end process;
end archi;
Following is the VHDL code for a 4-to-1 1-bit MUX using a Case statement.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d : in std_logic;
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s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
case s is
when "00" => o <= a;
when "01" => o <= b;
when "10" => o <= c;
when others => o <= d;
end case;
end process;
end archi;
Following is the VHDL code for a 4-to-1 1-bit MUX using tristate buffers.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (3 downto 0);
o : out std_logic);
end mux;
architecture archi of mux is
begin
o <= a when (s(0)='0') else 'Z';
o <= b when (s(1)='0') else 'Z';
o <= c when (s(2)='0') else 'Z';
o <= d when (s(3)='0') else 'Z';
end archi;
Following is the VHDL code for a 3-to-1 1-bit MUX with a 1-bit latch.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;
architecture archi of mux is
begin
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process (a, b, c, d, s)
begin
if (s = "00") then o <= a;
elsif (s = "01") then o <= b;
elsif (s = "10") then o <= c;
end if;
end process;
end archi;
Following is the VHDL code for a logical shifter.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lshift is
port(DI : in unsigned(7 downto 0);
SEL : in unsigned(1 downto 0);
SO : out unsigned(7 downto 0));
end lshift;
architecture archi of lshift is
begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when "10",
DI sll 3 when others;
end archi;
Following is the VHDL code for an unsigned 8-bit Adder.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0));
end adder;
architecture archi of adder is
begin
SUM <= A + B;
end archi;
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Following is the VHDL code for an unsigned 8-bit adder with carry in.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A,B : in std_logic_vector(7 downto 0);
CI : in std_logic;
SUM : out std_logic_vector(7 downto 0));
end adder;
architecture archi of adder is
begin
SUM <= A + B + CI;
end archi;
Following is the VHDL code for an unsigned 8-bit adder with carry out.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0);
CO : out std_logic);
end adder;
architecture archi of adder is
signal tmp: std_logic_vector(8 downto 0);
begin
tmp <= conv_std_logic_vector(
(conv_integer(A) +
conv_integer(B)),9);
SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;
Following is the VHDL code for an unsigned 8-bit adder with carry in and carry
out.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A,B : in std_logic_vector(7 downto 0);
CI : in std_logic;
SUM : out std_logic_vector(7 downto 0);
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CO : out std_logic);
end adder;
architecture archi of adder is
signal tmp: std_logic_vector(8 downto 0);
begin
tmp <= conv_std_logic_vector(
(conv_integer(A) +
conv_integer(B) +
conv_integer(CI)),9);
SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;
Following is the VHDL code for a simple signed 8-bit adder.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity adder is
port(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0));
end adder;
architecture archi of adder is
begin
SUM <= A + B;
end archi;
Following is the VHDL code for an unsigned 8-bit subtractor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity subtr is
port(A,B : in std_logic_vector(7 downto 0);
RES : out std_logic_vector(7 downto 0));
end subtr;
architecture archi of subtr is
begin
RES <= A - B;
end archi;
Following is the VHDL code for an unsigned 8-bit adder/subtractor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity addsub is
port(A,B : in std_logic_vector(7 downto 0);
OPER: in std_logic;
RES : out std_logic_vector(7 downto 0));
end addsub;
architecture archi of addsub is
begin
RES <= A + B when OPER='0'
else A - B;
end archi;
endmodule
Following is the VHDL code for an unsigned 8-bit greater or equal comparator.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compar is
port(A,B : in std_logic_vector(7 downto 0);
CMP : out std_logic);
end compar;
architecture archi of compar is
begin
CMP <= '1' when A >= B
else '0';
end archi;
Following is the VHDL code for an unsigned 8x4-bit multiplier.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult is
port(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(3 downto 0);
RES : out std_logic_vector(11 downto 0));
end mult;
architecture archi of mult is
begin
RES <= A * B;
end archi;
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Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
serial in, and serial out.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;
Following is VHDL code for a 4-bit unsigned up counter with asynchronous clear.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
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Following is the VHDL code for a 4-bit unsigned down counter with synchronous
set.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
tmp <= "1111";
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
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