Features

Utilizes the AVR Enhanced RISC Architecture

High Performance and Low Power Sleep Mode to Conserve Power 120 Powerful Instructions - Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Operating Range: 1.6 to 3.6 Volts Fully Static Operation, 0-33 MHz (0.5 micron), 0-45 MHz (0.35 micron) Seven External Interrupt Sources AVR Scalable Test Access Interface Test Vectors for >99% Fault Coverage Verilog and VHDL Simulation Models Faster Version can be Created Upon Request

Description
The AVR Embedded RISC Microcontroller Core is a low-power CMOS 8-bit microprocessor based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, it achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR Core is based on an enhanced RISC architecture that combines a rich instruction set with the 32 general purpose working registers. Each of the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The architecture supports high level languages efficiently as well as extremely dense assembler code programs. It also provides any number of external and internal interrupts. The AVR Core is provided in an encrypted netlist format with Verilog and VHDL simulation models, a fully functional test bench and ATPG vectors for >99% fault coverage. It is supported with a full suite of program and system development tools including: macro assemblers, ANSI C Compilers, program debugger/simulators, and in-circuit emulator.

Embedded RISC Microcontroller Core

Rev. 0890A02/99

I/O Configuration
Figure 1. AVR Core I/O Configuration
coreso Scan Test coresi corese Clock cp2 pc inst adr iore iowe ramre ramwe Data Memory ramadr
dbusout dbusin

astacp2 astamode astase astasi astaso ireset cpuwait leavbus lbit12 irqlines irqack irqackad sleepi irqok globint pclden pcld ASTA Test

Program Memory

I/O Registers

AVR CORE

Control

Interrupt

Sleep Control

Watchdog

wdri

Memory Programming

AVR Core

AVR Core
I/O Description
Table 1. I/O Description Name Input/ Output Function Clock Port cp2 Clock Input Any register in the core will update its contents only on the positive edge of cp2. Control Ports When high, ireset causes the core to reset the program counter pc, the status register SREG, and the stack pointer, loading all with zeros ($0000). When ireset is high and leavbus is inactive, zero ($00) is driven on the Data Bus dbusout, and the I/O Write Strobe iowe is held high while the I/O Read Strobe and the Data Memory Strobes (ramre, ramwe) are held low. This allows I/O registers to be reset by reading zero from the Bus. This signal is used to add wait cycles to allow slow memory accesses. When cpuwait is high, the core repeats the current cycle (only for instructions addressing the RAM space such as ld or st). When cpuwait is released, the cycle is executed as normal. For details, refer to the timing diagrams below. This signal is used to control dbusout externally. When high, dbusin is connected directly to dbusout, and all I/O and Data Memory Strobes are held low. Disables lpm and elpm instructions. Program Memory Ports pc [15:0] Program Counter inst [15:0] Program Memory data bus Output Program Memory always returns the instruction stored at the address pointed to. The size of this port determines the program memory size. Instruction from Program Memory is presented to the core, selected by the address on pc address bus. I/O Registers adr [5:0] I/O Register address bus iore I/O Registers read strobe iowe I/O Registers write strobe Output Valid only when accompanied by a strobe on iore or iowe lines. Used only with the 64 I/O memory locations. These locations can be mapped into the regular Data Memory Address Space. The core will then issue an iore or ramre read strobe based on target address. Used only with the 64 I/O memory locations. These locations can be mapped into the regular Data Memory Address Space. The core will then issue an iowe or ramwe read strobe based on target address. Data Memory Ports ramadr [15:0] Data Memory address bus ramre Data Memory read strobe Output Valid only when accompanied by a strobe on ramre or ramwe lines. Used to address the SRAM memory locations. The core will issue an iore or ramre read strobe based on target address.

ireset AVR Core Reset

Input

cpuwait Wait CPU

Input

leavbus leave dbusout lbit12 Logical and between Lock bit 1 and 2

Input

Input

Input

Output

Output

Output

Table 1. I/O Description (Continued) Name ramwe Data Memory write strobe dbusin [7:0] Data Bus Input dbusout [7:0] Data Bus Output Input/ Output Output Input Output Function Used to address the SRAM memory locations. The core will issue an iore or ramre read strobe based on target address. All data transfers use dbusin or dbusout to transfer data into or out of the core. Memory locations are selected by the address on ramadr (Data Memory Address). I/O Register locations are selected by the address on adr. Interrupt Ports irqlines [6:0] Interrupt Request Lines Each interrupt source drives its own dedicated IRQ line into the Core. When the global interrupt bit is enabled, a high level (one) on any interrupt line will push the current pc on the stack. The associated interrupt handler vector address is put in the Program Counter pc before execution is restarted. irqack will go high (one) for one clock cycle to acknowledge the interrupt being executed. This is often used as input to interrupt flags designed to clear when their corresponding interrupt handler is executed. The irqackad lines identify which interrupt is being executed during the same cycle. The address of the interrupt being executed. The address is valid only if the irqack signal is set (one). Sleep Controller Ports sleepi Sleep instruction irqok Interrupt Request OK globint Global interrupts enabled Output Set while executing the sleep instruction. This should cause the sleep controller to stop the clock to the core if sleep mode has been enabled. When in sleep mode (clock stopped), this signal will tell the sleep controller that an interrupt exists which should cause the clock to restart. The sleep controller should start the core clock as soon as possible. This is the current state of the I bit in the Core State Register. This signal is used to qualify wake-up from power-down by external interrupts. Memory Programming Ports pclden enable pc load pcld [1:0] Load Program Counter Input Input Enable pc load with pcld signals. Load Program Counter pc from dbusin if pclden is active. pcld [1] load high byte, pcld [0] load low byte. Watchdog Port wdri Watchdog reset instruction Output Set while executing the wdi (watchdog reset) instruction. Scan Test Ports corese coresi [2:0]
(1)

Input

irqack Interrupt Acknowledge irqackad [2:0] Interrupt Acknowledge Address

Output

Output

Output

Output

Input Input Output

Core Test Scan Enable Core Test Scan Inputs Core Test Scan Outputs

coreso [2:0](1)

AVR Core

AVR Core
Table 1. I/O Description (Continued) Name Input/ Output Function ASTA Test Ports astacp2 ASTA clock astamode [1:0](1) astase [8:0](1) astasi [8:0](1) astaso [8:0]
Note:
(1)

Input Input Input Input Output

Any register in the ASTA interface will update its contents only on the positive edge of astacp2. ASTA mode inputs used to swap between ASTA mode or normal function mode. ASTA Test Scan Enables ASTA Test Scan Inputs ASTA Test Scan Outputs

1. Width is subject to change.

AVR Core Architecture

Figure 2. Block Diagram of the AVR Core and a Typical Set of Peripherals
Program Download ROM or Flash Program Memory Serial Peripheral Interface EEPROM Reference Data System Clock Source Program Counter

AVR CORE

16-bit program bus Instruction Register

UART

Serial Data In/Out

32 General Purpose Registers

ADC/DAC

Analog Data In/Out

RAM Working Data

ALU

Status Register

Analog Comparators

8-bit data bus

Systemspecific Logic

Standard Interfaces Digital Data In/Out

Watchdog Timer

Interrupt Controller

Timer Counters

The AVR core is based on a Harvard architecture with separate memories and buses for program and data (Figure 2). The memory spaces in the AVR architecture are all linear and regular memory maps. 5

Figure 3. AVR Data Memory Map

32*8-bit Working Register File $ 00 $ 1F $ 20 I/O Registers $ 5F $ 60 $ 3F $ 00 I/O Registers

Regular Data Memory

$ FFFF

The central AVR architectural element is a fast-access register file containing 32 x 8-bit general purpose registers with a single clock cycle access time. This means that during one clock cycle, one ALU operation is executed. Two operands are accessed from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. The ALU supports arithmetic and logic functions between registers or between a constant and a register, as well as single register operations. The program memory can be implemented in ROM or Flash memory. It is accessed with a single level of pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed in every clock cycle. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single instruction. During interrupts and subroutine calls, the return address is stored on a software stack. The 8-bit data memory (Figure 3) has 16-bit direct addressing. This gives a potential memory space of 64K bytes. The data memory address space includes the register file, and a 64-address I/O memory space for peripheral functions such as control registers, timer-counters and A/D converters. As shown in Figure 3, the I/O memory space is automatically re-mapped for access by the register file.

AVR Core

AVR Core
The General Purpose Register File
The figure below shows the structure of the 32 general purpose working registers in the CPU. Figure 4. AVR CPU General Purpose Working Registers
7 R0 R1 R2 R13 General Purpose Working Registers R14 R15 R16 R17 R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte Z-register high byte $0D $0E $0F $10 $11 0 Addr. $00 $01 $02

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16 to R31. The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire register file. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X,Y and Z registers can be set to index any register in the file. THE X-REGISTER, Y-REGISTER AND Z-REGISTER The registers R26 to R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as: Figure 5. The X, Y and Z Registers
15 X - register 7 R27 ($1B) 0 7 R26 ($1A) 0 0

15 Y - register 7 R29 ($1D) 0 7 R28 ($1C)

0 0

15 Z - register 7 R31 ($1F) 0 7 R30 ($1E)

0 0

In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).

The ALU - Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logical and bit-functions.

Data Memory Configuration

The following figure shows how the AVR Core Memory is organized: Figure 6. SRAM Organization
Register File R0 R1 R2 R29 R30 R31 I/O Registers $00 $01 $02 $0020 $0021 $0022 Data Address Space $0000 $0001 $0002 $001D $001E $001F

$3D $3E $3F

$005D $005E $005F External Memory $0060 $0061

$FFFF

The first 96 locations address the Register File + I/O Memory, and the next locations address the external data memory. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space.

AVR Core

AVR Core
The Indirect with Displacement mode features a 63 address location reach from the base address given by the Y or Z-register. When using register indirect addressing modes with automatic pre-decrement or post-increment, the address registers X, Y and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers and the 64K bytes of external data SRAM in the AVR Core are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

The AVR Enhanced RISC microcontroller core supports powerful and efficient addressing modes for access to the program memory and data memory (SRAM, Register File and I/O Memory). This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. REGISTER DIRECT, SINGLE REGISTER RD Figure 7. Direct Single Register Addressing

The operand is contained in register d (Rd). REGISTER DIRECT, TWO REGISTERS RD AND RR Figure 8. Direct Register Addressing, Two Registers

The operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O DIRECT Figure 9. I/O Direct Addressing

The operand address is contained in 6 bits of the instruction word. n is the destination or source register address. DATA DIRECT Figure 10. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. DATA INDIRECT WITH DISPLACEMENT Figure 11. Data Indirect with Displacement

The operand address is the result of the Y or Z-register contents added to the displacement contained in 6 bits of the instruction word.

10

AVR Core

AVR Core
DATA INDIRECT Figure 12. Data Indirect Addressing

The operand address is the contents of the X, Y or the Z-register. DATA INDIRECT WITH PRE-DECREMENT Figure 13. Data Indirect Addressing With Pre-Decrement

The X, Y or the Z-register is decremented before the operation. The operand address is the decremented contents of the X, Y or the Z-register. DATA INDIRECT WITH POST-INCREMENT Figure 14. Data Indirect Addressing With Post-Increment

The X, Y or the Z-register is incremented after the operation. The operand address is the content of the X, Y or the Z-register prior to incrementing.

11

CONSTANT ADDRESSING USING THE LPM INSTRUCTION Figure 15. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select the word address (0 - 32K) and the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM is used, LSB of the RAM Page Z register RAMPZ is used to select low or high memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page). DIRECT PROGRAM ADDRESS, JMP AND CALL Figure 16. Direct Program Memory Addressing
31 OP 16 LSBs 15 0 21 20 6 MSBs 16

Program execution continues at the address immediate in the instruction words. INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL Figure 17. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e. the pc is loaded with the contents of the Z-register).

12

AVR Core

AVR Core
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL Figure 18. Relative Program Memory Addressing

Program execution continues at address pc + k + 1. The relative address k is -2048 to 2047.

13

Data Memory Access

Data Memory is accessed in two clock cycles. During the first cycle of a write instruction, the data is driven onto dbusout. During the second cycle, the core issues an address on ramadr and the ramwe strobe. When ramwe is high and ramadr matches the address of an existing memory location, the memory should update its contents only if this occurs on the rising edge of cp2. As the new data is no longer valid on dbusout, the data must be latched outside the core. During the second cycle of a read instruction, the core issues an address on ramadr and the ramre strobe. While ramre is high and ramadr matches the address of an existing memory location, the memory should drive its contents onto dbusin. Data memory space from address $00 to $5F cannot be used for SRAM data space because it is used for the general purpse register file and the I/O registers (see Figure 3 on page 6). Figure 19. Data Memory Access. Read is combinatorial, write is synchronous. During write, the data value disappears from dbusin in cycle 2 and needs to be latched for one cycle outside the core.
ramre

ramadr dbusin ramwe D Q DI A WE

MUX

from I/Os

DO

cp2 dbusout

Figure 20. AVR SRAM Memory Read, using 'ld' or lds instruction.

cp2

ramre

ramadr

valid

dbusin Id cycle 1

valid Id cycle 2 next instruction

14

AVR Core

AVR Core
Figure 21. AVR SRAM Memory Read, using 'ld' or lds instruction with one wait state.

cp2

cpuwait

ramre

ramadr

valid

valid

dbusin Id cycle 1 Id cycle 2

X Id cycle 2

valid next instruction

Figure 22. AVR SRAM Memory Write, using st or sts instruction.

cp2

ramwe

ramadr

valid

dbusout

valid st cycle 1

valid 1 st cycle 2 next instruction

Note:

Not valid when the source register is subject to post-incrementation or pre-decrementation, i.e. the instructions st-Z/Z+, r30/r31, st-Y/Y+, r28/r29, st-X/X+, r26/r27.

15

Figure 23. AVR SRAM Memory Write, using st or sts instruction with one wait cycle.

cp2

cpuwait

ramwe

ramadr

valid

valid

dbusout

valid st cycle 1

valid 1 st cycle 2

valid 1 st cycle 2 next instruction

Note:

Not valid when the source register is subject to post-incrementation or pre-decrementation, i.e. the instructions st-Z/Z+, r30/r31, st-Y/Y+, r28/r29, st-X/X+, r26/r27.

Stack Access
Figure 24. Pushing Program Counter to SRAM Stack with 'rcall/icall instruction.

cp2

ramwe

ramadr

Stack Address

Stack Address -1

dbusout

PC low byte

PC high byte

pc

valid program memory access

valid

inst

X rcall/icall/eicall cycle 1

X rcall/icall/eicall cycle 2 rcall/icall/eicall cycle 3

valid

valid

next instruction

16

AVR Core

AVR Core
Figure 25. Popping Program Counter from SRAM Stack with 'ret/reti instruction.

cp2

ramre

ramadr

Stack Address

Stack Address -1

dbusin

PC high byte

PC low byte

pc

valid program memory access

inst ret/reti cycle 1

X ret/reti cycle 2

X ret/reti cycle 3 ret/reti cycle 4

valid next instruction

Figure 26. Pushing Register to SRAM Stack with 'push instruction

cp2

ramwe

ramadr

valid

dbusout push cycle 1

valid push cycle 2 next instruction

17

Figure 27. Popping to Register from SRAM Stack with 'pop instruction.

cp2

ramre

ramadr

valid

dbusin pop cycle 1 pop cycle 2

valid next instruction

I/O Memory
The I/O space definition of the AVR Core is shown in the following table: Table 2. AVR Core I/O Space
Address Hex $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($39) $38 ($58) $37 ($57) ... $00 ($20) Note: User specific I/O registers Reserved for next AVR Core generation Name SREG SPH SPL RAMPZ Function Status Register Stack Pointer High Stack Pointer Low Reserved for next AVR Core generation RAMPZ Register

In parentheses is the SRAM address as the registers can also be addressed as ordinary SRAM locations within the address space $20 - $5F as described in I/O Registers below.
Unused locations are not shown in the table

Note:

I/O Registers
All the peripheral status, control and data registers can be accessed by making them addressable in the I/O space by connecting adr, iore and iowe signals. The different I/O locations are directly accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. When using IN and OUT (SBIS and SBIC), the I/O register address $00 - $3F must be used. As the I/O registers are also represented in the SRAM address space, they can also be addressed as ordinary SRAM locations using ld/lds and st/sts instructions within the address space $20 - $5F. The SRAM address is obtained by adding $20 to the direct I/O address. The SRAM address is given in parentheses after the I/O direct address throughout this document. I/O registers within the address range $00 ($20) - $1F ($3F) are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. The different I/O and peripherals control registers are explained in the following sections.

18

AVR Core

AVR Core
Status Register
The core register most commonly read and written by software is the Status Register (SREG). This register is updated on all arithmetic and logical instructions, and is also supported by special instructions in the instruction set. Software can also access this register to store or manipulate register contents directly. The AVR status register - SREG - at I/O space location $3F is defined as:
Bit $3F ($5F) Read/Write Initial value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG

Bit 7 - I: Global Interrupt Enable: The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control must be performed externally. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled, independent of the external individual enable values. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. Bit 6 - T: Bit Copy Storage: The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. Bit 5 - H: Half Carry Flag: The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. Bit 4 - S: Sign Bit, S = N V: The S-bit is always an exclusive or between the negative flag N and the twos complement overflow flag V. See the Instruction Set Description for detailed information. Bit 3 - V: Twos Complement Overflow Flag: The twos complement overflow flag V supports twos complement arithmetics. See the Instruction Set Description for detailed information. Bit 2 - N: Negative Flag: The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. Bit 1 - Z: Zero Flag: The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. Bit 0 - C: Carry Flag: The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.

19

The Stack Pointer - SP

The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AVR Core supports up to 64K bytes SRAM, all 16 bit are used.
Bit $3E ($5E) $3D ($5D) 15 SP15 SP7 7 Read/Write R/W R/W Initial value 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when data is pushed onto the Stack with subroutine CALL and interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. Extended Memory Pointer Registers - RAMPZ The AVR architecture supports four pointers, X-, Y-, Z-, and Stack-Pointer. On systems with more than 64K bytes of program memory, the Z-pointer will not reach the whole memory space with the 16 bits located in the General Purpose Register File. For the Z-pointer to reach the entire memory area, the remaining bit is read and written by software through I/O, through the register RAMPZ.
Bit $3B ($5B) Read/Write Initial value 7
-

6
-

5
-

4
-

3
-

2
-

1
-

0
RAMPZ0

RAMPZ

R/W 0

R/W 0

R/W 0

R/W 0

R/W 0

R/W 0

R/W 0

R/W 0

The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer. As the AVR Core does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the elpm instruction is used. The different settings of the RAMPZ0 bit have the following effects. RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is accessed by elpm. RAMPZ0 = 1: Program memory address $8000 - $FFFF (upper 64K bytes) is accessed by elpm.

20

AVR Core

AVR Core
I/O Memory Access
I/O registers can be accessed in a single clock cycle. During this clock cycle, the core will issue a 6-bit address on adr, and either an iore or an iowe. While iore is high and adr matches the address of the register, the I/O register should drive its contents onto dbusin. When iowe is high and adr matches the address of the register, the register should update its contents only if this occurs on a rising edge of cp2. Figure 28. A typical I/O Register Construction. Write is synchronous, read is combinatorial.
iore adr[5:0]

Address Decode

from I/Os dbusin iowe DI A WE MUX from I/Os

cp2 dbusout

Figure 29. AVR I/O Register Read, using 'in' instruction. dbusin is driven by I/O Register.

cp2

iore

adr

valid

dbusin in

valid next instruction

21

Figure 30. AVR I/O Register Write, using out instruction. dbusout is driven by AVR Core.

cp2

iowe

adr

valid

dbusout out

valid next instruction

As the I/O registers are also represented in the SRAM address space, I/O registers are accessible by regular memory access instructions ld/ldd/lds and st/std/sts. The access will appear like any other memory access, but the address will be presented on adr and mapped from the address range 0x20-0x5F used in SRAM, down to the 0x00-0x3F recognized by the I/O registers. This operation is performed automatically by the core. Figure 31. AVR I/O Register Read, using 'ld' instruction. dbusin is driven by I/O Register.

cp2

iore

adr

valid

dbusin Id cycle 1

valid Id cycle 2 next instruction

Figure 32. AVR I/O Register Write, using st instruction.

cp2

iowe

adr

valid

dbusout Id cycle 1

valid Id cycle 2 next instruction

22

AVR Core

AVR Core
Reset and Interrupt Handling
The AVR Core provides 7 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are enabled by the I-bit in the status register. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in . The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. ireset has the highest priority, and next are irqlines[0] to irqlines[6]. Table 3. Reset and Interrupt Vectors
Vector No. 1 2 3 4 5 6 7 8 Program Address $000 $002 $004 $006 $008 $00A $00C $00E Source ireset irqlines[0] irqlines[1] irqlines[2] irqlines[3] irqlines[4] irqlines[5] irqlines[6] Interrupt Definition Internal Reset Interrupt Request Line 0 Interrupt Request Line 1 Interrupt Request Line 2 Interrupt Request Line 3 Interrupt Request Line 4 Interrupt Request Line 5 Interrupt Request Line 6

The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
Address $000 $001 $002 $004 $006 $007 $008 $009 $00A $00B $00C $00E ; $010 RESET: <instr> xxx ; Main program start Labels Code rjmp nop jmp jmp rjmp nop rjmp nop rjmp nop jmp jmp INT5 INT6 ; IRQ5 Handle ; IRQ6 Handle INT4 ; IRQ4 Handle INT3 ; IRQ3 Handle INT0 INT1 INT2 RESET Comments ; Reset Handle ; ; IRQ0 Handle ; IRQ1 Handle ; IRQ2 Handle

23

Reset
The ireset line controls the reset of the AVR Core. To properly reset the AVR, a three cycle pulse must be applied to the ireset input. After this, the program counter is reset to 0000 and the AVR Core is ready. Note: Setup and hold times must be respected on the ireset line (see timing diagrams).

Interrupts
None of the irqlines are latched in the AVR Core. For this reason, it is necessary to maintain the irqlines[6:0] signals until the corresponding acknowledgment. The figure below shows the interrupt acknowledgment schemes. Figure 33. Interrupt arriving in last cycle of instruction
cycle 0 CP2 cycle 1 cycle 2 cycle 3

instruction last cycle irqlines[X]

ramadr

stack address

stack address-1

Drive PC to dbusout

high byte

low byte

ramwe

irqackad

irqack

Next PC valid

valid

24

AVR Core

AVR Core
Figure 34. Interrupt arriving in cycle other than last
cycle -X CP2 cycle 0 cycle 1 cycle 2 cycle 3

Previous instruction irqlines[X]

last cycle

ramadr

stack address

stack address-1

Drive PC to dbusout

high byte

low byte

ramwe

irqackad

irqack

Next PC valid

valid

25

AVR Scalable Test Access (ASTA) Interface

The AVR Scalable Test Access (ASTA) interface provides designers with great flexibility to test the AVR Embedded Core and its peripherals. First, the ASTA architecture allows the designer to apply pre-computed ATPG test vectors with more than 99% fault coverage. Secondly, it allows ATPG vectors to be generated for the rest of the chip. The main characteristic of the ASTA architecture however, is its capability to be scaled and split into several scan chains, making it possible to test the program memory space, the RAM space and the I/O space simultaneously. The ASTA interface can be considered as a boundary scan ring that encompasses the entire AVR Embedded Core. This scan chain allows all primary AVR inputs to be controlled and all primary AVR outputs to be observed, resulting in over a 99% fault coverage. This scan ring is actually split into nine different scan chains which can be grouped as desired, giving the flexibility to create specific tests such as RAM space testing or program memory space testing. All of the scan chains which form the ASTA scan ring have a common clock (astacp2). However, they have separate scan inputs (astasi[8:0]) and outputs (astaso[8:0]) as well as separate scan enable signals (astase[8:0]) which gives this architecture its flexibility. To achieve 99% fault coverage, the three internal scan chains which have coresi[2:0] for inputs, coreso[2:0] for outputs and a common corese for scan enable must be used for applying ATPG vectors. The ASTA interface is shown below: Figure 35. The ASTA Interface.
astaso[3] Functional Inputs

AVR

astaso[8] Functional

YP

TE

AVRCORE

YP

EN

YP

Functional Inputs

TE

EN

astasi[3]

EN

TE

YP

TE

Outputs astasi[8]

Functional Outputs

EN

TE

YP

TE

YP

TE

astaso[0] Functional Inputs

astaso[4] Functional Outputs

YP

EN

astasi[0] astase[8:0] astacp2 cp2 corese

EN

EN

astasi[4]

26

AVR Core

AVR Core
ASTA Signals
The signals which control the ASTA interface are described below. Table 4. ASTA Signals
Signal astacp2 astamode[1:0] astamode[0] = 0 Description Clock for all ASTA flip-flops ASTA mode select for inputs (astamode[0]) and outputs (astamode[1]) Functional Mode and External Capture Mode The ASTA input interface is transparent. This implies that the device is in Functional Mode. Nevertheless, the ASTA scan chains can capture all AVR input signals. Internal Control Mode The ASTA input interface is controlled by ASTA scan chains. The ASTA interface can control all AVR input signals. Functional Mode and Internal Capture Mode The ASTA output interface is transparent. This implies that the device is in Functional Mode. Nevertheless, the ASTA scan chains can capture all AVR output signals. External Control Mode The ASTA output interface is controlled by ASTA scan chains. The ASTA interface can control all AVR output signals. ASTA scan inputs ASTA scan outputs ASTA scan enables

astamode[0] = 1

astamode[1] = 0

astamode[1] = 1 astasi[8:0] astaso[8:0] astase[8:0]

ASTA Scan Chains

The ASTA architecture is based on the possibility of joining the ASTA scan chains in order to dynamically create new scan chains dedicated to a specific test goal. The ASTA architecture is formed by nine scan chains which are defined below: Table 5. ASTA Scan Chains
ASTA Chain ASTA chain 0 ASTA chain 1 ASTA chain 2 ASTA chain 3 ASTA chain 4 ASTA chain 5 ASTA chain 6 ASTA chain 7 ASTA chain 8 Scan Input astasi[0] astasi[1] astasi[2] astasi[3] astasi[4] astasi[5] astasi[6] astasi[7] astasi[8] Scan Output astaso[0] astaso[1] astaso[2] astaso[3] astaso[4] astaso[5] astaso[6] astaso[7] astaso[8] Scan Enable astase[0] astase[1] astase[2] astase[3] astase[4] astase[5] astase[6] astase[7] astase[8] AVR Inputs/Outputs Controlled/Observed inst[15:0] dbusin[7:0] irqlines[6:0] control = lbit12, pcld[1:0], pclden, leavbus, cpuwait, ireset irq outputs = globint, irqackad[2:0], irqack, irqok, sleepi, wdri RAM space = ramadr[15:0], ramwe, ramre I/O space = adr[5:0], iowe, iore dbusout[7:0] pc[15:0]

In all scan chains LSB is scanned in first and MSB scanned out first.

27

ASTA Scan Input Cell

Each primary input of the AVR Embedded core is connected to an ASTA scan input cell which can be configured to run in different modes. Figure 36. ASTA Scan Input Cell
To next scan input

From AVR Primary Input

0 To AVRCORE Input SO D Q 1

astase[X]

SE

astacp2

SI astamode[0]

From previous scan ouput

The following signals control the ASTA scan input cell: Table 6. ASTA Scan Input Cell
Signal astacp2 astase[X] astamode[0] astamode[0] = 0 Description Clock for all ASTA flip-flops Local scan enable for the selected ASTA scan chain Test mode selector Functional Mode and External Capture Mode The ASTA input interface is transparent. This implies that the device is in Functional Mode. Nevertheless, the ASTA scan chains can capture all AVR input signals. See Table 4. Internal Control Mode The ASTA input interface is controlled by ASTA scan chains. The ASTA interface can control all AVR input signals. See Table 4.

astamode[0] = 1

ASTA Scan Output Cell

Each primary output of the AVR Embedded core is connected to an A.S.T.A scan output cell which can be configured in different modes.

28

AVR Core

AVR Core
Figure 37. ASTA Scan Output Cell
To next scan input cell

From AVRCORE Output

0 To AVR Primary Output SO D Q 1

astase[X]

SE

astacp2

SI astamode[1]

From previous scan ouput cell

The following signals control the ASTA scan output cell: Table 7. ASTA Scan Output Cell
Signal astacp2 astase[X] astamode[1] astamode[1] = 0 Description Clock for all ASTA flip-flops Local scan enable for the selected ASTA scan chain Test mode selector Functional Mode and Internal Capture Mode The ASTA output interface is transparent. This is Functional Mode. Nevertheless, the ASTA scan chains can capture all AVR output signals. See Table 4. External Control Mode The ASTA output interface is controlled by ASTA scan chains. The ASTA interface can control all AVR output signals. See Table 4.

astamode[1] = 1

Testing the AVR Embedded Core

The AVR Embedded Core is shipped with a pre-computed set of ATPG test vectors ensuring over a 99% fault coverage. This set of vectors is generated with a special configuration of the ASTA interface. The designer must recreate this configuration in his design. In order to apply the precomputed ATPG vectors: 1. The designer must have access to the following top level pins: cp2: global clock test_se: new global scan enable (to be created by the user) astamode[1:0]: astamode selectors coresi[2:0]: Internal scan chain inputs coreso[2:0]: Internal scan chain outputs asta_scin: ASTA boundary ring input (to be created by the user) asta_scout: ASTA boundary ring output (to be created by the user) 2. The following signals must be tied together: cp2 = astacp2 test_se = corese = astase[8:0] 3. The ASTA boundary ring must be connected as follows: asta_scin = astasi[0] astaso[0] = astasi[1]

29

astaso[1] = astasi[2] astaso[2] = astasi[3] astaso[3] = astasi[4] astaso[4] = astasi[5] astaso[5] = astasi[6] astaso[6] = astasi[7] astaso[7] = astasi[8] astaso[8] = asta_scout which results in a scan chain linked as follows: asta_scin, ASTA chain 0, ASTA chain 1, ASTA chain 2, ASTA chain 3, ASTA chain 4, ASTA chain 5, ASTA chain 6, ASTA chain 7, ASTA chain 8, asta_scout

Testing the AVR Peripherals

The AVR Peripherals can be separated into three classes: standard AVR peripherals (AVR UART, AVR SPI, etc.), other embedded Macros and User Defined Logic (UDL). All can be tested using the ASTA interface.

Methodologies
Because the test goal for todays designs is over a 99% fault coverage, the recommended methodology for testing designs containing the AVR Embedded core is Full Scan. This is the simplest methodology. In specific cases however, good coverage can be achieved with Partial Scan, BIST or non scan techniques. To allow a large amount of freedom in a design, the ASTA architecture makes it possible to use all of these special DFT methodologies.

Test Configuration
A fourth scan chain must be created around the AVR Embedded Core by linking the nine ASTA scan chains as described in the previous section. With this scan chain, the AVR Embedded Core can be bypassed (the core is an ATPG black box for the designer due to its encrypted format), and ATPG test vectors can then be generated for the rest of the chip, including AVR standard peripherals, embedded Macros and UDL. Partial Scan or ad-hoc methodologies can also be used by controlling this scan chain.

Special Tests with the ASTA Interface

Using the ASTA Interface allows all AVR output pins to be controlled and all AVR input pins to be observed. Specific tests can then be created as described below.

Ram Space Testing

By linking ASTA chain 5 with ASTA chain 1, test sequences can be generated to verify the correct functionality of the RAM itself or of the RAM space mapping.

I/O Space Testing

By linking ASTA chain 6 with ASTA chain 1, test sequences can be generated to verify the correct functionality of the I/O space mapping.

Program Memory Space Testing

By linking ASTA chain 8 with ASTA chain 0, test sequences can be generated to verify the correct functionality of the Program Memory space.

30

AVR Core

AVR Core
Input/Output Timing
tCLK /astacp2 tHIGH tLOW

Inputs tSU

Valid tHO

Outputs tCKO (min) tCKO (max)

Valid

Inputs

Outputs tCOMB (min) tCOMB (max)

Symbol tCP2 tSU tHO tCKO tCOMB

Parameter Clock cycle Input setup time Input hold time Clock to output delay Combinational delay; input to output

Note: The delays shown in this diagram are all process specific. For the corresponding characterized values, refer to one of the following datasheets: AVR Embedded Core ATC50 Electrical Characteristics (0.5 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V 0.3V) AVR Embedded Core ATC50/E2 Electrical Characteristics (0.5 micron three-layer-metal CMOS/NVM process intended for use with a supply voltage of 3.3V 0.3V) AVR Embedded Core ATC35 Electrical Characteristics (0.35 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V 0.3V)

31

AVR Core Register Summary

Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) ... $01 ($21) $00 ($20) User Specific I/O Registers Reserved for next AVR Core generation Name SREG SPH SPL RAMPZ Bit 7 I SP15 SP7 Bit 6 T SP14 SP6 Bit 5 H SP13 SP5 Bit 4 S SP12 SP4 Bit 3 V SP11 SP3 Bit 2 N SP10 SP2 Bit 1 Z SP9 SP1 Bit 0 C SP8 SP0 Page 19 20 20

Reserved for next AVR Core generation RAMPZ0 20

32

AVR Core

AVR Core
AVR Core Instruction Set
Instruction Set Nomenclature:
Status Register (SREG): SREG: Status register C: Carry flag in status register Z: Zero flag in status register N: Negative flag in status register V: Twos complement overflow indicator S: N V, For signed tests H: Half Carry flag in the status register T: Transfer bit used by BLD and BST instructions I: Global interrupt enable/disable flag Registers and operands: Rd: Destination (and source) register in the register file Rr: Source register in the register file R: Result after instruction is executed K: Constant literal or byte data (8 bit) k: Constant address data for program counter b: Bit in the register file or I/O register (3 bit) s: Bit in the status register (3 bit) X,Y,Z: Indirect address register (X=R27:R26, Y=R29:R28 and Z=R31:R30) P: I/O port address q: Displacement for direct addressing (6 bit) I/O Registers RAMPZ: Register concatenated with the Z register enabling indirect addressing of the whole Program Area on MCUs with more than 64K bytes of Program Code (ELPM instruction). Stack: STACK:Stack for return address and pushed registers SP: Stack Pointer to STACK Flags: : 0: 1: -:

Flag affected by instruction Flag cleared by instruction Flag set by instruction Flag not affected by instruction

Conditional Branch Summary

Test Boolean Mnemonic Complementary Boolean Mnemonic Comment

Rd > Rr Rd Rr Rd = Rr Rd Rr Rd < Rr Rd > Rr Rd Rr Rd = Rr Rd Rr Rd < Rr Carry Negative Overflow Zero

Z(N V) = 0 (N V) = 0 Z=1 Z+(N V) = 1 (N V) = 1 C+Z=0 C=0 Z=1 C+Z=1 C=1 C=1 N=1 V=1 Z=1

BRLT* BRGE BREQ BRGE* BRLT BRLO* BRSH/BRCC BREQ BRSH* BRLO/BRCS BRCS BRMI BRVS BREQ

Rd Rr Rd < Rr Rd Rr Rd > Rr Rd Rr Rd Rr Rd < Rr Rd Rr Rd > Rr Rd Rr No carry Positive No overflow Not zero

Z+(N V) = 1 (N V) = 1 Z=0 Z(N V) = 0 (N V) = 0 C+Z=1 C=1 Z=0 C+Z=0 C=0 C=0 N=0 V=0 Z=0

BRGE* BRLT BRNE BRLT* BRGE BRSH* BRLO/BRCS BRNE BRLO* BRSH/BRCC BRCC BRPL BRVC BRNE

Signed Signed Signed Signed Signed Unsigned Unsigned Unsigned Unsigned Unsigned Simple Simple Simple Simple

* Interchange Rd and Rr in the operation before the test. i.e. CP Rd,Rr CP Rr,Rd

33

Complete Instruction Set Summary

Mnemonic Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers Ones Complement Twos Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd Rr Rd Rd K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF Rd Rd $00 Rd Rd Rd v K Rd Rd ($FF - K) Rd Rd + 1 Rd Rd 1 Rd Rd Rd Rd Rd Rd Rd $FF Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1

(continued)

34

AVR Core

AVR Core
Complete Instruction Set Summary (continued)
Mnemonic Operands Description Operation Flags #Clocks BRANCH INSTRUCTIONS RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k k k k Relative Jump Indirect Jump to (Z) Direct Jump to k Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call to k Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd Rr Rd Rr C Rd K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None 2 2 3 3 3 4 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

(continued)

35

Complete Instruction Set Summary (continued)

Mnemonic Operands Description Operation Flags #Clocks

DATA TRANSFER INSTRUCTIONS MOV LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM ELPM IN OUT PUSH POP Rd, P P, Rr Rr Rd Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Extended Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) R0 (RAMPZ, Z ) Rd P P Rr STACK Rr Rd STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 2 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2

(continued)

36

AVR Core

AVR Core
Complete Instruction Set Summary (continued)
Mnemonic Operands Description Operation Flags #Clocks

BIT AND BIT-TEST INSTRUCTIONS SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr. for WDR/timer) I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1

37

ADC - Add with Carry

Description:

Adds two registers and the contents of the C flag and places the result in the destination register Rd.
Operation:

(i)

Rd Rd + Rr + C

Syntax:

Operands:

Program Counter:

(i)

ADC Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0001

11rd

dddd

rrrr

Status Register (SREG) Boolean Formulae: I H: T H S V N Z C

Rd3Rr3+Rr3R3+R3Rd3 Set if there was a carry from bit 3; cleared otherwise N V, For signed tests. Rd7Rr7R7+Rd7Rr7R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. Rd7 Rr7 Rr7 R7 R7 Rd7 Set if the result is $00; cleared otherwise. Rd7Rr7+Rr7R7+R7Rd7 Set if there was carry from the MSB of the result; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
; Add R1:R0 to R3:R2 add adc r2,r0 r3,r1 ; Add low byte ; Add with carry high byte

Words: 1 (2 bytes) Cycles: 1

38

AVR Core

AVR Core
ADD - Add without Carry
Description:

Adds two registers without the C flag and places the result in the destination register Rd.
Operation:

(i)

Rd Rd + Rr
Syntax: Operands: Program Counter:

(i)

ADD Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0000

11rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I H: T H S V N Z C

Rd3Rr3+Rr3R3+R3Rd3 Set if there was a carry from bit 3; cleared otherwise N V, For signed tests. Rd7Rr7R7+Rd7Rr7R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Rr7 +Rr7 R7+ R7 Rd7 Set if there was carry from the MSB of the result; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
add add r1,r2 r28,r28 ; Add r2 to r1 (r1=r1+r2) ; Add r28 to itself (r28=r28+r28)

Words: 1 (2 bytes) Cycles: 1

39

ADIW - Add Immediate to Word

Description:

Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates on the upper four register pairs, and is well suited for operations on the pointer registers.
Operation:

(i)

Rdh:Rdl Rdh:Rdl + K
Syntax: Operands: Program Counter:

(i)

ADIW Rdl,K
16 bit Opcode:

dl {24,26,28,30}, 0 K 63

PC PC + 1

1001

0110

KKdd

KKKK

Status Register (SREG) and Boolean Formulae: I S: V: T H S V N Z C

N V, For signed tests. Rdh7 R15 Set if twos complement overflow resulted from the operation; cleared otherwise. R15 Set if MSB of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise. R15 Rdh7 Set if there was carry from the MSB of the result; cleared otherwise.

N:

Z:

C:

R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 = R15-R8, Rdl7-Rdl0=R7-R0).

Example:
adiw r24,1 adiw r30,63 ; Add 1 to r25:r24 ; Add 63 to the Z pointer(r31:r30)

Words: 1 (2 bytes) Cycles: 2

40

AVR Core

AVR Core
AND - Logical AND
Description:

Performs the logical AND between the contents of register Rd and register Rr and places the result in the destination register Rd.
Operation:

(i)

Rd Rd Rr
Syntax: Operands: Program Counter:

(i)

AND Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0010

00rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I S: V: T H S V 0 N Z C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
and ldi and r2,r3 r16,1 r2,r16 ; Bitwise and r2 and r3, result in r2 ; Set bitmask 0000 0001 in r16 ; Isolate bit 0 in r2

Words: 1 (2 bytes) Cycles: 1

41

ANDI - Logical AND with Immediate

Description:

Performs the logical AND between the contents of register Rd and a constant and places the result in the destination register Rd.
Operation:

(i)

Rd Rd K
Syntax: Operands: Program Counter:

(i)

ANDI Rd,K
16 bit Opcode:

16 d 31, 0 K 255

PC PC + 1

0111

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formulae: I S: V: T H S V 0 N Z C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
andi r17,$0F andi r18,$10 andi r19,$AA ; Clear upper nibble of r17 ; Isolate bit 4 in r18 ; Clear odd bits of r19

Words: 1 (2 bytes) Cycles: 1

42

AVR Core

AVR Core
ASR - Arithmetic Shift Right
Description:

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides a twos complement value by two without changing its sign. The carry flag can be used to round the result.
Operation:

(i)

b7 - - - - - - - - - b0
Syntax:

C
Operands: Program Counter:

(i)

ASR Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0101

Status Register (SREG) and Boolean Formulae: I S: V: T H S V N Z C

N V, For signed tests. N C (For N and C after the shift) Set if (N is set and C is clear) or (N is clear and C is set); Cleared otherwise (for values of N and C after the shift). R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd0 Set if, before the shift, the LSB of Rd was set; cleared otherwise.

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
ldi asr ldi asr r16,$10 r16 r17,$FC r17 ; Load decimal 16 into r16 ; r16=r16 / 2 ; Load -4 in r17 ; r17=r17/2

Words: 1 (2 bytes) Cycles: 1

43

BCLR - Bit Clear in SREG

Description:

Clears a single flag in SREG.

Operation:

(i)

SREG(s) 0
Syntax: Operands: Program Counter:

(i)

BCLR s
16 bit Opcode:

0s7

PC PC + 1

1001

0100

1sss

1000

Status Register (SREG) and Boolean Formulae: I I: T: H: S: V: N: Z: C: T H S V N Z C

0 if s = 7; Unchanged otherwise. 0 if s = 6; Unchanged otherwise. 0 if s = 5; Unchanged otherwise. 0 if s = 4; Unchanged otherwise. 0 if s = 3; Unchanged otherwise. 0 if s = 2; Unchanged otherwise. 0 if s = 1; Unchanged otherwise. 0 if s = 0; Unchanged otherwise.

Example:
bclr bclr 0 7 ; Clear carry flag ; Disable interrupts

Words: 1 (2 bytes) Cycles: 1

44

AVR Core

AVR Core
BLD - Bit Load from the T Flag in SREG to a Bit in Register.
Description:

Copies the T flag in the SREG (status register) to bit b in register Rd.
Operation:

(i)

Rd(b) T
Syntax: Operands: Program Counter:

(i)

BLD Rd,b
16 bit Opcode:

0 d 31, 0 b 7

PC PC + 1

1111

100d

dddd

0bbb

Status Register (SREG) and Boolean Formulae: I T H S V N Z C -

Example:
; Copy bit bst bld r1,2 r0,4 ; Store bit 2 of r1 in T flag ; Load T flag into bit 4 of r0

Words: 1 (2 bytes) Cycles: 1

45

BRBC - Branch if Bit in SREG is Cleared

Description:

Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form.
Operation:

(i)

If SREG(s) = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRBC s,k

0 s 7, -64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

ksss

Status Register (SREG) and Boolean Formulae: I Example:

cpi r20,5 ; Compare r20 to the value 5 ; Branch if zero flag cleared ; Branch destination (do nothing) brbc 1,noteq ... noteq:nop

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

46

AVR Core

AVR Core
BRBS - Branch if Bit in SREG is Set
Description:

Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is set. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form.
Operation:

(i)

If SREG(s) = 1 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRBS s,k

0 s 7, -64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

ksss

Status Register (SREG) and Boolean Formulae: I Example:

bst r0,3 ; Load T bit with bit 3 of r0 brbs 6,bitset ; Branch T bit was set ... bitset: nop ; Branch destination (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

47

BRCC - Branch if Carry Cleared

Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 0,k).
Operation:

(i)

If C = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRCC k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k000

Status Register (SREG) and Boolean Formulae: I Example:

addr22,r23 brccnocarry ... nocarry: nop ; Branch destination (do nothing) ; Add r23 to r22 ; Branch if carry cleared

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

48

AVR Core

AVR Core
BRCS - Branch if Carry Set
Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 0,k).
Operation:

(i)

If C = 1 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRCS k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k000

Status Register (SREG) and Boolean Formulae: I Example:

cpi r26,$56 ; Compare r26 with $56 ; Branch if carry set ; Branch destination (do nothing) brcs carry ... carry: nop

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

49

BREQ - Branch if Equal

Description:

Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned or signed binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 1,k).
Operation:

(i)

If Rd = Rr (Z = 1) then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BREQ k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k001

Status Register (SREG) and Boolean Formulae: I Example:

cpr1,r0 breqequal ... equal: nop ; Branch destination (do nothing) ; Compare registers r1 and r0 ; Branch if registers equal

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

50

AVR Core

AVR Core
BRGE - Branch if Greater or Equal (Signed)
Description:

Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signed binary number represented in Rd was greater than or equal to the signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 4,k).
Operation:

(i)

If Rd Rr (N V = 0) then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRGE k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k100

Status Register (SREG) and Boolean Formulae: I Example:

cpr11,r12 brgegreateq ... greateq: nop ; Branch destination (do nothing) ; Compare registers r11 and r12 ; Branch if r11 >= r12 (signed)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

51

BRHC - Branch if Half Carry Flag is Cleared

Description:

Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 5,k).
Operation:

(i)

If H = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRHC k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k101

Status Register (SREG) and Boolean Formulae: I Example:

brhc hclear ... hclear: nop ; Branch destination (do nothing) ; Branch if half carry flag cleared

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

52

AVR Core

AVR Core
BRHS - Branch if Half Carry Flag is Set
Description:

Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is set. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 5,k).
Operation:

(i)

If H = 1 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRHS k
16 bit Opcode:

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false k101

1111

00kk

kkkk

Status Register (SREG) and Boolean Formulae: I Example:

brhshset ... hset: nop ; Branch destination (do nothing) ; Branch if half carry flag set

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

53

BRID - Branch if Global Interrupt is Disabled

Description:

Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 7,k).
Operation:

(i)

If I = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRID k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k111

Status Register (SREG) and Boolean Formulae: I Example:

brid intdis ... intdis: nop ; Branch destination (do nothing) ; Branch if interrupt disabled

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

54

AVR Core

AVR Core
BRIE - Branch if Global Interrupt is Enabled
Description:

Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is set. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 7,k).
Operation:

(i)

If I = 1 then PC PC + k + 1, else PC PC + 1
Syntax: Operands: Program Counter:

(i)

BRIE k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k111

Status Register (SREG) and Boolean Formulae: I Example:

brieinten ... inten: nop ; Branch destination (do nothing) ; Branch if interrupt enabled

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

55

BRLO - Branch if Lower (Unsigned)

Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned binary number represented in Rd was smaller than the unsigned binary number represented in Rr. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 0,k).
Operation:

(i)

If Rd < Rr (C = 1) then PC PC + k + 1, else PC PC + 1

Syntax: Operands: Program Counter:

(i)

BRLO k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k000

Status Register (SREG) and Boolean Formulae: I Example:

eor loop: inc ... cpi r19,$10 ; Compare r19 with $10 ; Branch if r19 < $10 (unsigned) ; Exit from loop (do nothing) brlo loop nop r19,r19 r19 ; Clear r19 ; Increase r19

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

56

AVR Core

AVR Core
BRLT - Branch if Less Than (Signed)
Description:

Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signed binary number represented in Rd was less than the signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 4,k).
Operation:

(i)

If Rd < Rr (N V = 1) then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRLT k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k100

Status Register (SREG) and Boolean Formulae: I Example:

cp ... less: nop ; Branch destination (do nothing) r16,r1 ; Compare r16 to r1 ; Branch if r16 < r1 (signed) brlt less

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

57

BRMI - Branch if Minus

Description:

Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is set. This instruction branches relatively to PC in either direction (PC-64 destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 2,k).
Operation:

(i)

If N = 1 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRMI k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k010

Status Register (SREG) and Boolean Formulae: I Example:

subi brmi ... negative: nop ; Branch destination (do nothing) r18,4 negative ; Subtract 4 from r18 ; Branch if result negative

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

58

AVR Core

AVR Core
BRNE - Branch if Not Equal
Description:

Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned or signed binary number represented in Rd was not equal to the unsigned or signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 1,k).
Operation:

(i)

If Rd Rr (Z = 0) then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRNE k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k001

Status Register (SREG) and Boolean Formulae: I Example:

eor loop: inc ... cpi brne nop r27,5 loop ; Compare r27 to 5 ; Branch if r27<>5 ; Loop exit (do nothing) r27,r27 r27 ; Clear r27 ; Increase r27

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

59

BRPL - Branch if Plus

Description:

Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 2,k).
Operation:

(i)

If N = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRPL k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k010

Status Register (SREG) and Boolean Formulae: I Example:

subi r26,$50 brpl positive ... positive: nop ; Branch destination (do nothing) ; Subtract $50 from r26 ; Branch if r26 positive

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

60

AVR Core

AVR Core
BRSH - Branch if Same or Higher (Unsigned)
Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. If the instruction is executed immediately after execution of any of the instructions CP, CPI, SUB or SUBI the branch will occur if and only if the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented in Rr. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 0,k).
Operation:

(i)

If Rd Rr (C = 0) then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRSH k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k000

Status Register (SREG) and Boolean Formulae: I Example:

subi r19,4 brsh highsm ... highsm: nop ; Branch destination (do nothing) ; Subtract 4 from r19 ; Branch if r19 >= 4 (unsigned)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

61

BRTC - Branch if the T Flag is Cleared

Description:

Conditional relative branch. Tests the T flag and branches relatively to PC if T is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 6,k).
Operation:

(i)

If T = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRTC k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k110

Status Register (SREG) and Boolean Formulae: I Example:

bst brtc ... tclear: nop ; Branch destination (do nothing) r3,5 tclear ; Store bit 5 of r3 in T flag ; Branch if this bit was cleared

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

62

AVR Core

AVR Core
BRTS - Branch if the T Flag is Set
Description:

Conditional relative branch. Tests the T flag and branches relatively to PC if T is set. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 6,k).
Operation:

(i)

If T = 1 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRTS k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

00kk

kkkk

k110

Status Register (SREG) and Boolean Formulae: I Example:

bst r3,5 ; Store bit 5 of r3 in T flag ; Branch if this bit was set ; Branch destination (do nothing) brts tset ... tset: nop

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

63

BRVC - Branch if Overflow Cleared

Description:

Conditional relative branch. Tests the Overflow flag (V) and branches relatively to PC if V is cleared. This instruction branches relatively to PC in either direction (PC-64destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBC 3,k).
Operation:

(i)

If V = 0 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRVC k

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false

16 bit Opcode:

1111

01kk

kkkk

k011

Status Register (SREG) and Boolean Formulae:

I Example:

T -

H -

S -

V -

N -

Z -

C -

add

r3,r4

; Add r4 to r3 ; Branch if no overflow ; Branch destination (do nothing)

brvc noover ... noover: nop

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

64

AVR Core

AVR Core
BRVS - Branch if Overflow Set
Description:

Conditional relative branch. Tests the Overflow flag (V) and branches relatively to PC if V is set. This instruction branches relatively to PC in either direction (PC-64 destinationPC+63). The parameter k is the offset from PC and is represented in twos complement form. (Equivalent to instruction BRBS 3,k).
Operation:

(i)

If V = 1 then PC PC + k + 1, else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

BRVS k
16 bit Opcode:

-64 k +63

PC PC + k + 1 PC PC + 1, if condition is false k011

1111

00kk

kkkk

Status Register (SREG) and Boolean Formulae: I Example:

add brvs ... overfl: nop ; Branch destination (do nothing) r3,r4 overfl ; Add r4 to r3 ; Branch if overflow

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false 2 if condition is true

65

BSET - Bit Set in SREG

Description:

Sets a single flag or bit in SREG.

Operation:

(i)

SREG(s) 1
Syntax: Operands: Program Counter:

(i)

BSET s
16 bit Opcode:

0s7

PC PC + 1

1001

0100

0sss

1000

Status Register (SREG) and Boolean Formulae: I I: T: H: S: V: N: Z: C: T H S V N Z C

1 if s = 7; Unchanged otherwise. 1 if s = 6; Unchanged otherwise. 1 if s = 5; Unchanged otherwise. 1 if s = 4; Unchanged otherwise. 1 if s = 3; Unchanged otherwise. 1 if s = 2; Unchanged otherwise. 1 if s = 1; Unchanged otherwise. 1 if s = 0; Unchanged otherwise.

Example:
bset bset 6 7 ; Set T flag ; Enable interrupt

Words: 1 (2 bytes) Cycles: 1

66

AVR Core

AVR Core
BST - Bit Store from Bit in Register to T Flag in SREG
Description:

Stores bit b from Rd to the T flag in SREG (status register).

Operation:

(i)

T Rd(b)
Syntax: Operands: Program Counter:

(i)

BST Rd,b
16 bit Opcode:

0 d 31, 0 b 7

PC PC + 1

1111

101d

dddd

Xbbb

Status Register (SREG) and Boolean Formulae: I T: T H S V N Z C -

0 if bit b in Rd is cleared. Set to 1 otherwise.

Example:
; Copy bit bst bld r1,2 r0,4 ; Store bit 2 of r1 in T flag ; Load T into bit 4 of r0

Words: 1 (2 bytes) Cycles: 1

67

CALL - Long Call to a Subroutine

Description:

Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be stored onto the stack. (See also RCALL).

Operation:

(i) (ii)

PC k PC k
Syntax:

Devices with 16 bits PC, 128K bytes program memory maximum. Devices with 22 bits PC, 8M bytes program memory maximum.
Operands: Program Counter:Stack

(i)

CALL k

0 k 64K 0 k 4M

PC kSTACK PC+2 SP SP-2, (2 bytes, 16 bits) PC kSTACK PC+2 SP SP-3 (3 bytes, 22 bits)

(ii)

CALL k

32 bit Opcode:

1001 kkkk

010k kkkk

kkkk kkkk

111k kkkk

Status Register (SREG) and Boolean Formulae: I Example:

mov call nop ... check: cpi breq ret ... error: rjmp error ; Infinite loop r16,$42 error ; Check if r16 has a special value ; Branch if equal ; Return from subroutine r16,r0 check ; Copy r0 to r16 ; Call subroutine ; Continue (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 2 (4 bytes) Cycles: 4

68

AVR Core

AVR Core
CBI - Clear Bit in I/O Register

Description:

Clears a specified bit in an I/O register. This instruction operates on the lower 32 I/O registers - addresses 0-31.
Operation:

(i)

I/O(P,b) 0
Syntax: Operands: Program Counter:

(i)

CBI P,b
16 bit Opcode:

0 P 31, 0 b 7

PC PC + 1

1001

1000

pppp

pbbb

Status Register (SREG) and Boolean Formulae: I Example:

cbi $12,7 ; Clear bit 7 in Port D

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

69

CBR - Clear Bits in Register

Description:

Clears the specified bits in register Rd. Performs the logical AND between the contents of register Rd and the complement of the constant mask K. The result will be placed in register Rd.
Operation:

(i)

Rd Rd ($FF - K)
Syntax: Operands: Program Counter:

(i)

CBR Rd,K

16 d 31, 0 K 255

PC PC + 1

16 bit Opcode: See ANDI with K complemented.

Status Register (SREG) and Boolean Formulae: I S: V: T H S V 0 N Z C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
cbr cbr r16,$F0 r18,1 ; Clear upper nibble of r16 ; Clear bit 0 in r18

Words: 1 (2 bytes) Cycles: 1

70

AVR Core

AVR Core
CLC - Clear Carry Flag

Description:

Clears the Carry flag (C) in SREG (status register).

Operation:

(i)

C0
Syntax: Operands: Program Counter:

(i)

CLC
16 bit Opcode:

None

PC PC + 1

1001

0100

1000

1000

Status Register (SREG) and Boolean Formulae: I C: T H S V N Z C 0

0 Carry flag cleared

Example:
add clc r0,r0 ; Add r0 to itself ; Clear carry flag

Words: 1 (2 bytes) Cycles: 1

71

CLH - Clear Half Carry Flag

Description:

Clears the Half Carry flag (H) in SREG (status register).

Operation:

(i)

H0
Syntax: Operands: Program Counter:

(i)

CLH

None

PC PC + 1

16 bit Opcode:

1001

0100

1101

1000

Status Register (SREG) and Boolean Formulae: I T H 0 S V N Z C -

H:

0 Half Carry flag cleared

Example:
clh ; Clear the Half Carry flag

Words: 1 (2 bytes) Cycles: 1

72

AVR Core

AVR Core
CLI - Clear Global Interrupt Flag

Description:

Clears the Global Interrupt flag (I) in SREG (status register).

Operation:

(i)

I0
Syntax: Operands: Program Counter:

(i)

CLI
16 bit Opcode:

None

PC PC + 1

1001

0100

1111

1000

Status Register (SREG) and Boolean Formulae: I 0 T H S V N Z C -

I:

0 Global Interrupt flag cleared

Example:
cli in sei r11,$16 ; Disable interrupts ; Read port B ; Enable interrupts

Words: 1 (2 bytes) Cycles: 1

73

CLN - Clear Negative Flag

Description:

Clears the Negative flag (N) in SREG (status register).

Operation:

(i)

N0
Syntax: Operands: Program Counter:

(i)

CLN
16 bit Opcode:

None

PC PC + 1

1001

0100

1010

1000

Status Register (SREG) and Boolean Formulae: I T H S V N 0 Z C -

N:

0 Negative flag cleared

Example:
add cln r2,r3 ; Add r3 to r2 ; Clear negative flag

Words: 1 (2 bytes) Cycles: 1

74

AVR Core

AVR Core
CLR - Clear Register

Description:

Clears a register. This instruction performs an Exclusive OR between a register and itself. This will clear all bits in the register.
Operation:

(i)

Rd Rd Rd
Syntax: Operands: Program Counter:

(i)

CLR Rd

0 d 31

PC PC + 1

16 bit Opcode: (see EOR Rd,Rd)

0010

01dd

dddd

dddd

Status Register (SREG) and Boolean Formulae: I S: T 0 Cleared 0 Cleared 0 Cleared 1 Set H S 0 V 0 N 0 Z 1 C -

V:

N:

Z:

R (Result) equals Rd after the operation.

Example:
clr loop: inc ... cpi r18,$50 ; Compare r18 to $50 r18 r18 ; clear r18 ; increase r18

brne loop

Words: 1 (2 bytes) Cycles: 1

75

CLS - Clear Signed Flag

Description:

Clears the Signed flag (S) in SREG (status register).

Operation:

(i)

S0
Syntax: Operands: Program Counter:

(i)

CLS
16 bit Opcode:

None

PC PC + 1

1001

0100

1100

1000

Status Register (SREG) and Boolean Formulae: I T H S 0 V N Z C -

S:

0 Signed flag cleared

Example:
add cls r2,r3 ; Add r3 to r2 ; Clear signed flag

Words: 1 (2 bytes) Cycles: 1

76

AVR Core

AVR Core
CLT - Clear T Flag
Description:

Clears the T flag in SREG (status register).

Operation:

(i)

T0
Syntax: Operands: Program Counter:

(i)

CLT
16 bit Opcode:

None

PC PC + 1

1001

0100

1110

1000

Status Register (SREG) and Boolean Formulae: I T 0 H S V N Z C -

T:

0 T flag cleared

Example:
clt ; Clear T flag

Words: 1 (2 bytes) Cycles: 1

77

CLV - Clear Overflow Flag

Description:

Clears the Overflow flag (V) in SREG (status register).

Operation:

(i)

V0
Syntax: Operands: Program Counter:

(i)

CLV
16 bit Opcode:

None

PC PC + 1

1001

0100

1011

1000

Status Register (SREG) and Boolean Formulae: I T H S V 0 N Z C -

V:

0 Overflow flag cleared

Example:
add clv r2,r3 ; Add r3 to r2 ; Clear overflow flag

Words: 1 (2 bytes) Cycles: 1

78

AVR Core

AVR Core
CLZ - Clear Zero Flag
Description:

Clears the Zero flag (Z) in SREG (status register).

Operation:

(i)

Z0
Syntax: Operands: Program Counter:

(i)

CLZ
16 bit Opcode:

None

PC PC + 1

1001

0100

1001

1000

Status Register (SREG) and Boolean Formulae: I T H S V N Z 0 C -

Z:

0 Zero flag cleared

Example:
add clz r2,r3 ; Add r3 to r2 ; Clear zero

Words: 1 (2 bytes) Cycles: 1

79

COM - Ones Complement

Description:

This instruction performs a ones complement of register Rd.

Operation:

(i)

Rd $FF - Rd
Syntax: Operands: Program Counter:

(i)

COM Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0000

Status Register (SREG) and Boolean Formulae: I T H S V 0 N Z C 1

S:

NV For signed tests. 0 Cleared. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; Cleared otherwise. 1 Set.

V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
com breq ... zero: nop ; Branch destination (do nothing) r4 zero ; Take ones complement of r4 ; Branch if zero

Words: 1 (2 bytes) Cycles: 1

80

AVR Core

AVR Core
CP - Compare
Description:

This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All conditional branches can be used after this instruction.
Operation:

(i)

Rd - Rr
Syntax: Operands: Program Counter:

(i)

CP Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0001

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I H: T H S V N Z C

Rd3 Rr3+ Rr3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rd7 R7+ Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. Rd7 Rr7 +Rr7 R7+ R7 Rd7 Set if the result is $00; cleared otherwise. Rd7 Rr7+ Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) after the operation.

Example:
cp r4,r19 ; Compare r4 with r19 ; Branch if r4 <> r19 ; Branch destination (do nothing) brne noteq ... noteq: nop

Words: 1 (2 bytes) Cycles: 1

81

CPC - Compare with Carry

Description:

This instruction performs a compare between two registers Rd and Rr and also takes into account the previous carry. None of the registers are changed. All conditional branches can be used after this instruction.
Operation:

(i)

Rd - Rr - C
Syntax: Operands: Program Counter:

(i)

CPC Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0000

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I H: T H S V N Z C

Rd3 Rr3+ Rr3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7+ Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Z Previous value remains unchanged when the result is zero; cleared otherwise. Rd7 Rr7+ Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) after the operation.

Example:
; Compare r3:r2 with r1:r0 cp cpc brne ... noteq: nop ; Branch destination (do nothing) r2,r0 r3,r1 noteq ; Compare low byte ; Compare high byte ; Branch if not equal

Words: 1 (2 bytes) Cycles: 1

82

AVR Core

AVR Core
CPI - Compare with Immediate
Description:

This instruction performs a compare between register Rd and a constant. The register is not changed. All conditional branches can be used after this instruction.
Operation:

(i)

Rd - K
Syntax: Operands: Program Counter:

(i)

CPI Rd,K
16 bit Opcode:

16 d 31, 0 K 255

PC PC + 1

0011

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formulae: I H: T H S V N Z C

Rd3 K3+ K3 R3+ R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 K7 R7 +Rd7 K7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 K7 +K7 R7+ R7 Rd7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) after the operation.

Example:
cpi brne ... error: nop ; Branch destination (do nothing) r19,3 error ; Compare r19 with 3 ; Branch if r19<>3

Words: 1 (2 bytes) Cycles: 1

83

CPSE - Compare Skip if Equal

Description:

This instruction performs a compare between two registers Rd and Rr, and skips the next instruction if Rd = Rr.
Operation:

(i)

If Rd = Rr then PC PC + 2 (or 3) else PC PC + 1

Syntax: Operands: Program Counter:

(i)

CPSE Rd,Rr

0 d 31, 0 r 31

PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a two word instruction

16 bit Opcode:

0001

00rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I Example:

inc cpse neg nop r4 r4,r0 r4 ; Increase r4 ; Compare r4 to r0 ; Only executed if r4<>r0 ; Continue (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

84

AVR Core

AVR Core
DEC - Decrement
Description:

Subtracts one -1- from the contents of register Rd and places the result in the destination register Rd. The C flag in SREG is not affected by the operation, thus allowing the DEC instruction to be used on a loop counter in multiple-precision computations. When operating on unsigned values, only BREQ and BRNE branches can be expected to perform consistently. When operating on twos complement values, all signed branches are available.
Operation:

(i)

Rd Rd - 1
Syntax: Operands: Program Counter:

(i)

DEC Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

1010

Status Register and Boolean Formulae: I S: T H S V N Z C -

NV For signed tests. R7 R6 R5 R4 R3 R2 R1 R0 Set if twos complement overflow resulted from the operation; cleared otherwise. Twos complement overflow occurs if and only if Rd was $80 before the operation. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; Cleared otherwise.

V:

N:

Z:

R (Result) equals Rd after the operation.

Example:
ldi loop: add dec nop r17,$10 r1,r2 r17 ; Load constant in r17 ; Add r2 to r1 ; Decrement r17 ; Branch if r17<>0 ; Continue (do nothing)

brne loop

Words: 1 (2 bytes) Cycles: 1

85

ELPM - Extended Load Program Memory

Description:

Loads one byte pointed to by the (RAMPZ, Z) register into register 0 (R0). This instruction features a 100% space effective constant initialization or constant data fetch. The program memory is organized in 16 bits words and the LSB of the (RAMPZ, Z) (17 bits) pointer selects either low byte (0) or high byte (1). This instruction can address 128K bytes (64K words) of program memory.
Operation: Comment:

(i)

R0 (RAMPZ, Z)
Syntax: Operands:

(RAMPZ, Z) points to program memory

Program Counter:

(i)

ELPM
16 bit Opcode:

None

PC PC + 1

1001

0101

1101

1000

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi elpm r31 r30,$F0 ; Clear Z high byte ; Set Z low byte ; Load constant from program ; memory pointed to by Z (r31:r30)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 3

86

AVR Core

AVR Core
EOR - Exclusive OR
Description:

Performs the logical EOR between the contents of register Rd and register Rr and places the result in the destination register Rd.
Operation:

(i)

Rd Rd Rr
Syntax: Operands: Program Counter:

(i)

EOR Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0010

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I S: V: T H S V 0 N Z C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
eor eor r4,r4 r0,r22 ; Clear r4 ; Bitwise exclusive or between r0 and r22

Words: 1 (2 bytes) Cycles: 1

87

ICALL - Indirect Call to Subroutine

Description:

Indirect call of a subroutine pointed to by the Z (16 bits) pointer register in the register file. The Z pointer register is 16 bits wide and allows call to a subroutine within the current 64K words (128K bytes) section in the program memory space.
Operation:

(i) (ii)

PC(15-0) Z(15 - 0)Devices with 16 bits PC, 128K bytes program memory maximum. PC(15-0) Z(15 - 0)Devices with 22 bits PC, 8M bytes program memory maximum. PC(21-16) is unchanged
Syntax: Operands: Program Counter: Stack

(i)

ICALL

None

See Operation

STACK PC+1 SP SP-2 (2 bytes, 16 bits) STACK PC+1 SP SP-3 (3 bytes, 22 bits)

(ii)

ICALL

None

See Operation

16 bit Opcode:

1001

0101

XXXX

1001

Status Register (SREG) and Boolean Formulae: I Example:

mov icall r30,r0 ; Set offset to call table ; Call routine pointed to by r31:r30

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 3

88

AVR Core

AVR Core
IJMP - Indirect Jump
Description:

Indirect jump to the address pointed to by the Z (16 bits) pointer register in the register file. The Z pointer register is 16 bits wide and allows jump within the current 64K words (128K bytes) section of program memory.

Operation:

(i) (ii)

PC Z(15 - 0) Devices with 16 bits PC, 128K bytes program memory maximum. PC(15-0) Z(15-0) Devices with 22 bits PC, 8M bytes program memory maximum. PC(21-16) is unchanged
Syntax: Operands: Program Counter: Stack

(ii) (iii)

IJMP IJMP
16 bit Opcode:

None None

See Operation See Operation

Not Affected Not Affected

1001

0100

XXXX

1001

Status Register (SREG) and Boolean Formulae: I Example:

mov ijmp r30,r0 ; Set offset to jump table ; Jump to routine pointed to by r31:r30

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

89

IN - Load an I/O Port to Register

Description:

Loads data from the I/O Space (Ports, Timers, Configuration registers etc.) into register Rd in the register file.
Operation:

(i)

Rd P
Syntax: Operands: Program Counter:

(i)

IN Rd,P
16 bit Opcode:

0 d 31, 0 P 63

PC PC + 1

1011

0PPd

dddd

PPPP

Status Register (SREG) and Boolean Formulae: I Example:

in cpi breq ... exit: nop ; Branch destination (do nothing) r25,$16 r25,4 exit ; Read Port B ; Compare read value to constant ; Branch if r25=4

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

90

AVR Core

AVR Core
INC - Increment
Description:

Adds one -1- to the contents of register Rd and places the result in the destination register Rd. The C flag in SREG is not affected by the operation, thus allowing the INC instruction to be used on a loop counter in multiple-precision computations. When operating on unsigned numbers, only BREQ and BRNE branches can be expected to perform consistently. When operating on twos complement values, all signed branches are available.
Operation:

(i)

Rd Rd + 1
Syntax: Operands: Program Counter:

(i)

INC Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0011

Status Register and Boolean Formulae: I S: T NV For signed tests. V: R7 R6 R5 R4 R3 R2 R1 R0 Set if twos complement overflow resulted from the operation; cleared otherwise. Twos complement overflow occurs if and only if Rd was $7F before the operation. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4R3 R2 R1 R0 Set if the result is $00; Cleared otherwise. H S V N Z C -

N:

Z:

R (Result) equals Rd after the operation.

Example:
clr loop: inc ... cpi brne nop r22,$4F loop ; Compare r22 to $4f ; Branch if not equal ; Continue (do nothing) r22 r22 ; clear r22 ; increment r22

Words: 1 (2 bytes)
Cycles: 1

91

JMP - Jump
Description:

Jump to an address within the entire 4M (words) program memory. See also RJMP.
Operation:

(i)

PC k
Syntax: Operands: Program Counter: Stack

(i)

JMP k
32 bit Opcode:

0 k 4M

PC k

Unchanged

1001 kkkk

010k kkkk

kkkk kkkk

110k kkkk

Status Register (SREG) and Boolean Formulae: I T H S V N Z C -

Example:
mov jmp ... farplc: nop ; Jump destination (do nothing) r1,r0 farplc ; Copy r0 to r1 ; Unconditional jump

Words: 2 (4 bytes) Cycles: 3

92

AVR Core

AVR Core
LD - Load Indirect from SRAM to Register using Index X
Description:

Loads one byte indirect from SRAM, I/O location or register file to register. This memory location is pointed to by the X (16 bits) pointer register in the register file. Memory access is limited to the current SRAM, I/O location or register file page of 64K bytes. The X pointer register can either be left unchanged after the operation, or it can be incremented or decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the X pointer register. The results loaded by the following instructions are undefined. ld XL, X+ ld XH, X+ ld XL, -X ld XH, -X
Using the X pointer: Operation:

Comment:

(i) (ii) (iii)

Rd (X) Rd (X) XX-1

Syntax:

XX+1 Rd (X)
Operands:

X: Unchanged X: Post incremented X: Pre decremented

Program Counter:

(i) (ii) (iii)

LD Rd, X LD Rd, X+ LD Rd,-X

0 d 31 0 d 31 0 d 31

PC PC + 1 PC PC + 1 PC PC + 1

16 bit Opcode :

(i) (ii) (iii)

1001 1001 1001

000d 000d 000d

dddd dddd dddd

1100 1101 1110

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi ld ld ldi ld ld r27 r26,$1F r0,X+ r1,X r26,$60 r2,X r3,-X ; Clear X high byte ; Set X low byte to $1F ; Load r0 with memory loc. $1F-R31(X post inc) ; Load r1 with memory loc. $20-I/O loc. $00 ; Set X low byte to $60 ; Load r2 with memory loc. $60-SRAM loc. $60 ; Load r3 with memory loc. $5F-I/O loc. $3F(X pre dec)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

93

LD (LDD) - Load Indirect from SRAM to Register using Index Y

Description:

Loads one byte indirect with or without displacement from SRAM, I/O location or register file to register. This memory location is pointed to by the Y (16 bits) pointer register in the register file. Memory access is limited to the current SRAM, I/O location or register file page of 64K bytes. The Y pointer register can either be left unchanged after the operation, or it can be incremented or decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the Y pointer register. The results loaded by the following instructions are undefined. ld YL, Y+ ld YH, Y+ ld YL, -Y ld YH, -Y
Using the Y pointer: Operation:

Comment:

(i) (ii) (iii) (iiii)

Rd (Y) Rd (Y) YY-1 Rd (Y+q)

Syntax:

YY+1 Rd (Y)

Y: Unchanged Y: Post incremented Y: Pre decremented Y: Unchanged, q: Displacement

Program Counter:

Operands:

(i) (ii) (iii) (iiii)

LD Rd, Y LD Rd, Y+ LD Rd,-Y LDD Rd, Y+q

16 bit Opcode :

0 d 31 0 d 31 0 d 31 0 d 31, 0 q 63

PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1

(i) (ii) (iii) (iiii)

1000 1001 1001 10q0

000d 000d 000d qq0d

dddd dddd dddd dddd

1000 1001 1010 1qqq

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi ld ld ldi ld ld ldd r29 r28,$1F r0,Y+ r1,Y r28,$60 r2,Y r3,-Y r4,Y+2 ; Clear Y high byte ; Set Y low byte to $1F ; Load r0 with memory loc. $1F-R31(Y post inc) ; Load r1 with memory loc. $20-I/O loc. $00 ; Set Y low byte to $60 ; Load r2 with memory loc. $60-SRAM loc. $60 ; Load r3 with memory loc. $5F-I/O loc. $3F(Y pre dec) ; Load r4 with memory loc. $61-SRAM loc. $61

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

94

AVR Core

AVR Core
LD (LDD) - Load Indirect From SRAM to Register using Index Z
Description:

Loads one byte indirectly with or without displacement from SRAM, I/O location or register file to register. This memory location is pointed to by the Z (16 bits) pointer register in the register file. Memory access is limited to the current SRAM, I/O location or register file page of 64K bytes. The Z pointer register can either be left unchanged after the operation, or it can be incremented or decremented. These features are especially suited for stack pointer usage of the Z pointer register, however because the Z pointer register can be used for indirect subroutine calls, indirect jumps and table lookup, it is often more convenient to use the X or Y pointer as a dedicated stack pointer. For using the Z pointer for table lookup in program memory see the LPM and ELPM instructions. The results loaded by the following instructions are undefined. ld ZL, Z+ ld ZH, Z+ ld ZL, -Z ld ZH, -Z
Using the Z pointer: Operation:

Comment:

(i) (ii) (iii) (iiii)

Rd (Z) Rd (Z) Z Z -1 Rd (Z+q)

Syntax:

ZZ+1 Rd (Z)

Z: Unchanged Z: Post increment Z: Pre decrement Z: Unchanged, q: Displacement

Program Counter:

Operands:

(i) (ii) (iii) (iiii)

LD Rd, Z LD Rd, Z+ LD Rd,-Z LDD Rd, Z+q

16 bit Opcode :

0 d 31 0 d 31 0 d 31 0 d 31, 0 q 63

PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1

(i) (ii) (iii) (iiii)

1000 1001 1001 10q0

000d 000d 000d qq0d

dddd dddd dddd dddd

0000 0001 0010 0qqq

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi ld ld ldi ld ld ldd r29 r28,$10 r0,Z+ r1,Z r28,$60 r2,Z r3,-Z r4,Z+2 ; Clear Z high byte ; Set Z low byte to $10 ; Load r0 with memory loc. $10-R16(Z post inc) ; Load r1 with memory loc. $11-R17 ; Set Z low byte to $60 ; Load r2 with memory loc. $60-SRAM loc. $60 ; Load r3 with memory loc. $5F-I/O loc. $3F(Z pre dec) ; Load r4 with memory loc. $61-SRAM loc. $61

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

95

LDI - Load Immediate

Description:

Loads an 8 bit constant directly to register 16 to 31.

Operation:

(i)

Rd K
Syntax: Operands: Program Counter:

(i)

LDI Rd,K
16 bit Opcode:

16 d 31, 0 K 255

PC PC + 1

1110

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi lpm r31 r30,$F0 ; Clear Z high byte ; Set Z low byte to $F0 ; Load constant from program ; memory pointed to by Z

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

96

AVR Core

AVR Core
LDS - Load Direct from SRAM
Description:

Loads one byte from the SRAM to a Register. A 16-bit address must be supplied. Memory access is limited to the current SRAM Page of 64K bytes. The LDS instruction uses the RAMPZ register to access memory above 64K bytes.

Operation:

(i)

Rd (k)
Syntax: Operands: Program Counter:

(i)

LDS Rd,k
32 bit Opcode:

0 d 31, 0 k 65535

PC PC + 2

1001 kkkk

000d kkkk

dddd kkkk

0000 kkkk

Status Register (SREG) and Boolean Formulae: I Example:

lds add sts r2,$FF00 r2,r1 $FF00,r2 ; Load r2 with the contents of SRAM location $FF00 ; add r1 to r2 ; Write back

T -

H -

S -

V -

N -

Z -

C -

Words: 2 (4 bytes) Cycles: 3

97

LPM - Load Program Memory

Description:

Loads one byte pointed to by the Z register into register 0 (R0). This instruction features a 100% space effective constant initialization or constant data fetch. The program memory is organized in 16 bits words and the LSB of the Z (16 bits) pointer selects either low byte (0) or high byte (1). This instruction can address the first 64K bytes (32K words) of program memory.
Operation: Comment:

(i)

R0 (Z)
Syntax: Operands:

Z points to program memory

Program Counter:

(i)

LPM
16 bit Opcode:

None

PC PC + 1

1001

0101

1100

1000

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi lpm r31 r30,$F0 ; Clear Z high byte ; Set Z low byte ; Load constant from program ; memory pointed to by Z (r31:r30)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 3

98

AVR Core

AVR Core
LSL - Logical Shift Left
Description:

Shifts all bits in Rd one place to the left. Bit 0 is cleared. Bit 7 is loaded into the C flag of the SREG. This operation effectively multiplies an unsigned value by two.
Operation:

(i) C b7 - - - - - - - - - - - - - - - - - - b0
Syntax: Operands:

0
Program Counter:

(i)

LSL Rd

0 d 31

PC PC + 1

16 bit Opcode: (see ADD Rd,Rd)

0000

11dd

dddd

dddd

Status Register (SREG) and Boolean Formulae: I H: S: V: Rd3 N V, For signed tests. N C (For N and C after the shift) Set if (N is set and C is clear) or (N is clear and C is set); Cleared otherwise (for values of N and C after the shift). R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Set if, before the shift, the MSB of Rd was set; cleared otherwise. T H S V N Z C

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
add lsl r0,r4 r0 ; Add r4 to r0 ; Multiply r0 by 2

Words: 1 (2 bytes) Cycles: 1

99

LSR - Logical Shift Right

Description:

Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides an unsigned value by two. The C flag can be used to round the result.
Operation:

0 b7 - - - - - - - - - - - - - - - - - - b0 C

Syntax:

Operands:

Program Counter:

(i)

LSR Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0110

Status Register (SREG) and Boolean Formulae: I S: V: T H S

N 0

N V, For signed tests. N C (For N and C after the shift) Set if (N is set and C is clear) or (N is clear and C is set); Cleared otherwise (for values of N and C after the shift). 0 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd0 Set if, before the shift, the LSB of Rd was set; cleared otherwise.

N: Z:

C:

R (Result) equals Rd after the operation.

Example:
add lsr r0,r4 r0 ; Add r4 to r0 ; Divide r0 by 2

Words: 1 (2 bytes) Cycles: 1

100

AVR Core

AVR Core
MOV - Copy Register
Description:

This instruction makes a copy of one register into another. The source register Rr is left unchanged, while the destination register Rd is loaded with a copy of Rr.
Operation:

(i)

Rd Rr
Syntax: Operands: Program Counter:

(i)

MOV Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0010

11rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I Example:

mov call ... check: cpi ... ret ; Return from subroutine r16,$11 ; Compare r16 to $11 r16,r0 check ; Copy r0 to r16 ; Call subroutine

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

101

MUL - Multiply
Description:

This instruction performs 8-bit 8-bit 16-bit unsigned multiplication.

Rr Multiplicand 8

Rd Multiplier 8

R1 Product High 16

R0 Product Low

The multiplicand Rr and the multiplier Rd are two registers. The 16-bit product is placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand and the multiplier is selected from R0 or R1 the result will overwrite those after multiplication.

Operation:

(i)

R1,R0 Rr Rd
Syntax: Operands: Program Counter:

(i)

MUL Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

1001

11rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae: I C: T H S V N Z C

R15 Set if bit 15 of the result is set; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:
mulr6,r5; Multiply r6 and r5 movr6,r1; Copy result back in r6:r5 movr5,r0; Copy result back in r6:r5

Words: 1 (2 bytes) Cycles: 2

Not available in AVR Embedded Core.

102

AVR Core

AVR Core
NEG - Twos Complement
Description:

Replaces the contents of register Rd with its twos complement; the value $80 is left unchanged.
Operation:

(i)

Rd $00 - Rd
Syntax: Operands: Program Counter:

(i)

NEG Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0001

Status Register (SREG) and Boolean Formulae: I H: T H S V N Z C

R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise NV For signed tests. R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a twos complement overflow from the implied subtraction from zero; cleared otherwise. A twos complement overflow will occur if and only if the contents of the Register after operation (Result) is $80. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; Cleared otherwise. R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0 Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C flag will be set in all cases except when the contents of Register after operation is $00.

S:

V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
sub neg positive: nop r11,r0 r11 ; Subtract r0 from r11 ; Branch if result positive ; Take twos complement of r11 ; Branch destination (do nothing) brpl positive

Words: 1 (2 bytes) Cycles: 1

103

NOP - No Operation
Description:

This instruction performs a single cycle No Operation.

Operation:

(i)

No
Syntax: Operands: Program Counter:

(i)

NOP
16 bit Opcode:

None

PC PC + 1

0000

0000

0000

0000

Status Register (SREG) and Boolean Formulae:

I Example:

T -

H -

S -

V -

N -

Z -

C -

clr ser out nop out

r16 r17 $18,r16

; Clear r16 ; Set r17 ; Write zeros to Port B ; Wait (do nothing)

$18,r17

; Write ones to Port B

Words: 1 (2 bytes) Cycles: 1

104

AVR Core

AVR Core
OR - Logical OR
Description:

Performs the logical OR between the contents of register Rd and register Rr and places the result in the destination register Rd.
Operation:

(i)

Rd Rd v Rr
Syntax: Operands: Program Counter:

(i)

OR Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0010

10rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae:

I S: V:

T -

H -

V 0

C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
or bst brts ... ok: nop ; Branch destination (do nothing) r15,r16 r15,6 ok ; Do bitwise or between registers ; Store bit 6 of r15 in T flag ; Branch if T flag set

Words: 1 (2 bytes) Cycles: 1

105

ORI - Logical OR with Immediate

Description:

Performs the logical OR between the contents of register Rd and a constant and places the result in the destination register Rd.
Operation:

(i)

Rd Rd v K
Syntax: Operands: Program Counter:

(i)

ORI Rd,K
16 bit Opcode:

16 d 31, 0 K 255

PC PC + 1

0110

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formulae:

I S: V:

T -

H -

V 0

C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
ori ori r16,$F0 r17,1 ; Set high nibble of r16 ; Set bit 0 of r17

Words: 1 (2 bytes) Cycles: 1

106

AVR Core

AVR Core
OUT - Store Register to I/O port
Description:

Stores data from register Rr in the register file to I/O space (Ports, Timers, Configuration registers etc.).
Operation:

(i)

P Rr
Syntax: Operands: Program Counter:

(i)

OUT P,Rr
16 bit Opcode:

0 r 31, 0 P 63

PC PC + 1

1011

1PPr

rrrr

PPPP

Status Register (SREG) and Boolean Formulae:

I Example:

T -

H -

S -

V -

N -

Z -

C -

clr ser out nop out

r16 r17 $18,r16

; Clear r16 ; Set r17 ; Write zeros to Port B ; Wait (do nothing)

$18,r17

; Write ones to Port B

Words: 1 (2 bytes) Cycles: 1

107

POP - Pop Register from Stack

Description:

This instruction loads register Rd with a byte from the STACK.

Operation:

(i)

Rd STACK
Syntax: Operands: Program Counter:Stack

(i)

POP Rd

0 d 31

PC PC + 1SP SP + 1

16 bit Opcode:

1001

000d

dddd

1111

Status Register (SREG) and Boolean Formulae: I Example:

call ... routine: push push ... pop pop ret r13 r14 ; Restore r13 ; Restore r14 ; Return from subroutine r14 r13 ; Save r14 on the stack ; Save r13 on the stack routine ; Call subroutine

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

108

AVR Core

AVR Core
PUSH - Push Register on Stack
Description:

This instruction stores the contents of register Rr on the STACK.

Operation:

(i)

STACK Rr

Syntax:

Operands:

Program Counter:Stack:

(i)

PUSH Rr
16 bit Opcode:

0 r 31

PC PC + 1SP SP - 1

1001

001d

dddd

1111

Status Register (SREG) and Boolean Formulae: I Example:

call ... routine: push push ... pop pop ret r13 r14 ; Restore r13 ; Restore r14 ; Return from subroutine r14 r13 ; Save r14 on the stack ; Save r13 on the stack routine ; Call subroutine

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

109

RCALL - Relative Call to Subroutine

Description:

Calls a subroutine within 2K words (4K bytes). The return address (the instruction after the RCALL) is stored onto the stack. (See also CALL).
Operation:

(i) (ii)

PC PC + k + 1 PC PC + k + 1
Syntax:

Devices with 16 bits PC, 128K bytes program memory maximum. Devices with 22 bits PC, 8M bytes program memory maximum.
Operands: Program Counter: Stack

(i)

RCALL k

-2K k 2K -2K k 2K

PC PC + k + 1 PC PC + k + 1

STACK PC+1 SP SP-2 (2 bytes, 16 bits) STACK PC+1 SP SP-3 (3 bytes, 22 bits)

(ii)

RCALL k

16 bit Opcode:

1101

kkkk

kkkk

kkkk

Status Register (SREG) and Boolean Formulae: I Example:

rcall ... routine: push ... pop ret r14 ; Restore r14 ; Return from subroutine r14 ; Save r14 on the stack routine ; Call subroutine

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 3

110

AVR Core

AVR Core
RET - Return from Subroutine
Description:

Returns from subroutine. The return address is loaded from the STACK.
Operation:

(i) (ii)

PC(15-0) STACK Devices with 16 bits PC, 128K bytes program memory maximum. PC(21-0) STACKDevices with 22 bits PC, 8M bytes program memory maximum.
Syntax: Operands: Program Counter: Stack

(i) (ii)

RET RET
16 bit Opcode:

None None

See Operation See Operation

SPSP+2,(2 bytes,16 bits pulled) SPSP+3,(3 bytes,22 bits pulled)

1001

0101

0XX0

1000

Status Register (SREG) and Boolean Formulae: I Example:

call ... routine: push ... pop ret r14 ; Restore r14 ; Return from subroutine r14 ; Save r14 on the stack routine ; Call subroutine

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 4

111

RETI - Return from Interrupt

Description:

Returns from interrupt. The return address is loaded from the STACK and the global interrupt flag is set.
Operation:

(i) (ii)

PC(15-0) STACK Devices with 16 bits PC, 128K bytes program memory maximum. PC(21-0) STACKDevices with 22 bits PC, 8M bytes program memory maximum.
Syntax: Operands: Program Counter: Stack

(i) (ii)

RETI RETI
16 bit Opcode:

None None

See Operation See Operation

SP SP +2 (2 bytes, 16 bits) SP SP +3 (3 bytes, 22 bits)

1001

0101

0XX1

1000

Status Register (SREG) and Boolean Formulae: I 1 I: T H S V N Z C -

1 The I flag is set.

Example:
... extint: push ... pop reti r0 ; Restore r0 ; Return and enable interrupts r0 ; Save r0 on the stack

Words: 1 (2 bytes) Cycles: 4

112

AVR Core

AVR Core
RJMP - Relative Jump
Description:

Relative jump to an address within PC-2K and PC + 2K (words). In the assembler, labels are used instead of relative operands. For AVR microcontrollers with program memory not exceeding 4K words (8K bytes) this instruction can address the entire memory from every address location.
Operation:

(i)

PC PC + k + 1
Syntax: Operands: Program Counter: Stack

(i)

RJMP k
16 bit Opcode:

-2K k 2K

PC PC + k + 1

Unchanged

1100

kkkk

kkkk

kkkk

Status Register (SREG) and Boolean Formulae: I Example:

cpi brne rjmp error: add inc ok: nop r16,$42 error ok r16,r17 r16 ; Compare r16 to $42 ; Branch if r16 <> $42 ; Unconditional branch ; Add r17 to r16 ; Increment r16 ; Destination for rjmp (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

113

ROL - Rotate Left trough Carry

Description:

Shifts all bits in Rd one place to the left. The C flag is shifted into bit 0 of Rd. Bit 7 is shifted into the C flag.
Operation:

C b7 - - - - - - - - - - - - - - - - - - b0 C

Syntax:

Operands:

Program Counter:

(i)

ROL Rd

0 d 31

PC PC + 1

16 bit Opcode: (see ADC Rd,Rd)

0001

11dd

dddd

dddd

Status Register (SREG) and Boolean Formulae: I H: S: V: Rd3 N V, For signed tests. N C (For N and C after the shift) Set if (N is set and C is clear) or (N is clear and C is set); Cleared otherwise (for values of N and C after the shift). R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Set if, before the shift, the MSB of Rd was set; cleared otherwise. T H S V N Z C

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
rolr15 brcsoneenc ... oneenc: nop ; Branch destination (do nothing) ; Rotate left ; Branch if carry set

Words: 1 (2 bytes) Cycles: 1

114

AVR Core

AVR Core
ROR - Rotate Right trough Carry
Description:

Shifts all bits in Rd one place to the right. The C flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C flag.
Operation:

C b7 - - - - - - - - - - - - - - - - - - b0 C

Syntax:

Operands:

Program Counter:

(i)

ROR Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0111

Status Register (SREG) and Boolean Formulae:

I S: V:

T -

H -

N V, For signed tests. N C (For N and C after the shift) Set if (N is set and C is clear) or (N is clear and C is set); Cleared otherwise (for values of N and C after the shift). R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd0 Set if, before the shift, the LSB of Rd was set; cleared otherwise.

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
rorr15 brcczeroenc ... zeroenc: nop ; Branch destination (do nothing) ; Rotate right ; Branch if carry cleared

Words: 1 (2 bytes) Cycles: 1

115

SBC - Subtract with Carry

Description:

Subtracts two registers and subtracts with the C flag and places the result in the destination register Rd.
Operation:

(i)

Rd Rd - Rr - C
Syntax: Operands: Program Counter:

(i)

SBC Rd,Rr

0 d 31, 0 r 31

PC PC + 1

16 bit Opcode:

0000

10rd

dddd

rrrr

Status Register and Boolean Formulae: I H: T H S V N Z C

Rd3 Rr3 + Rr3 R3 + R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7 +Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Z Previous value remains unchanged when the result is zero; cleared otherwise. Rd7 Rr7+ Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of the Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
; Subtract r1:r0 from r3:r2 sub sbc r2,r0 r3,r1 ; Subtract low byte ; Subtract with carry high byte

Words: 1 (2 bytes) Cycles: 1

116

AVR Core

AVR Core
SBCI - Subtract Immediate with Carry
Description:

Subtracts a constant from a register and subtracts with the C flag and places the result in the destination register Rd.
Operation:

(i)

Rd Rd - K - C
Syntax: Operands: Program Counter:

(i)

SBCI Rd,K

16 d 31, 0 K 255

PC PC + 1

16 bit Opcode:

0100

KKKK

dddd

KKKK

Status Register and Boolean Formulae: I H: T H S V N Z C

Rd3 K3 + K3 R3 + R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 K7 R7 +Rd7 K7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Z Previous value remains unchanged when the result is zero; cleared otherwise. Rd7 K7+ K7 R7 +R7 Rd7 Set if the absolute value of the constant plus previous carry is larger than the absolute value of Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
; Subtract $4F23 from r17:r16 subi r16,$23 sbci r17,$4F ; Subtract low byte ; Subtract with carry high byte

Words: 1 (2 bytes) Cycles: 1

117

SBI - Set Bit in I/O Register

Description:

Sets a specified bit in an I/O register. This instruction operates on the lower 32 I/O registers - addresses 0-31.
Operation:

(i)

I/O(P,b) 1
Syntax: Operands: Program Counter:

(i)

SBI P,b
16 bit Opcode:

0 P 31, 0 b 7

PC PC + 1

1001

1010

pppp

pbbb

Status Register (SREG) and Boolean Formulae: I Example:

out sbi in $1E,r0 $1C,0 r1,$1D ; Write EEPROM address ; Set read bit in EECR ; Read EEPROM data

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

118

AVR Core

AVR Core
SBIC - Skip if Bit in I/O Register is Cleared

Description:

This instruction tests a single bit in an I/O register and skips the next instruction if the bit is cleared. This instruction operates on the lower 32 I/O registers - addresses 0-31.
Operation:

(i)

If I/O(P,b) = 0 then PC PC + 2 (or 3) else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

SBIC P,b

0 P 31, 0 b 7

PC PC + 1, If condition is false, no skip. PC PC + 2, If next instruction is one word. PC PC + 3, If next instruction is JMP or CALL

16 bit Opcode:

1001

1001

pppp

pbbb

Status Register (SREG) and Boolean Formulae: I Example:

e2wait: sbic $1C,1 rjmp e2wait nop ; Skip next inst. if EEWE cleared ; EEPROM write not finished ; Continue (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed)

119

SBIS - Skip if Bit in I/O Register is Set

Description:

This instruction tests a single bit in an I/O register and skips the next instruction if the bit is set. This instruction operates on the lower 32 I/O registers - addresses 0-31.
Operation:

(i)

If I/O(P,b) = 1 then PC PC + 2 (or 3) else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

SBIS P,b

0 P 31, 0 b 7

PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a JMP or a CALL

16 bit Opcode:

1001

1011

pppp

pbbb

Status Register (SREG) and Boolean Formulae: I Example:

waitset: sbis $10,0 rjmp waitset nop ; Skip next inst. if bit 0 in Port D set ; Bit not set ; Continue (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed)

120

AVR Core

AVR Core
SBIW - Subtract Immediate from Word
Description:

Subtracts an immediate value (0-63) from a register pair and places the result in the register pair. This instruction operates on the upper four register pairs, and is well suited for operations on the pointer registers.
Operation:

(i)

Rdh:Rdl Rdh:Rdl - K
Syntax: Operands: Program Counter:

(i)

SBIW Rdl,K
16 bit Opcode:

dl {24,26,28,30}, 0 K 63

PC PC + 1

1001

0111

KKdd

KKKK

Status Register (SREG) and Boolean Formulae: I S: V: T H S V N Z C

N V, For signed tests. Rdh7 R15 Set if twos complement overflow resulted from the operation; cleared otherwise. R15 Set if MSB of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise. R15 Rdh7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

N:

Z:

C:

R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 = R15-R8, Rdl7-Rdl0=R7-R0).

Example:
sbiw sbiw r24,1 r28,63 ; Subtract 1 from r25:r24 ; Subtract 63 from the Y pointer(r29:r28)

Words: 1 (2 bytes) Cycles: 2

121

SBR - Set Bits in Register

Description:

Sets specified bits in register Rd. Performs the logical ORI between the contents of register Rd and a constant mask K and places the result in the destination register Rd.
Operation:

(i)

Rd Rd v K
Syntax: Operands: Program Counter:

(i)

SBR Rd,K
16 bit Opcode:

16 d 31, 0 K 255

PC PC + 1

0110

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formulae: I S: V: T H S V 0 N Z C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd after the operation.

Example:
sbr sbr r16,3 r17,$F0 ; Set bits 0 and 1 in r16 ; Set 4 MSB in r17

Words: 1 (2 bytes) Cycles: 1

122

AVR Core

AVR Core
SBRC - Skip if Bit in Register is Cleared

Description:

This instruction tests a single bit in a register and skips the next instruction if the bit is cleared.
Operation:

(i)

If Rr(b) = 0 then PC PC + 2 (or 3) else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

SBRC Rr,b

0 r 31, 0 b 7

PC PC + 1, If condition is false, no skip. PC PC + 2, If next instruction is one word. PC PC + 3, If next instruction is JMP or CALL

16 bit Opcode:

1111

110r

rrrr

Xbbb

Status Register (SREG) and Boolean Formulae: I Example:

sub sub nop r0,r1 r0,r1 ; Subtract r1 from r0 ; Skip if bit 7 in r0 cleared ; Only executed if bit 7 in r0 not cleared ; Continue (do nothing) sbrc r0,7

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed)

123

SBRS - Skip if Bit in Register is Set

Description:

This instruction tests a single bit in a register and skips the next instruction if the bit is set.
Operation:

(i)

If Rr(b) = 1 then PC PC + 2 (or 3) else PC PC + 1

Syntax:

Operands:

Program Counter:

(i)

SBRS Rr,b

0 r 31, 0 b 7

PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a JMP or a CALL

16 bit Opcode:

1111

111r

rrrr

Xbbb

Status Register (SREG) and Boolean Formulae: I Example:

sub sbrs neg nop r0,r1 r0,7 r0 ; Subtract r1 from r0 ; Skip if bit 7 in r0 set ; Only executed if bit 7 in r0 not set ; Continue (do nothing)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed)

124

AVR Core

AVR Core
SEC - Set Carry Flag
Description:

Sets the Carry flag (C) in SREG (status register).

Operation:

(i)

C1
Syntax: Operands: Program Counter:

(i)

SEC
16 bit Opcode:

None

PC PC + 1

1001

0100

0000

1000

Status Register (SREG) and Boolean Formulae: I C: T 1 Carry flag set H S V N Z C 1

Example:
sec adc r0,r1 ; Set carry flag ; r0=r0+r1+1

Words: 1 (2 bytes) Cycles: 1

125

SEH - Set Half Carry Flag

Description:

Sets the Half Carry (H) in SREG (status register).

Operation:

(i)

H1
Syntax: Operands: Program Counter:

(i)

SEH
16 bit Opcode:

None

PC PC + 1

1001

0100

0101

1000

Status Register (SREG) and Boolean Formulae: I H: T H 1 S V N Z C -

1 Half Carry flag set

Example:
seh ; Set Half Carry flag

Words: 1 (2 bytes) Cycles: 1

126

AVR Core

AVR Core
SEI - Set Global Interrupt Flag
Description:

Sets the Global Interrupt flag (I) in SREG (status register).

Operation:

(i)

I1
Syntax: Operands: Program Counter:

(i)

SEI
16 bit Opcode:

None

PC PC + 1

1001

0100

0111

1000

Status Register (SREG) and Boolean Formulae: I 1 I: T H S V N Z C -

1 Global Interrupt flag set

Example:
cli in sei r13,$16 ; Disable interrupts ; Read Port B ; Enable interrupts

Words: 1 (2 bytes) Cycles: 1

127

SEN - Set Negative Flag

Description:

Sets the Negative flag (N) in SREG (status register).

Operation:

(i)

N1
Syntax: Operands: Program Counter:

(i)

SEN
16 bit Opcode:

None

PC PC + 1

1001

0100

0010

1000

Status Register (SREG) and Boolean Formulae: I N: T H S V N 1 Z C -

1 Negative flag set

Example:
add sen r2,r19 ; Add r19 to r2 ; Set negative flag

Words: 1 (2 bytes) Cycles: 1

128

AVR Core

AVR Core
SER - Set all bits in Register
Description:

Loads $FF directly to register Rd.

Operation:

(i)

Rd $FF
Syntax: Operands: Program Counter:

(i)

SER Rd
16 bit Opcode:

16 d 31

PC PC + 1

1110

1111

dddd

1111

Status Register (SREG) and Boolean Formulae: I Example:

clr ser out nop out $18,r17 r16 r17 $18,r16 ; Clear r16 ; Set r17 ; Write zeros to Port B ; Delay (do nothing) ; Write ones to Port B

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

129

SES - Set Signed Flag

Description:

Sets the Signed flag (S) in SREG (status register).

Operation:

(i)

S1
Syntax: Operands: Program Counter:

(i)

SES
16 bit Opcode:

None

PC PC + 1

1001

0100

0100

1000

Status Register (SREG) and Boolean Formulae:

I S:

T -

H -

S 1

V -

N -

Z -

C -

1 Signed flag set

Example:
add ses r2,r19 ; Add r19 to r2 ; Set negative flag

Words: 1 (2 bytes) Cycles: 1

130

AVR Core

AVR Core
SET - Set T Flag
Description:

Sets the T flag in SREG (status register).

Operation:

(i)

T1
Syntax: Operands: Program Counter:

(i)

SET
16 bit Opcode:

None

PC PC + 1

1001

0100

0110

1000

Status Register (SREG) and Boolean Formulae: I T: T 1 1 T flag set H S V N Z C -

Example:
set ; Set T flag

Words: 1 (2 bytes) Cycles: 1

131

SEV - Set Overflow Flag

Description:

Sets the Overflow flag (V) in SREG (status register).

Operation:

(i)

V1
Syntax: Operands: Program Counter:

(i)

SEV
16 bit Opcode:

None

PC PC + 1

1001

0100

0011

1000

Status Register (SREG) and Boolean Formulae: I V: T H S V 1 N Z C -

1 Overflow flag set

Example:
add sev r2,r19 ; Add r19 to r2 ; Set overflow flag

Words: 1 (2 bytes) Cycles: 1

132

AVR Core

AVR Core
SEZ - Set Zero Flag
Description:

Sets the Zero flag (Z) in SREG (status register).

Operation:

(i)

Z1
Syntax: Operands: Program Counter:

(i)

SEZ
16 bit Opcode:

None

PC PC + 1

1001

0100

0001

1000

Status Register (SREG) and Boolean Formulae: I Z: T 1 Zero flag set H S V N Z 1 C -

Example:
add sez r2,r19 ; Add r19 to r2 ; Set zero flag

Words: 1 (2 bytes) Cycles: 1

133

SLEEP
Description:

This instruction sets the circuit in sleep mode defined by the MCU control register. When an interrupt wakes up the MCU from a sleep state, the instruction following the SLEEP instruction will be executed before the interrupt handler is executed.
Operation:

Syntax:

Operands:

Program Counter:

SLEEP
16 bit Opcode:

None

PC PC + 1

1001

0101

100X

1000

Status Register (SREG) and Boolean Formulae: I Example:

mov sleep r0,r11 ; Copy r11 to r0 ; Put MCU in sleep mode

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

134

AVR Core

AVR Core
ST - Store Indirect From Register to SRAM using Index X
Description:

Stores one byte indirect from Register to SRAM, I/O location or register file. This Memory location is pointed to by the X (16 bits) pointer register in the register file. Memory access is limited to the current SRAM, I/O location or register file Page of 64K bytes. The X pointer register can either be left unchanged after the operation, or it can be incremented or decremented. These features are especially suited for stack pointer usage of the X pointer register. The results stored by the following instructions are undefined. st X+, XL st X+, XH st -X, XL st -X, XH
Using the X pointer: Operation: Comment:

(i) (ii) (iii)

(X) Rr (X) Rr XX-1

Syntax:

X X+1 (X) Rr
Operands:

X: Unchanged X: Post incremented X: Pre decremented

Program Counter:

(i) (ii) (iii)

ST X, Rr ST X+, Rr ST -X, Rr
16 bit Opcode :

0 r 31 0 r 31 0 r 31

PC PC + 1 PC PC + 1 PC PC + 1

(i) (ii) (iii)

1001 1001 1001

001r 001r 001r

rrrr rrrr rrrr

1100 1101 1110

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi st st ldi st st r27 r26,$1F X+,r0 X,r1 r26,$60 X,r2 -X,r3 ; Clear X high byte ; Set X low byte to $1F ; Store r0 in memory loc. $1F-R31(X post inc) ; Store r1 in memory loc. $20-I/O loc. $00 ; Set X low byte to $60 ; Store r2 in memory loc. $60-SRAM loc. $60 ; Store r3 in memory loc. $5F-I/O loc. $3F(X pre dec)

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

135

ST (STD) - Store Indirect From Register to SRAM using Index Y

Description:

Stores one byte indirect with or without displacement from Register to SRAM. The SRAM location is pointed to by the Y (16 bits) pointer register in the register file. Memory access is limited to the current SRAM Page of 64K bytes. To access another SRAM page the RAMPY register in the I/O area has to be changed. The Y pointer register can either be left unchanged after the operation, or it can be incremented or decremented. These features are especially suited for stack pointer usage of the Y pointer register. The results stored by the following instructions are undefined. st Y+, YL st Y+, YH st -Y, YL st -Y, YH
Using the Y pointer: Operation:

Comment:

(i) (ii) (iii) (iiii)

(Y) Rr (Y) Rr YY-1 (Y+q) Rr

Syntax:

Y Y+1 (Y) Rr

Y: Unchanged Y: Post incremented Y: Pre decremented Y: Unchanged, q: Displacement

Program Counter:

Operands:

(i) (ii) (iii) (iiii)

ST Y, Rr ST Y+, Rr ST -Y, Rr STD Y+q, Rr

16 bit Opcode :

0 r 31 0 r 31 0 r 31 0 r 31, 0 q 63

PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1

(i) (ii) (iii) (iiii)

1000 1001 1001 10q0

001r 001r 001r qq1r

rrrr rrrr rrrr rrrr

1000 1001 1010 1qqq

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi st st ldi st st std r29 r28,$1F Y+,r0 Y,r1 r28,$60 Y,r2 -Y,r3 Y+2,r4 ; Clear Y high byte ; Set Y low byte to $1F ; Store r0 in memory loc. $1F-R31(Y post inc) ; Store r1 in memory loc. $20-I/O loc. $00 ; Set Y low byte to $60 ; Store r2 in memory loc. $60-SRAM loc. $60 ; Store r3 in memory loc. $5F-I/O loc. $3F(Y pre dec) ; Store r4 in memory loc. $61-SRAM loc. $61

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

136

AVR Core

AVR Core
ST (STD) - Store Indirect From Register to SRAM using Index Z
Description:

Stores one byte indirect with or without displacement from Register to SRAM. The SRAM location is pointed to by the Z (16 bits) pointer register in the register file. Memory access is limited to the current SRAM Page of 64K bytes. To access another SRAM page the RAMPZ register in the I/O area has to be changed. The Z pointer register can either be left unchanged after the operation, or it can be incremented or decremented. These features are very suited for stack pointer usage of the Z pointer register, but because the Z pointer register can be used for indirect subroutine calls, indirect jumps and table lookup it is often more convenient to use the X or Y pointer as a dedicated stack pointer. The results stored by the following instructions are undefined. st Z+, ZL st Z+, ZH st -Z, ZL st -Z, ZH
Using the Z pointer: Operation:

Comment:

(i) (ii) (iii) (iiii)

(Z) Rr (Z) Rr ZZ-1 (Z+q) Rr

Syntax:

Z Z+1 (Z) Rr

Z: Unchanged Z: Post incremented Z: Pre decremented Z: Unchanged, q: Displacement

Program Counter:

Operands:

(i) (ii) (iii) (iiii)

ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q, Rr

16 bit Opcode :

0 r 31 0 r 31 0 r 31 0 r 31, 0 q 63

PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1

(i) (ii) (iii) (iiii)

1000 1001 1001 10q0

001r 001r 001r qq1r

rrrr rrrr rrrr rrrr

0000 0001 0010 0qqq

Status Register (SREG) and Boolean Formulae: I Example:

clr ldi st st ldi st st std r31 r30,$10 Z+,r0 Z,r1 r30,$60 Z,r2 -Z,r3 Z+2,r4 ; Clear Z high byte ; Set Z low byte to $10 ; Store r0 in memory loc. $10-R16(Z post inc) ; Store r1 in memory loc. $11-R17 ; Set Z low byte to $60 ; Store r2 in memory loc. $60-SRAM loc. $60 ; Store r3 in memory loc. $5F-I/O loc. $3F(Z pre dec) ; Store r4 in memory loc. $61-SRAM loc. $61

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 2

137

STS - Store Direct to SRAM

Description:

Stores one byte from a Register to the SRAM. A 16-bit address must be supplied. Memory access is limited to the current SRAM Page of 64K bytes. The SDS instruction uses the RAMPZ register to access memory above 64K bytes.

Operation:

(i)

(k) Rr
Syntax: Operands: Program Counter:

(i)

STS k,Rr
32 bit Opcode:

0 r 31, 0 k 65535

PC PC + 2

1001 kkkk

001d kkkk

dddd kkkk

0000 kkkk

Status Register (SREG) and Boolean Formulae: I Example:

lds add sts r2,$FF00 r2,r1 $FF00,r2 ; Load r2 with the contents of SRAM location $FF00 ; add r1 to r2 ; Write back

T -

H -

S -

V -

N -

Z -

C -

Words: 2 (4 bytes) Cycles: 3

138

AVR Core

AVR Core
SUB - Subtract without Carry
Description:

Subtracts two registers and places the result in the destination register Rd.
Operation:

(i)

Rd Rd - Rr
Syntax: Operands: Program Counter:

(i)

SUB Rd,Rr
16 bit Opcode:

0 d 31, 0 r 31

PC PC + 1

0001

10rd

dddd

rrrr

Status Register and Boolean Formulae: I H: T H S V N Z C

Rd3 Rr3 +Rr3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7 +Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Rr7 +Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
sub brne ... noteq: nop ; Branch destination (do nothing) r13,r12 noteq ; Subtract r12 from r13 ; Branch if r12<>r13

Words: 1 (2 bytes) Cycles: 1

139

SUBI - Subtract Immediate

Description:

Subtracts a register and a constant and places the result in the destination register Rd. This instruction is working on Register R16 to R31 and is very well suited for operations on the X, Y and Z pointers.
Operation:

(i)

Rd Rd - K
Syntax: Operands: Program Counter:

(i)

SUBI Rd,K
16 bit Opcode:

16 d 31, 0 K 255

PC PC + 1

0101

KKKK

dddd

KKKK

Status Register and Boolean Formulae: I H: T H S V N Z C

Rd3 K3+K3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 K7 R7 +Rd7 K7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 K7 +K7 R7 +R7 Rd7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

S: V:

N:

Z:

C:

R (Result) equals Rd after the operation.

Example:
subir22,$11 brnenoteq ... noteq: nop ; Branch destination (do nothing) ; Subtract $11 from r22 ; Branch if r22<>$11

Words: 1 (2 bytes) Cycles: 1

140

AVR Core

AVR Core
SWAP - Swap Nibbles
Description:

Swaps high and low nibbles in a register.

Operation:

(i)

R(7-4) Rd(3-0), R(3-0) Rd(7-4)

Syntax: Operands: Program Counter:

(i)

SWAP Rd
16 bit Opcode:

0 d 31

PC PC + 1

1001

010d

dddd

0010

Status Register and Boolean Formulae: I T H S V N Z C -

R (Result) equals Rd after the operation.

Example:
inc swap inc swap r1 r1 r1 r1 ; Increment r1 ; Swap high and low nibble of r1 ; Increment high nibble of r1 ; Swap back

Words: 1 (2 bytes) Cycles: 1

141

TST - Test for Zero or Minus

Description:

Tests if a register is zero or negative. Performs a logical AND between a register and itself. The register will remain unchanged.
Operation:

(i)

Rd Rd Rd
Syntax: Operands: Program Counter:

(i)

TST Rd
16 bit Opcode:

0 d 31

PC PC + 1

0010

00dd

dddd

dddd

Status Register and Boolean Formulae: I S: V: T H S V 0 N Z C -

N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.

N:

Z:

R (Result) equals Rd.

Example:
tst ... zero: nop ; Branch destination (do nothing) r0 ; Test r0 ; Branch if r0=0 breq zero

Words: 1 (2 bytes) Cycles: 1

142

AVR Core

AVR Core
WDR - Watchdog Reset
Description:

This instruction resets the Watchdog Timer. This instruction must be executed within a limited time given by the WD prescaler. See the Watchdog Timer hardware specification.
Operation:

(i)

WD timer restart.
Syntax: Operands: Program Counter:

(i)

WDR
16 bit Opcode:

None

PC PC + 1

1001

0101

101X

1000

Status Register and Boolean Formulae: I Example:

wdr ; Reset watchdog timer

T -

H -

S -

V -

N -

Z -

C -

Words: 1 (2 bytes) Cycles: 1

143

144

AVR Core

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