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    Week 3

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    Marcos Infante
    The document describes a logic family with NAND and NOR gates that has specific static discipline requirements. It provides the low and high noise margins, as well as the width of the forbidden region for the inverter. It then calculates the minimum pull-up resistor values needed for the inverter, NAND, and NOR gates to meet the requirements. Finally, it calculates the maximum power consumption for each gate.

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    Week 3

    Uploaded by

    Marcos Infante
    2K views11 pages
    The document describes a logic family with NAND and NOR gates that has specific static discipline requirements. It provides the low and high noise margins, as well as the width of the forbidden region for the inverter. It then calculates the minimum pull-up resistor values needed for the inverter, NAND, and NOR gates to meet the requirements. Finally, it calculates the maximum power consumption for each gate.

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    The document describes a logic family with NAND and NOR gates that has specific static discipline requirements. It provides the low and high noise margins, as well as the width of the forbidden region for the inverter. It then calculates the minimum pull-up resistor values needed for the inverter, NAND, and NOR gates to meet the requirements. Finally, it calculates the maximum power consumption for each gate.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    2K views11 pages

    Week 3

    Uploaded by

    Marcos Infante
    The document describes a logic family with NAND and NOR gates that has specific static discipline requirements. It provides the low and high noise margins, as well as the width of the forbidden region for the inverter. It then calculates the minimum pull-up resistor values needed for the inverter, NAND, and NOR gates to meet the requirements. Finally, it calculates the maximum power consumption for each gate.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 11
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    The passage describes a MOSFET-based logic family and calculates several of its characteristics like noise margins and required pull-up resistor values.

    The maximum positive voltage at v is 7.5V. The minimum negative voltage is -3V. The maximum currents through D1 and D2 are 1A.

    The static discipline required for the family is: VS=5.0V, VOH=4.5V, VIH=4.0V, VIL=1.5V, VOL=1.0V.

    1.

    H3P1: A LOGIC FAMILY


    (9 points possible) For many purposes of gate design, we can model a MOSFET used as a switch simply as as an ideal switch and an "on-state resistor" RON. This is the SR model. Assuming this model for the MOSFET, consider the inverter in the figure. This inverter is intended to be used as an element in a logic family with NAND and NOR gates.

    The static discipline required for this family is:

    VS=5.0V, VOH=4.5V, VIH=4.0V, VIL=1.5V, VOL=1.0V.


    What is the low noise margin (in Volts)?

    What is the high noise margin (in Volts)?

    What is the width of the forbidden region (in Volts)?

    Suppose that the threshold voltage for the MOSFET is and

    VT=2.0V

    RON=7000.0. RPuI (in Ohms) for

    What is the minimum value of the pullup resistor

    which this inverter can obey the required static discipline?

    Now, consider the NAND gate of this family. What is the minimum value of the pullup resistor RPuA (in Ohms) for which this inverter can obey the required static discipline?

    How about the NOR gate of this family. What is the minimum value of the pullup resistor RPuO (in Ohms) for which this inverter can obey the required static discipline?

    Assume that we implemented this family with the minimum pullup resistors that you have already calculated. What is the maximum power (in Watts) consumed by the inverter?

    What is the maximum power (in Watts) consumed by the NAND?

    What is the maximum power (in Watts) consumed by the NOR?

    2. H3P2: GRAPHICAL INVERTER MODEL


    (7 points possible)

    A calculator uses digital logic to perform math functions, but a calculator was malfunctioning and not adding correctly. After much debugging, we discovered there was an inverter that had been malfunctioning. To fix the calculator we need to replace the inverter with a new one. We can draw our calculator as the system shown in Figure 1, where Network A has an output that is the input to our inverter and the output of the inverter is the input to Network B.

    Figure 1 shows the relevant static disciplines for Networks A and B. Figure 2 shows the graphical models for three inverters.

    Which one will ensure we invert correctly according to the static discplines of the two networks? Enter the letter label of the correct inverter.

    Give the minimum value of correct operation.

    VIL (in Volts) for the inverter to ensure

    Give the maximum value of correct operation.

    VIH (in Volts) for the inverter to ensure

    Give the maximum value of correct operation.

    VOL (in Volts) for the inverter to ensure

    Give the minimum value of correct operation.

    VOH (in Volts) for the inverter to ensure

    What is the high noise margin,

    NMH (in Volts), from the minimum

    and maximum values that you obtained?

    What is the low noise margin,

    NML (in Volts), from the minimum and

    maximum values that you obtained?

    3. H3P3
    (4 points possible) A nonlinear device Z has the i-v relationship shown below.

    This device is used in the circuit shown below, where "I" is the value of the current source.

    Assuming that

    I=10A, what is the value of the voltage vo (in Volts)?

    Now assuming that Volts)?

    I=3A, what is the value of the voltage vo (in

    Finally, for the last two parts assume that

    I=1A.

    What is the value of the voltage vo (in Volts)?

    What is the value of the voltage v1 (in Volts)?

    4. H3P4: DIODE LIMITER

    (4 points possible) In the circuit shown there are two ideal diodes, two resistors, two DC voltage sources, and an AC voltage source.

    The resistors both have the resistance DC sources is

    R=5.6k. The voltage of the

    V1=3.25V and V2=3.0V.

    An ideal diode has the characteristic shown:

    The AC voltage source puts out a symmetrical triangle wave that looks like:

    The peak voltage of this waveform is

    7.5V.

    What is the maximum positive voltage (in Volts) that can appear at v?

    What is the minimum (negative) voltage (in Volts) that can appear at v?

    What is the maximum current (in Amperes) that can go through diode D1?

    What is the maximum current (in Amperes) that can go through diode D2?

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