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    Asic

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    Immanuel Vinoth
    The document outlines the course plan for the VLSI Design subject taught in the second year of the Electronics and Communication Engineering department at Francis Xavier Engineering College. It includes 18 topics to be covered across 30 weeks, ranging from introduction to ASICs and logic design to logic synthesis, simulation, testing, floor planning, placement and routing. The course will use 5 specified reference books and be taught by instructor Femila Savio.

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    Asic

    Uploaded by

    Immanuel Vinoth
    137 views2 pages
    The document outlines the course plan for the VLSI Design subject taught in the second year of the Electronics and Communication Engineering department at Francis Xavier Engineering College. It includes 18 topics to be covered across 30 weeks, ranging from introduction to ASICs and logic design to logic synthesis, simulation, testing, floor planning, placement and routing. The course will use 5 specified reference books and be taught by instructor Femila Savio.

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    The document outlines the course plan for the VLSI Design subject taught in the second year of the Electronics and Communication Engineering department at Francis Xavier Engineering College. It includes 18 topics to be covered across 30 weeks, ranging from introduction to ASICs and logic design to logic synthesis, simulation, testing, floor planning, placement and routing. The course will use 5 specified reference books and be taught by instructor Femila Savio.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd
    Download as xls, pdf, or txt
    137 views2 pages

    Asic

    Uploaded by

    Immanuel Vinoth
    The document outlines the course plan for the VLSI Design subject taught in the second year of the Electronics and Communication Engineering department at Francis Xavier Engineering College. It includes 18 topics to be covered across 30 weeks, ranging from introduction to ASICs and logic design to logic synthesis, simulation, testing, floor planning, placement and routing. The course will use 5 specified reference books and be taught by instructor Femila Savio.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd
    Download as xls, pdf, or txt
    of 2

    FXEC/ECE/08-09/EVEN/ASI/CP/REV.

    NO- 0

    FRANCIS XAVIER ENGINEERING COLLEGE DEPARTMENT OF ECE COURSE PLAN

    SUB CODE : AN1625 SEM/YR/BRANCH:II / I / ME VLSI DESIGN

    SUB :ASIC DESIGN STAFF NAME: FEMILA SAVIO V

    REFERENCE BOOKS: R1 : M.J.S .Smith, "Application Specific Integrated Circuits, Addison -Wesley Longman Inc., 1997 R2 : Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, Prentice Hall PTR, 2003. R3 : Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2004 R4 : R. Rajsuman, System-on-a-Chip Design and Test. Santa Clara, CA: Artech House Publishers, 2000. R5 : F. Nekoogar. Timing Verification of Application-Specific Integrated Circuits (ASICs). Prentice Hall PTR, 1999.

    Lect. Unit No No I 1,2 3 4,5 6 7 8 9,10 11 12,13 14,15

    16 17,18 19 20,21 22 23,24 25-27 28,29 30

    Week no INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN Types of ASICs R1 18-30 1 Design flow R1 30-32 CMOS transistors R1 55-62 CMOS Design rules R1 72-74 Combinational Logic Cell R1 74-83 2 Sequential logic cell R1 84-88 Data path logic cell R1 89-112 Transistors as Resistors R1 131-135 Transistor Parasitic Capacitance R1 136-142 3 Logical effort-Library cell design, Library architecture R1 143-158 PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS II AND PROGRAMMABLE ASIC I/O CELLS Anti fuse R1 184-187 static RAM, EPROM and EEPROM technology R1 188-189 4 PREP benchmarks R1 193-194 Actel ACT R1 205-218 Xilinx LCA, Altera FLEX R1 218-223 Altera MAX R1 223-232 5 DC & AC inputs and outputs R1 246-266 Clock & Power inputs R1 267-272 Xilinx I/O blocks R1 272-275

    Topics to be covered

    Text

    Pages

    31,32 33 34 34 35 35 36 37 38,39 40 41,42 43 44 45,46 47 48,49 50 51,52 53 53 54,55 56,57 58,59 60,61 62

    PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC III DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY Actel ACT R1 289-297 6 Xilinx LCA R1 298-301 Xilinx EPLD, Altera MAX 5000 and 7000 R1 302-304 Altera MAX 9000 R1 304-305 Altera FLEX R1 305-305 Design systems R1 313-317 7 Logic Synthesis R1 318-320 Half gate ASIC R1 321-330 Schematic entry R1 342-359 Low level design language R1 359-366 PLA tools -EDIF R1 367-382 8 CFI design representation R1 383-387 IV LOGIC SYNTHESIS, SIMULATION AND TESTING Verilog and logic synthesis R1 594-606 VHDL and logic synthesis R1 607-618 types of simulation R1 655-656 9 boundary scan test R1 728-749 fault simulation R1 759-768 automatic test pattern generation R1 769-779 V ASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND ROUTING System partition, FPGA partitioning R1 823-825 FPGA partitioning R1 834-838 partitioning methods R1 838-851 10 floor planning R1 867-886 placement,physical design flow R1 887-909 global routing, detailed routing, special routing R1 924-952 circuit extraction & DRC R1 953-960

    Staff- in charge V.FEMILA SAVIO

    Verified By HOD

    Approved By PRINCIPAL

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