8085 features, Signal description

8085 features:
8085 is an 8-bit microprocessor. It is capable of addressing 64kbytes of memory. It requires a +5volts of power supply. 8085 operates on 3MHz clock. 8085 A-2 operates on maximum clock frequency 5MHz. It has 16 address lines, out of which 8 address lines are multiplexed with data lines. It is manufactured in NMOS technology It is available in 40 pin dual in line (DIP) package.

8085 Pin diagram:

8085 Signal Description:

Address & data lines: Address bus: 8085 has 16-bit address bus AD0-AD7 and A8-A15. In this lower address bus is multiplexed with data bus. A8-A15 lines are unidirectional and AD0-AD7 lines are bidirectional. Data bus: AD7-AD0 is 8-bit bidirectional data bus. It is multiplexed with lower order address bus. ALE: Address latch enable. It is used to de-multiplex AD0-AD7. It is connected to strobe input of latch which is used to separate address and data bus lines. It is issued in first T-state. Control & Status Signals: RD: Read control signal is issued to memory or IO device to read data from it. WR: Write control signal is issued to memory or IO device to write data into it. IO/M: It is a signal which is used to distinguish between IO operation and memory operation. It is also used in generating memory and IO, read and write control signals. S1, S0: these are status signals. Depending on the value on these lines, the type of operation being performed by the processor can be determined. Below table shows that information.

Power Supply and clock signals: Vcc: +5v power supply line Vss: electrical ground signal. X1, X2: crystal is connected between these pins. The frequency is internally divided by 2. The systems operates generally at 3MHz. Hence 6 MHz clock signal needs to be connected between X1, X2 lines. CLK (out): It is the clock output signal from processor, which can be used to clock other peripherals in the microprocessor based system. READY: This is used when the processor is reading or writing data to a slow peripheral. When this signal goes low processor inserts wait states, until it goes high. Reset Signals: RESET IN: when low signal is applied on this pin, 8085 resets and the microprocessor boots from 0000h location in memory i.e. PC is loaded with 0000h location. RESET OUT: when processor is reset, this signal goes high. This pin is connected to reset input of other peripherals. So when processor is reset, other peripherals are also reset. Serial IO lines: SID: serial input data, used to receive serial data. SOD: serial output data, used to send serial data Interrupt Signals: INTR: interrupt request is general purpose interrupt signal. The interrupting device needs to send the vector address also. INTA: is interrupt acknowledging signal. This signal indicates that processor has accepted the interrupt. RST7.5, RST6.5, RST5.5: These are external vectored interrupts. When these interrupt occurs, processor vectors to a specific location. TRAP: It is a non-mask able interrupt. DMA signals: HOLD: This line is used by DMA controller to request microprocessor for system bus. When this line goes high microprocessor completes its current bus cycle and issues system bus to DMA controller. HLDA: HOLD acknowledging signal. Processor acknowledges DMA request using this signal.

8085 Architecture
below figure shows the architecture of 8085 microprocessor.

The following are the different blocks in the 8085 processor. ALU: it is 8-bit ALU. It can perform arithmetic and logical operations on 8-bit data. If an operation needs to be performed on 16-bit data, it needs to be broken into two 8-bit parts and each 8-bit operation should be performed on each 8-bit data. It takes operand inputs from accumulator and a temporary register. Result of the operation is stored in accumulator. Depending on the result of operation, flags in flag register values will be changed. Flag register: As already explained contents of flag register will be changed according to the result of ALU operation. Below figure shows the flag register format of 8085.

Sign flag (S): when the result of ALU operation is negative sign flag is set. If the result is positive, then sign flag is reset. i. e. the D7 bit of accumulator is copied into the sign flag, as D7 anyhow contains sign. Zero flag (Z): when the result of ALU operation is zero, Zero flag is set. If the result is non-zero then flag is reset. Auxiliary carry (AC): If an ALU operation results in carry from lower nibble to upper nibble (or) bit D3 to bit D4, Auxiliary flag is set. Else it is reset. This flag is used in BCD arithmetic. Parity flag (P): If the result contains even number of ones, the flag is set else it is reset. So the parity flag is odd parity bit. Carry flag (CY): If the arithmetic operation results in carry, CY flag is set, else it is reset. Timing and Control unit: This is responsible for generation of control signals, such as RD, WR to interface peripherals. It also synchronizes all microprocessor operations. Instruction Register and Decoding: Instruction register holds instruction that is fetched from memory. Instruction decoder decodes the opcode (which is part of fetched instruction present in instruction register). Instruction register is not accessible to the programmer. Register Array:

8085 has six general purpose registers B, C, D, E, H, L. They can be used as pairs to hold 16-bit data as BC, DE, HL. Accumulator is 8-bit register which holds the results of operations as well as operand on which some operation needs to be performed. Flag register contains five flags, namely S, Z, CY, AC, P flags. 8085 has two 16- bit register PC, SP. PC always consists of address of next instruction to be executed. SP always points to top of stack. i.e. address of top memory location of stack. Stack is a data structure. It is used to store return addresses whenever call to subprograms or an interrupt occurs. Two temporary registers W, Z are also present. These are used to hold temporary results during execution. But these are not accessible to the user. Incrementer and decrementer address latch is for incrementing the PC content for every fetch cycle. Interrupt Controller:

8085 has 5 external interrupts. TRAP, INTR, RST 5.5, RST 6.5, and RST 7.5. Whenever processor gets interrupt it finishes current instruction execution and issues INTA (interrupt acknowledge) signal to the peripheral which raised the interrupt and goes to execute interrupt service routine. Interrupt controller controls the interrupts. Serial I/O control: Serial data can be sent out using SOD pin and serial data can be read from SID pin. It controls serial IO related operations.

Pin Diagram and Pin description of 8085

8085 is a 40 pin IC, The signals from the pins can be grouped as follows

1. Power supply and clock signals 2. Address bus 3. Data bus 4. Control and status signals 5. Interrupts and externally initiated signals 6. Serial I/O ports

1. Power supply and Clock frequency signals:

Vcc: + 5 volt power supply

Vss: Ground

X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator. The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally. CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor.

2. Address Bus:

A8 - A15: (output; 3-state) It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address;

3. Data bus:

AD0 - AD7 (input/output; 3-state) These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7.

In the subsequent IO / memory, read / write clock cycle the lines are used as data bus. The CPU may read or write out data through these lines.

4. Control and Status signals:

ALE (output) - Address Latch Enable.

It is an output signal used to give information of AD0-AD7 contents. It is a positive going pulse generated when a new operation is started by uP. When pulse goes high it indicates that AD0-AD7 are address. When it is low it indicates that the contents are data.

RD (output 3-state, active low) - Read memory or IO device. This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device

WR (output 3-state, active low) - Write memory or IO device. This indicates that the data on the data bus is to be written into the selected memory location or I/O device.

IO/M (output) - Select memory or an IO device. This status signal indicates that the read / write operation relates to whether the memory or I/O device.

It goes high to indicate an I/O operation. It goes low for memory operations.

5. Status Signals:

S1:

S2: It is used to know the type of current operation of the microprocessor.

Opcode fetch

Memory read

Memory write

I/O read

I/O write

Interrupt acknowledge

Halt

Hold

Reset

6. Interrupts and Externally initiated operations:

They are the signals initiated by an external device to request the microprocessor to do a particular task or work.

There are five hardware interrupts called, 1.TRAP 2.RST 7.5 3.RST 6.5 4.RST 5.5 5.INTA

On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA (Interrupt Acknowledge) signal.

Reset In (input, active low) This signal is used to reset the microprocessor. The program counter inside the microprocessor is set to zero. The buses are tri-stated. Reset Out (Output) It indicates CPU is being reset. Used to reset all the connected devices when the microprocessor is reset.

7. Direct Memory Access (DMA): Tri state devices:

When 2 or more devices are connected to a common bus, to prevent the devices from interfering with each other, the tristate gates are used to disconnect all devices except the one that is communicating at a given instant.

The CPU controls the data transfer operation between memory and I/O device. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly.

The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits.

HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data.

READY (input) Memory and I/O devices will have slower response compared to microprocessors. Before completing the present job such a slow peripheral may not be able to handle further data or control signal from CPU. The processor sets the READY signal after completing the present job to access the data. The microprocessor enters into WAIT state while the READY pin is disabled.

8. Single Bit Serial I/O ports:

SID (input) SOD (output)

- Serial input data line - Serial output data line

These signals are used for serial communication.