Scribd
Upload
151 views3 pages

RTL Design and VLSI Implementation of An Efficient Convolutional Encoder and Adaptive Viterbi Decoder

For more projects feel free to contact us [email protected] ; www.nanocdac.com Contact us : Mallikarjuna.V, 08297578555

Uploaded by

Nsrc Nano Scientifc
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
151 views3 pages

RTL Design and VLSI Implementation of An Efficient Convolutional Encoder and Adaptive Viterbi Decoder

For more projects feel free to contact us [email protected] ; www.nanocdac.com Contact us : Mallikarjuna.V, 08297578555

Uploaded by

Nsrc Nano Scientifc
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 3

The Floating-Point Unit of the Jaguar x86Core AIM: The main aim of the project is to design The Floating-Point

Unit of the Jaguar x 86 Cores. A !T"ACT: The AMD Jaguar x86 core uses a fully-synthesized, !8-"it nati#e floatingpoint unit $%&'( "uilt as a co-processor model) The Jaguar %&' supports se#eral x86 *+A extensions, including x8,, MM-, ++. through ++./)!, A.+, 01M'1, A2-, and % 60 instruction sets) The front end of the unit decodes t3o complex operations per cycle and uses a dedicated renamer $45(, free list $%1(, and retire 6ueue $47( for in order dispatch and retire) The %&' issues to the execution units 3ith a dedicated out-of-order, dual-issue scheduler) .xecution units source operands from a synthesized physical register file $&4%( and "ypass net3or8) The "ac8 end of the unit has t3o execution pipes9 the first pipe contains a #ector integer A1', a #ector integer M'1 unit, and a floating-point adder $%&A(: the second pipe contains a #ector integer A1', a store-con#ert unit, and a floating-point iterati#e multiplier $%&M() The implementation of the unit focused on lo3-po3er design and on #ectorized single-precision $+&( performance optimizations) The #erification of the unit re6uired complex pseudo-random and formal #erification techni6ues) The Jaguar %&' is "uilt in a !8nm 0M;+ process)

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No:

#$C% &IA'"AM:

%ig9 Jaguar %&' <loc8 Diagram)

T$$#!: -ilinx =)!*+., Modelsim6)/c) APP#ICATI$( A&)A(TA'*!:

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No:

The AMD Jaguar x86core is a fully synthesized, t3o-3ide, out-of-order superscalar core implemented in a !8nm 0M;+ process, targeted at lo3 po3er, lo3-cost form factors) Jaguar is the next-generation architecture of the AMD <o"cat x86 core, supporting many x86 *+A extensions, including the floating-point specific sets x8,, MM-, ++. through ++./)!, A.+, 01M'1, A2- and % 60) "*F*"*(C*!: 4upley, J), >AMD?s @Jaguar?9 A next generation lo3 po3er x86core,A Bot 0hips !/) AMD, <*;+ and Cernel De#eloper Duide $<CDD( for AMD %amily 6h Models EEh-E%h &rocessors, http9FF333)amd)com +ingh, T): <ell, J): +outhard, +): >Jaguar9 A 5ext-Deneration 1o3- &o3er x86-6/ 0ore,A *++00 !E G, pp) !- G) <urgess, <): 0ohen, <): Denman, M): Dundas, J): Caplan, D): 4upley, J): ><o"cat9 AMDHs 1o3-&o3er x86 &rocessor,A *... Micro, pp) 6-!I) A) +cherer, M) Dolden, 5) Juffa, +) Meier, +) ;"erman, B) &arto#i, %) Je"er, >An out-of-order three 3ay superscalar multimedia floating point unit,A in Digest of Technical &apers, *... *nt) +olid-+tate 0ircuits 0onf)

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No:

You might also like