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Lesson - 12: Direct Memory Access

Direct memory access (DMA) allows large blocks of data to be transferred between memory and external devices efficiently. A DMA controller facilitates DMA transfers, allowing data to be transferred directly without interrupting the CPU. It works by requesting and gaining control of the system bus to perform transfers while letting the CPU continue processing. DMA is useful for bulk transfers like moving large files between storage and memory.

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68 views17 pages

Lesson - 12: Direct Memory Access

Direct memory access (DMA) allows large blocks of data to be transferred between memory and external devices efficiently. A DMA controller facilitates DMA transfers, allowing data to be transferred directly without interrupting the CPU. It works by requesting and gaining control of the system bus to perform transfers while letting the CPU continue processing. DMA is useful for bulk transfers like moving large files between storage and memory.

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Naagaraaju Aaraadhyula
Copyright
© Attribution Non-Commercial (BY-NC)
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DEVICE DRIVERS AND INTERRUPTS SERVICE MECHANISM

Lesson-12: DIRECT MEMORY ACCESS

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

Multi-byte data set or burst of data or block of data A DMA is required when a multi-byte data set or a burst of data or a block of data is to be transferred between the external device and system or two systems. A device facilitates DMA transfer with a processing element (single purpose processor) and that device is called DMAC (DMA Controller).
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 2

Using a DMA controller DMA based method useful, when a block of bytes are transferred, for example, from disk to the RAM or RAM to the disk. Repeatedly interrupting the processor for transfer of every byte during bulk transfer of data will waste too much of processor time in context switching
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 3

DMAC
System performance improves by separate processing of the transfers from and to the peripherals (for example, between camera memory and USB port)

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

Interconnections using a DMAC

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

DMAC hold request


After an ISR initiates and programs the DMAC, the DMAC sends a hold request to the CPU CPU acknowledges that if the system memory buses are free to use.

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

Three modes
Single transfer at a time and then release of the hold on the system bus. Burst transfer at a time and then release of the hold on the system bus. A burst may be of a few kB. Bulk transfer and then release of the hold on the system bus after the transfer is completed.
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 7

DMA proceeds without the CPU intervening Except (i) at the start for DMAC programming and initializing and (ii) at the end. Whenever a DMA request by external device is made to the DMAC, the CPU is requested (using interrupt signal) the DMA transfer by DMAC at the start to initiate the DMA and at the end to notify (using interrupt signal) the end of the DMA by DMAC.
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 8

Using a DMA controller


When a DMA controller is used to transfer a block of bytes: ISRs are not called during the transfer of bytes An ISR is called only at the beginning of the transfer to program the controller (DMAC) Another ISR is called only at the end of the transfer

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

Programming the DMAC registers


The ISR that initiates the DMA (Direct Memory Access) to the interrupting source, simply programs the DMA registers for the: command (for mode of transfer bulk or burst or bytes), data-count (number of bytes to be transferred), memory block address where access to data is made and I/O bus for start address of external device
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 10

Use of DMA Channel for Facilitating the Small Interrupt-Latency Period Sources
Small latency periods can be set when using a DMA channel when multiple interrupt from IO sources exist. The ISR run period from start to end can now be very small, [only short code for programming DMAC and for short code on end of DMA transfer for initiating new data transfer or new task.]
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 11

Multiple channels DMAC


Provides DMA action from system memories and two (or more IO) devices. Separate set of registers for programming each channel. Separate interrupt signals in the case of a multi-channel DMAC

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

12

On Chip DMAC in Microcontrollers


8051 family member 83C152JA (and its sister JB, JC and JD microcontrollers) two DMA channels on-chip. 80196KC has a PTS (Peripheral Transactions Server) that supports DMA functions. [Only single and bulk transfer modes are supported, not the burst transfer mode.] MC68340 microcontroller has two DMA channels on chip.
2008 Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 13

Summary

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

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We learnt
DMA controller is a device with single purpose processor and used when multiple bytes are to be transferred between memory and IO devices. Data transfer occurs efficiently between I/O devices and system memory with the least processor intervention using DMAC

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

15

We learnt
DMAC facilitates fast direct byte transfers between memory and I/O devices compared of interrupt driven DMA as it has in-built processing element and uses the system buses as and when they are made available by the processor.

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

16

End of Lesson 12 of Chapter 4

2008

Chapter-4 L12: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education

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