Document Type: Tutorial NI Supported: Yes Publish Date: May 21, 2012

Introduction to Distributed Clock Synchronization and the IEEE 1588 Precision Time Protocol
Table of Contents 1. 2. 3. 4. 5. 6. Distributed Clock Technology Overview IEEE 1588 Synchronization Synchronization Quality Network Topologies IEEE 1588 Application Areas NI Synchronization Products

Distributed Clock Technology Overview Measurement and automation systems involving multiple devices often require accurate timing in order to facilitate event synchronization and data correlation. For example, an industrial automation application may need to synchronize distributed motion controllers, or a test and measurement application may need to correlate data acquired from sensors distributed across a device under test. To achieve this synchronization, devices in the system must either have direct access to timing signals from a common source, or the devices must synchronize their individual clocks in order share a common time base. There are advantages and disadvantages to both methods of device synchronization. In systems where the devices are located nearby each other, typically a few meters, sharing a common timing signal is generally the easiest and most accurate method of synchronization. For example, a set of modular instruments in a PXI chassis all share a common 10 Mhz clock signal from the PXI backplane, enabling event synchronization to less than one nanosecond. To accurately use a common timing signal, a device must be calibrated to account for the signal propagation delay from the timing source to the device. Sharing a common timing signal becomes unfeasible when the distance between devices increase, or when devices frequently change location. Even at moderate distances, 50 meters, a common timing signal may require significant costs for cabling and configuration. In these situations, distributed clock synchronization becomes necessary. Using this approach, devices act on timing signals originating from a local clock which is synchronized to the other clocks in the system. Examples of distributed clock synchronization include devices synchronized to a GPS satellite, a PCs internal clock synchronized to an NTP time server, or a group of devices participating in the IEEE 1588 protocol. Instead of sharing timing signals directly, these devices periodically exchange information and adjust their local timing sources to match each other. The synchronization of distributed clocks requires a continuous process. A clock is essentially a two part device, consisting of a frequency source and an accumulator. In theory, if two clocks were set identically and their frequency sources ran at the exact same rate, they would remain synchronized indefinitely. In practice, however, clocks are set with limited precision, frequency sources run at slightly different rates, and rate of a frequency source changes over time and temperature. Most modern electronic clocks use a crystal oscillator as a frequency source. The frequency of a crystal oscillator varies due to initial manufacturing tolerance, temperature and pressure changes, and aging. Because of these inherent instabilities, distributed clocks must continually be synchronized to match each other in frequency and phase. IEEE 1588 Synchronization

IEEE 1588 provides a standard protocol for synchronizing clocks connected via a multicast capable network, such as Ethernet. Released as a standard in 2002, IEEE 1588 was designed to provide fault tolerant synchronization among heterogeneous networked clocks requiring little network bandwidth overhead, processing power, and administrative setup. IEEE 1588 provides this by defining a protocol known as the precision time protocol, or PTP. A heterogeneous network of clocks is a network containing clocks of varying characteristics, such as the origin of a clocks time source, and the stability of the clock's frequency. The PTP protocol provides a fault tolerant method of synchronizing all participating clocks to the highest quality clock in the network. IEEE 1588 defines a standard set of clock characteristics and defines value ranges for each. By running a distributed algorithm, called the best master clock algorithm (BMC), each clock in the network identifies the highest quality clock; that is the clock with the best set of characteristics. The highest ranking clock is called the grandmaster clock, and synchronizes all other slave clocks. If the grandmaster clock is removed from the network, or if its characteristics change in a way such that it is no longer the best clock, the BMC algorithm provides a way for the participating clocks to automatically determine the current best clock, which becomes the new grandmaster. The best master clock algorithm provides a fault tolerant, and administrative free way of determining the clock used as the time source for the entire network. Slave clocks synchronize to the 1588 grandmaster by using bidirectional multicast communication (see figure below). The grandmaster clock periodically issues a packet called a sync packet containing a timestamp of the time when the packet left the grandmaster clock. The grandmaster may also, optionally, issue a follow up packet containing the timestamp for the sync packet. The use of a separate follow up packet allows the grandmaster to accurately timestamp the sync packet on networks where the departure time of a packet cannot be known accurately beforehand. For example, the collision detection and random back off mechanism of Ethernet communication prevents the exact transmission time of a packet from being known until the packet is completely sent without a collision being detected, at which time it is impossible to alter the packets content.

1/4

www.ni.com

A slave clock receives the grandmasters sync packet and timestamps the packets arrival time using its own clock. The difference in the sync packets departure timestamp and the sync packets arrival timestamp is the combination of the slave clocks offset from the master and the network propagation delay. By adjusting its clock by the offset measured at this point, the offset between the master and slave can be reduced to the network propagation delay only. IEEE 1588 operates under the assumption that the network propagation delay is symmetrical. That is, the delay of a packet sent from the master to the slave is the same as the delay of a packet sent from the slave to the master. By making this assumption, the slave can discover, and compensate for the propagation delay. It accomplishes this by issuing a delay request packet which is time stamped on departure from the slave. The delay request message is received and time stamped by the master clock, and the arrival timestamp is sent back to the slave clock in a delay response packet. The difference in these two timestamps is the network propagation delay. By sending and receiving these synchronization packets, the slave clocks can accurately measure the offset between their local clock and the masters clock. The slaves can then adjust their clocks by this offset to match the time of the master. The IEEE 1588 specification does not include any standard implementation for adjusting a clock; it merely provides a standard protocol for exchanging these messages, allowing devices from different manufacturers, and with different implementations to interoperate. Synchronization Quality

Several factors affect the synchronization levels achievable using IEEE 1588 over Ethernet. During the time between synchronization packets, the individual clocks in a system will drift apart from each other due to frequency changes in their local timing source. This drift can be reduced by using higher stability timing sources and by shortening the intervals between synchronization packets. Temperature-controlled crystal oscillators (TCXOs) and oven-controlled crystal oscillators (OCXOs) provide higher stability than standard crystal oscillators, and atomic clocks provide still higher stability. In addition to stability, a clocks resolution will affect the accuracy of the timestamps transmitted in the PTP synchronization messages. Devices that have a higher resolution clock are able to more accurately timestamp messages. Also, variations in network delay, caused by jitter introduced by intermediate networking devices such as hubs and switches reduce the achievable synchronization level. Ethernet networking enables high bandwidth networks over long distances with relatively cheap cabling and infrastructure costs. Typical Ethernet based IEEE 1588 implementations provide sub-microsecond synchronization, however actual performance is highly implementation and topology specific. The decision regarding the best synchronization scheme to use, shared timing source or synchronized clocks, for a given application involves trade-offs between cost, accuracy, setup complexity, and distance requirements. PXI backplane synchronization is ideal for high-accuracy, high-speed acquisition, and with PXI-6653 modules, can be extended over 200 meters. Standard NTP synchronization over Ethernet offers millisecond level synchronization appropriate for lower-speed events that are not time-critical. IEEE 1588 provides an important alternative for systems requiring sub-microsecond synchronization in geographically distributed systems. Network Topologies

The level of precision achievable using the PTP protocol depends heavily on the jitter (the variation in latency) present in the underlying network topology. Point-to-point connections provide the highest precision. Hubs impose relatively little network jitter. Under very low or no network load, Layer 2 switches have a very low processing time, typically 2 to 10 s plus packet reception time, and have low latency jitter of about 0.4 s. But with network switches, a single queued maximum length packet imposes a delay for the following packet of about 122 s, and under high load conditions, more than one packet can be in the queue. Prioritization of packets, eg: IEEE 802.1p, does not fully solve the problem, as at least one long packet can be in front of a synchronization packet and so will impose up to 122 s to the jitter of transmission. An effective way to reduce the effect of jitter in Ethernet based IEEE 1588 networks is the use of IEEE 1588 boundary clocks or transparent switches (see figure below). A switch acting as a boundary clock runs the PTP protocol, and is synchronized to an attached master clock. The boundary clock in turn acts as a master clock to all attached slaves. With this approach, all internal latencies and jitter in the switch can be compensated and do not affect synchronization accuracy.

2/4

www.ni.com

Boundary clocks do NOT pass Sync, Follow_Up, Delay_Req, or Delay_Resp messages. Within a subnet, a port of a boundary clock acts just like an ordinary clock with respect to synchronization and best master clock algorithm. The boundary clock internally selects the port that sees the best clock as the single slave port. This port is a slave in the selected subnet. All other ports of the boundary clock internally synchronize to this slave port. Boundary clocks define a parent-child hierarchy of master-slave clocks. The best clock in the system is the Grand Master clock. If there are cyclic paths in the network topology the best master clock algorithm reduces the logical topology to an acyclic graph. Transparent switches solve the same problem as boundary clocks in a slightly different manner. A transparent switch is so called because it does not operate as a PTP node in a IEEE 1588 system. Instead, a transparent switch modifies the timing contents of PTP packets to account for the delay caused by the switch. Typically, a transparent switch calculates how much time a 'sync' packet spends inside the switch, and then modifies the timestamp of the associated 'follow up' packet to account for this delay. The use of transparent switches allows the PTP nodes to operate as if they were all part of one big LAN segment connected by hubs. IEEE 1588 Application Areas

The precise synchronization capabilities of PTP is leading to interest in its use for many different kinds of applications: Test & Measurement Factory Automation Power Plants Telecommunications Robotic Control

National Instruments IEEE 1588 products allows you to perform synchronized distributed measurement and automation: Read the current 1588 time Create future time events Time stamp triggers and pulse trains Create synchronized clocks NI Synchronization Products

NI-Sync NI-Sync is a library of VIs and functions for controlling NI PXI-665x and NI PCI-1588 timing modules. Using NI-Sync, you can configure all aspects of timing and synchronization for NI PXI-665x devices, including sharing trigger signals and clocks in one or more chassis. In addition, you can configure all aspects for NI PCI-1588 devices, including IEEE 1588 synchronization, trigger time stamping, and generation of synchronized signals. You can use NI-Sync in conjunction with other measurement software, such as NI-DAQmx, to create advanced high-channel-count measurements that span multiple PXI chassis or an Ethernet network. NI PCI-1588 - IEEE 1588 Precision Time Protocol Synchronization Interface The National Instruments PCI-1588 enables you to use IEEE 1588 to perform synchronized events over Ethernet. The NI PCI-1588 can generate events and clock signals at specified 1588 future times and timestamp input events with the 1588 system time. It has three general-purpose PFI lines for synchronizing non-1588 devices such as traditional instruments or PLCs via SMB connectors on the PCI bracket and a RTSI interface for synchronizing other PCI instruments in the same PC. The NI PCI-1588 provides a method for performing synchronous activity and analysis over low-cost Ethernet cabling.

NI PXI-6682 - GPS, IEEE 1588 and IRIG-B Timing and Synchronization for PXI The National Instruments PXI-6682 timing and synchronization module synchronizes PXI systems using GPS, IEEE 1588, and IRIG-B to perform synchronized events. The NI PXI-6682 can generate events and clock signals at specified synchronized future times and timestamp input events with the synchronized system time. You also can use the PXI-6682 to route clock signals and triggers with low skew within a PXI chassis or between multiple chassis, providing you a method for synchronizing multiple devices in a PXI system. To configure a complete PXI system using the PXI-6682, ni.com/pxiadvisor.

Related Links: Special Focus: Understanding the IEEE 1588 Precision Time Protocol NI PCI-1588 Precision Time Protocol Interface

3/4

www.ni.com

Incorporating LXI USB and Other Standards into a Hybrid Test System Device Selection in a Hybrid System

Legal This tutorial (this "tutorial") was developed by National Instruments ("NI"). Although technical support of this tutorial may be made available by National Instruments, the content in this tutorial may not be completely tested and verified, and NI does not guarantee its quality in any way or that NI will continue to support this content with each new revision of related products and drivers. THIS TUTORIAL IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND AND SUBJECT TO CERTAIN RESTRICTIONS AS MORE SPECIFICALLY SET FORTH IN NI.COM'S TERMS OF USE ( http://ni.com/legal/termsofuse/unitedstates/us/).

4/4

www.ni.com