Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

DESIGN AND ANALYSIS OF LOW POWER BANDGAP VOLTAGE REFERENCE CIRCUIT Tham Nyap Tet Clement1*, Ismail Saad1, Norfarariyanti Parimon 1
1

Nano Engineering and Materials (NEMs) Research Group, School of Engineering and Information Technology, Universiti Malaysia Sabah, Jalan UMS, 88400 Kota Kinabalu, Sabah.

ABSTRACT. In this paper, a low voltage bandgap voltage reference circuit is proposed, simulated and analysed. The Bandgap Voltage Reference (BGR) circuit is one of the many voltage references in the technological world and has been a well-known term used to identify a circuit that produces a constant low voltage around 1.22 V which is close to the bandgap energy of silicon at 1.22 eV. The BGR circuit proposed has a stable output at 1.22V ranging from -40 C to +125 C of temperature variations with less than 2.1592 mV or 10.90 ppm/K. The design includes a start-up circuit and a differential amplifier and the bandgap core circuit. The differential amplifier with 65 dB was successfully designed using a two stage amplification and the startup circuit was also successfully designed specifically for the BGR core. Using Silvaco Electronic Design Automation (S.EDA), the circuit is designed and tested. The design is done using 0.18 m technology process file from Silterra Sdn. Bhd. KEYWORDS: Bandgap Voltage Reference; analog IC; low-voltage; 0.18 m CMOS technology. INTRODUCTION Voltage reference is an electronic device used to produce a constant current irrespective of operating temperature, power supply and load variation, as well as through the passage of time. The Bandgap Voltage Reference (BGR) has been a well-known term used to identify a circuit that produces a constant low voltage around 1.22 V close to the bandgap energy of silicon at 1.22 eV. This circuit was first introduced by Widlar (1971), using conventional junction-isolated bipolar-IC technology to make a stable low-voltage, 1.220 V reference (Widlar, 1971). This type of circuitry became popular as voltage reference for low voltage circuits, especially in 5 V data acquisition systems where zener diodes are not suitable (Pease, 1990). The general concept of BGR circuit revolves around the existing temperature co-efficient (TC) between the pn junctions of a transistor. This is shown from the base-emitter voltage VBE of a diode and a Bipolar Junction Transistor (BJT) where the VBE generated from a pn-junction diode is dependent on temperature inverse proportionally also known as complementary-toabsolute-temperature (CTAT) and its approximated as 2 mV/K at room temperature (Allen, 2002). At the same time, another thermal coefficient is generated, VBE, from the difference in current density operation of 2 bipolar transistors or diodes. This VBE is directly proportional-toabsolute-temperature (PTAT) (Razavi, 2001). Leung et. al. (2003) manage to implement a CMOS BGR in a standard 0.6 m technology and obtained results of 1.14205 V 2.85 mV. David (2011) implemented a sub-1 V BGR of 235 mV but a TC of 34 ppm/degC.
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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

The main objective of this paper is to develop a stable voltage reference circuit for use in Integrated Circuit (IC) by designing BGR for stable voltage output around 1.20 V with variation of < 5 mV for a temperature range of -40 C < T < + 125 C using 0.18 m semiconductor fabrication technology. METHODS AND PROPOSED CIRCUIT Proposed BGR circuit The full proposed circuit is represented in Figure 9 in which, it contains 3 main individual components BGR core, start-up circuit and differential amplifier. This could be further simplified by representing using block diagrams such as Figure 10.

Figure 9: Full circuit of the proposed BGR

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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

Figure 10: Block diagrams representation of the proposed BGR circuit Analyzing the circuit, the BGR core, X1 in Figure 10, supplies 2 voltages, VBE1 and VBE2 which both exhibits a negative. However, VBE1 and VBE2 both exhibits a different TC by varying transistor M2, M4, M6, M16 and resistor R6 for transistor Q1 while, Q2 is affected by transistor M1, M3, M5, M15 and Resistor R5 from Figure 9. The difference in TC is fed into the Differential Amplifier, X2, and the PTAT voltage is generated. This PTAT voltage has a positive TC which will be fed back in to transistors of the BGR core circuit. This in turn acts as a close loop and will produce a constant current at VREF. The startup circuit is in place because during start-up of the circuit, it may end up in one of 2 different zones the dead (zero) zone and normal operating zone. To prevent the voltage reference ending up in the dead zone, the start-up circuit is introduced. Hence the start-up circuit here will introduce an initial voltage to the differential amplifier, in case that the circuit might end up in the dead zone. Else, the start-up circuit will remain in the cut-off zone where ideally, there will not be any current consumption. RESULTS AND DISCUSSION In Figure 11(a) there is almost no visible change in reference voltage, VREF, from -40 C to +125 C. However, when the y axis scale is zoomed as shown in Figure 11(b), there is noticeable slope which upon further investigation, the change is at 2.1592 mV across the whole range of temperature test. This proves the theory of CTAT and PTAT voltages could negate each other off if tuned correctly, providing an almost constant voltage reference with little dependence on temperature variations.

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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

(a)

(b)

Figure 11: Voltage output across the VREF of the proposed circuit (a) The VREF output from the proposed circuit (b) A zoom in graph of the VREF output from the proposed circuit.

(a)

(b)

Figure 12: Simulation results for current consumption and operational voltage (a) Current consumption of the circuit (b) Operational voltage range of the BRR circuit From the Figure 12(a), the current consumption is fairly high which is 624 A at 27 degC. Besides having very little dependence on temperature, any BGR circuit should be exhibit input voltage tolerance as well. As can be seen on Figure 12 (b), the proposed BGR circuit has been tested for input voltage variation, VDD, as well. The simulation shows that the circuit has a high voltage operation range of 2 V to 5.5 V with little variations of only 2.7565 mV.

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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

Table 2: Overall simulation results

No. 1 2 3 4 5 Parameter Supply Voltage Reference voltage Reference voltage variation Temperature Op-amp gain Minimum 2.7 1.80 N/A -40 N/A Typical @ 27 C 3 1.20 5 27 60 Maximum 3.3 1.25 N/A 125 N/A Proposed Results 3 1.2007 2.1592 -40 < T < 125 65.059 PASS / FAIL PASS PASS PASS PASS PASS Unit V V mV C dB

The simulation results are tabulated into Table 2 for easy reference. From Table 2, it can be seen that the specified supply voltage is between 2.7 V to 3.3 V, however, in this design, the supply voltage is actually larger, from 2.0 V to 5.5 V while maintaining the operation within the acceptable VREF variation. The temperature range tested is equal to the specific range and the output voltage, VREF, is at 1.2007 V while having a variation of 2.1592 mV throughout the range of temperature and supply voltage. The power consumption, on the other hand is at 1872 W is still in the acceptable range and could be further improved in future research. Table 3: Process corner testing with 2 different configurations
Trace 1 2 3 4 5 6 R5 (k) 150 150 150 800 800 800 R6 (k) 85465 85465 85465 413.5 413.5 413.5 Process Corner TT FF SS TT FF SS Minimum (V) 1.1985 1.1847 1.2099 1.2000 1.1873 1.2074 Maximum (V) 1.2007 1.1870 1.2112 1.2019 1.19067 1.21176 Peak-to-Peak (mV) 2.1592 2.3060 1.3198 1.9100 3.3371 4.2747 Pass / Fail Pass Pass Pass Pass Pass Pass

*TT Typical NMOS, typical PMOS FF Fast NMOS, fast PMOS SS Slow NMOS, slow NMOS From the Table 3, it can be seen that all the process corner manage to keep to a voltage variation (Peak-to-Peak) of less than 5 mV. The only noticeable difference is when going across process corners where there is a bigger difference in average voltage.

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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

Table 4: Comparison of the proposed BGR against existing designs

Project Proposed Circuit T. L. Brooks et. al. (1994) C. W. David et. al (2011) Y. T. Lin et. al. (2005) K. N. Leung (2001) Jiang et. al. (2000) Kevin Tom et. al. (2005) K. N. Leung (2003) Huang W. W. et. al. (2011) David et. al. (2011) Reference Voltage ( Vref ) 1.2007 Temperature Range ( C ) - 40 < T < 125 Voltage Variation ( mV ) 2.1592 Technology ( m ) 0.18 Temperature Coefficient ( ppm/C ) 10.90

2.005

N/A

5.5

0.65

115

0.700

-20 < T < 120

N/A

0.50

34

0.612

-20 < T < 100

N/A

0.35

20

0.603

0 < T < 100

N/A

0.6

15

1.20

0 < T < 100

N/A

1.2

100

0.703

0 < T < 60

N/A

0.18

1.14205

N/A

2.85

0.60

5.3 < TC < 2.6

1.2558

-40 < T < 140

0.60

26.5

0.235

-40 < T < 120

N/A

0.50

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Summarized in Table 4 is the comparison between the proposed BGR with some of the work of other researches. The proposed BGR gave a better TC than most of the researchers while being able to scale down the design to 0.18 m. The only design that was able to keep a lower TC is Kevin Tom et. al. (2005) and K. N. Leung (2003)

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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

Table 5 Comparison with commercially available products

Project/ Commercial Proposed Circuit Analog Devices ADR430A Analog Devices ADR435A Linear Technology LT6654 On Semiconductor REF3012 On Semiconductor LM285 Reference Voltage ( V ) 1.2007 2.048 5.000 1.25 1.25 1.235 Temperature Range ( C ) - 40 < T < 125 27 < T < 85 27 < T < 85 -40 < T < 125 -40 < T < 85 0 < T < 100 Voltage Variation ( mV ) 2.1592 3 6 N/A N/A 20 Temperature Coefficient, TC ( ppm/C ) 10.90 10 10 Grade A - 10 Grade B - 20 20 < TC < 50 80

Table 5 shows the comparison between the proposed circuit with commercially available products. As seen in Table 5, both Analog Devices and Linear Technology are able to keep to the 10 ppm/degC range. However, their products are of high reference voltage, thus, will lead to higher power consumption. CONCLUSION A low voltage bandgap voltage reference circuit has been designed and tested on a 0.18 m technology using by EDA simulation tools. The circuits operated with an output of 1.20 V average with temperature range from - 40 degC to + 125 degC with TC of 10.90 ppm/degC equivalent to 2.1592 mV voltage variations. The circuit can operate with a supply from as low as 2 V up to 6 V while maintaining within its allowed voltage variations with a power drain of 1.8 mW. The rather high power drain may be attributed to the technology that was used is meant for high performance power management applications, and the operational amplifier which consumes more power, hence the higher power consumption. ACKNOWLEDGEMENTS The author is thankful to Universiti Malaysia Sabah (UMS) for providing excellent research environment and facilities in which this work is completed using. Besides that, the author would like to acknowledge the support from SilTerra Malaysia Sdn. Bhd. for providing the technology file used to complete this research. REFERENCES Behzad Razavi. 2001. Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill International Edition. David C. W. Ng, David K. K. Kwong, and Ngai Wong. 2011. A Sub-1 V, 26 W, Low-OutputImpedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode.
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Proceeding of the 10th Seminar of Science & Technology 1-2 December 2012, Kota Kinabalu Sabah

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 19(7): 1305 - 1309 Huang W. W., Yang X., Ling C. D,. 2011. A Bandgap Voltage Reference Design for High Power Supply. Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference. 184 - 187 Jiang, Y and Lee, E. K. F. 2000. Design of low-voltage bandgap reference using transimpedance amplifier. IEEE Trans. Circuits Syst. II. 47(6): 552555. Kevin Tom and Atila Alvandpour. 2005. Curvature Compensated CMOS Bandgap with Sub 1V Supply. Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA06). Leung, K. N. and Mok, K. T, 2001. Analysis of multistage amplifier-frequency compensation. IEEE Trans. Circuits Syst. I. 48(9): pp. 10411056. Leung, K. N. and Mok, K. T. 2002. A sub-1-V 15-ppm/C CMOS bandgap reference without requiring low threshold voltage device. IEEE J. Solid-State Circuits. 37(4): 526529. Lin Y. T., Chung W. Y., Wu D. S., Lin H.C., and Lin Robert. A Low Voltage CMOS Bandgap Reference. 2005. The 3rd International IEEE-NEWCAS Conference. pp. 227 - 230 Pease, R. A. 1990. The design of band-gap reference circuits: Trials and tribulations. Proc. IEEE 1990: Bipolar Circuits Technology Meeting. 214218. Phillip E. Allen & Douglas R. Holberg. 2002. CMOS Analog Circuit design 2nd Ed. Oxford: Oxford University Press. Todd L. Brooks and Alan L. Westwick, "A Low-Power Diferential CMOS Band Gap Reference," 1994 IEEE International Solid State Circuits Conference, pp. 248, 249 Tom K. and Alvandpour A. 2005. Curvature Compensated CMOS Bandgap with Sub 1V Supply. Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA06). 4-8 Widlar, R. 1971. LM113 data sheet. National Semiconductor Linear Data Book. Santa Clara: National Semiconductor Corporation.

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