Ch7 VIRTUAL MEMORY

VIRTUAL MEMORY (sec. 7.4) An advanced memory system supports a number of needs: 1) Protection of other programs from interference 2) Relocation - allowing a program to use any physical page locations 3) Paging allowing the sum of all programs memory locations to be greater than physical main memory by using the hard disk as overflow Virtual memory using main memory as a cache for the hard disk drive. Thus, main memory need only contain the active portions of each programs memory locations (program and data). Before considering how VM works, lets look at an example MS windows 95 CPUs (virtual) address space. FFFFFFFF (32 bit address) Top 2 Gigabytes O.S., drivers, system DLLs

Custom DLLs Bottom 2 Gigabytes executable program heap initialized vars stack executable 00000000 MS Windows CPU address space note that Win95 allows program to access OS data structures in top 2 GB, whereas NT does not. Thats one reason why 95 crashes not infrequently. This is a huge address space, and only bits here and there are used. DLLs are often compiled to work only at specific addresses, so they have to be
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mapped to those addresses. Since DLLs may be shared between programs (or program instances), there must be a way to map a DLL in main memory to the program spaces of two or more programs. Likewise, data may in some cases be shared between programs (especially on servers). How is this mapping achieved? By dividing main memory into PAGES (or blocks), and mapping page addresses from the CPUs VIRTUAL PAGE ADDRESS to main memorys PHYSICAL PAGE ADDRESS. This can be done with a lookup table. Consider Windows again. The page size is 4 Kbytes. Thus, the virtual address consists of: Page address (31-12) Page offset (11-0)

Note that 20 bits serve to select one of the 1M pages that make up the 4 GB address map. Whats the problem here? We need a 1M element lookup table to do the translation, and each element requires 3-4 bytes! The full PAGE TABLE usually is resident on the hard drive, since it would be wasteful to put one such table in main memory for each program, and much less possible to put it on the CPU chip (as is needed for reasonably fast access). To do a memory access, one might have to first access the hard drive to read the page translation from the page table, then do the actual access from main memory (ignoring caches for the time being). But hard disk accesses take so long that the program is suspended while the access occurs.

3112 11 -0 virtual address

PAGE TABLE (4Mbyte?)

A12-29 MAIN MEMORY A 11-0 physical address

So this is much more complex than it first appears. To find out what actually happens, we first need to consider paging in more depth. PAGING BASICS The page table has a number of flag bits associated with each virtual page address. One of these, the VALID BIT, specifies whether the page is located in the main memory. If a memory access occurs to a page with the valid bit reset, a PAGE FAULT exception occurs, and the OS suspends the program and arranges to have the page transferred from hard disk to main memory. Then the program is restarted at the memory access instruction. NOTE that when a program starts up, the OS usually creates the page table on disk and resets all valid bits. This ensures that page faults will occur as a program starts up, and explains the long startup time for some programs (the OS has to set up the page table, then the first executable pages must be loaded, then any accessed DLLs, etc). When the OS runs out of memory (more correctly, available memory falls below a specified threshold), the OS will find a page that was not accessed recently, and will free it by resetting the valid bit of the owner programs page table. If the page was modified by the program (a DIRTY BIT in the page map was set), the OS first has to save the page to disk, to a special SWAP FILE. A Least Recently Used (LRU) algorithm must be implemented to estimate which pages have not been accessed recently. This is often done with a USE BIT or REFERENCE bit that is set by hardware whenever a page is accessed. The OS will periodically reset all the bits, so that after a while the pages that have not been accessed during the window will still have the bit reset. Page faults are usually handled in software since the overhead will be small compared to the access time for the disk. Furthermore, software can use clever algorithms for choosing how to place pages because even small reductions in the miss rate will pay for the cost of such algorithms.

VM SYSTEM BASICS A page table is used since in a fully associative system, you can have many locations what you are looking for can reside. A page table negates the need for a full search since you have indexed where everything is. A page table is indexed with the page number from the virtual address and contains the corresponding physical page number. Remember, each program will have its own page table. Using figure 7.22 with this system of 4 KB page sizes, we see we have our 4 GB of virtual address space and 1 GB of RAM. The number of entries in the page table then is 220 or 1 million entries. Since the page table may be too large to fit into main memory, the page table may itself be paged! To explain this, lets look at the last missing piece: To avoid TWO memory accesses each time that address translation happens, most CPU chips implement a page map cache, called a TRANSLATION LOOKASIDE BUFFER (TLB). The TLB caches the most recent page table entries. TLBs are usually small (4k entries or less), and may be fully associative (small ones) or set associative (larger ones). TLBs are reasonably fast. CPU TLB MainMem HDD

Lets consider what happens for a main memory access L/S. First, the TLB is accessed. If there is a TLB HIT, the physical address is accessed, and the valid bit. If valid is high, the main memory block transfer can be completed using the physical address. If the valid bit is reset, a page fault exception is generated. If there is a TLB MISS, things get complicated. First, the TLB entry must be loaded. We must first find out if the miss is just a TLB miss or if the page is out of main memory. If it is just a TLB miss, then the TLB is

updated. If it is a main memory miss, main gets loaded as does the TLB. If the page table is small, it can be locked into main memory, and the desired information is always available as a main memory access. If the page table is large, it will not fit into main memory, and might be accessed from disk only. BIG TLB miss penalty! If the page table itself gets paged, the TLB lines that access the page map may be preloaded and locked in place, so the system knows where to look for the page table (and whether the page table page is swapped out). Once the TLB line is loaded, processing proceeds as in the TLB hit case. See Fig 7.24 (TLB) and 7.25 (Virtual Mem, TLB and Caches all together). 7.26 is a flow chart of 7.25. Virtual vs Physical caches An important question is where the TLB is placed with regard to the Level 1 cache. If the TLB is AFTER the Level 1 cache, the Level 1 cache is a VIRTUALLY ADDRESSED cache, else it is a PHYSICALLY ADDRESSED cache. The main advantage of a virtually addressed cache is faster memory accesses when info is in cache, because there is no slowdown by TLB access. The main advantage of a physically addressed cache is that contents reflect the physical memory, and thus the cache does not need to be flushed for a process swap, as may be required in the case of the virtual cache. However, some systems also include some bits in each line that identify the process number of the process that owns the line, leading to a miss if the process numbers do not match. Protection Protection mechanisms are easily built onto this virtual memory framework. Most systems have separate user/supervisor (or system or kernel) modes. Usually protections are relaxed in the system mode, which is invoked when

the OS is running (exceptions/interrupts automatically switch mode to system, returning usually switches mode back to user). The page table/TLB usually have bits that limit access to read_only, read/ write or write_only. Its trivial for the hardware to generate an exception (often a type of page fault exception) when permissions are violated. Thus, shared DLLs and executables are read-only, while a processs data is R/W. Some systems have additional branch-and-bound registers that specify which areas of memory can be accessed. This is useful because it is finergrained than page-level accesses. Page tables themselves are usually part of the OS, and not modifiable by user code. Otherwise, user could change mapping to access other processs pages! Final Note What happens if a cache or TLB location exists while its page is swapped out by the OS? This can cause serious problems, especially in the cache case. If a cache line is dirty, for example, and is about to be replaced, it needs to be written to main memory. But if the page is not there, wed need a page fault, and so wed need to be able to recreate the state of the cache afterwards, or write the cache line to disk. To avoid such unpleasantness (and much hardware), the OS goes to the trouble of accessing the caches and invalidating lines associated with the page about to be removed (first writing back if the dirty bit is set). Problems: 1) A memory like 7.25 contains cache and a TLB. A memory reference can encounter three different types of misses: cache miss, TLB miss and a page fault. Consider all the combinations of these three events with one or more faults occurring. For each possibility, state whether this can occur and when. CACHE Miss Miss Miss TLB Miss Miss Hit VIRT MEM Miss Hit Miss
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POSSIBLE? yes, really old stuff yes, old stuff Impossible

Miss hits Hit page Hit Hit

Hit Miss Miss Hit

Hit Miss Hit Miss

yes, but page not checked if TLB Impossible, data not allowed in cache if not in memory yes Impossible

2) (7.32) Consider a virtual memory system with the following properties: 40 bit virtual byte address 16 KB pages 36 bit physical byte address What is the total size of the page table for each process on this machine, assuming that the valid, protection, dirty and use bits take 1 bit each and that all virtual pages are in use? Solution There are 40 bits minus 2x bits (from page offset) used for virtual addresses. This means there are 40 14 = 26 bits. So we have 226 pages or 64M (67, 108, 864) entries. Since each line would have 36 14 or 22 bits + the 4 from the valid, protection, dirty and use bits, we would use up: 64MB * 26 bits or 1,744,830,464 bits. If you use full 32 bit registers as an entry, the total space would be 2, 147, 483, 648 bits or 2 GB.