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The 8085 Chip: Ee309: Computer Organization, Architecture and Microprocessors

The document provides information about the 8085 microprocessor architecture. It describes the various signals and pins of the 8085 chip, including address/data buses, control signals, flags, and interrupts. It then summarizes the instruction set of the 8085, grouping the instructions into categories like data transfer, arithmetic, logical, branch, and stack/I/O instructions. For each instruction category, it provides brief descriptions of the individual instructions and notes which CPU flags they affect.

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Shashank Dubey
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205 views8 pages

The 8085 Chip: Ee309: Computer Organization, Architecture and Microprocessors

The document provides information about the 8085 microprocessor architecture. It describes the various signals and pins of the 8085 chip, including address/data buses, control signals, flags, and interrupts. It then summarizes the instruction set of the 8085, grouping the instructions into categories like data transfer, arithmetic, logical, branch, and stack/I/O instructions. For each instruction category, it provides brief descriptions of the individual instructions and notes which CPU flags they affect.

Uploaded by

Shashank Dubey
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CAMP:8085 Primer-1

EE309: Computer Organization, Architecture and MicroProcessors


http://www.ee.iitb.ac.in/sumantra/courses/up/up.html

The 8085 Chip


POWER & FREQ SIGNALS

F LAGS : S Z x A x P x cy ALE : Address Latch Enable: Positivegoing pulse at the start of a machine cycle (each 8085 operation), indicates AD7 - AD0 are A7 - A0 .
HIGH ORDER ADDRESS BUS MULTIPLEXED ADDRESS/DATA BUS

EXTERNALLY INITIATED SIGNALS EXTERNAL SIGNAL ACK SERIAL I/O

X1 X2 SID SOD A B D H W

VCC

TRAP RST7.5 RST6.5 RST5.5 INTR READY HOLD RESET IN

GND A FLAGS 15 C A8 E L SP A7 PC A0 Z

External devices or signals can initiate the following four operations: 1. Reset: RESET IN , RESET OU T Resets the 8085 PC 0 2. Ready: The 8085 waits for an integral number of cycles till this goes high. It waits to sync with slow peripherals 3. Hold: HOLD, HLDA (DMA). The 8085 relinquishes the control of buses, allows external peripherals to use them

CONTROL & STATUS SIGNALS

INTA HLDA

ALE S0 S1 IO/M RD WR

RESET OUT CLK OUT

4. Interrupt: (a) T RAP : Non-maskable interrupt, highest priority

(b) RST 7.5, RST 6.5, RST 5.5: Vectored restart interrupts (transfer program control to specic memory locations). Order of priority: 7.5 > 6.5 > 5.5 (c) IN T R: Software interrupt, general purpose (d) IN T A: Interrupt Acknowledge Machine Cycle Opcode Fetch Memory Read Memory Write I/O Read I/O Write Interurpt Ack Halt Hold Reset (Status) IO/M S1 S0 0 0 0 1 1 1 Z Z Z 1 1 0 1 0 1 0 X X 1 0 1 0 1 1 0 X X Control Signals RD = 0 RD = 0 WR = 0 RD = 0 WR = 0 IN T A = 0 RD = Z , W R = Z, IN T A = 1

Sumantra Dutta Roy, EE, IITB

[email protected]

CAMP:8085 Primer-2

The 8085 Instruction Set: Programmers View


1. 2. 3. 4. 5. Data Transfer Group Arithmetic Group Logical Group Branch Group Stack, I/O and Machine Control Instructions 1. Data Transfer Group MOV, MVI, LXI, LDA, STA, LHLD, SHLD, LDAX, STAX, XCHG 2. Arithmetic Group ADD, ADI, ADC, ACI, INR, INX, DAD, DAA SUB, SUI, SBB, SBI, DEC, DCX 3. Logical Group ANA, ORA, XRA, CMP, RLC, RAL, CMA, STC ANI, ORI, XRI, CPI, RRC, RAR, CMC 4. Branch Group JMP, JC, JZ, JNC, JNZ, RST, JP, JPE, JM, JPO, CALL, RET, CC, CNC, RC, RNC, CP, CM, RP, RM, CPE, CZ CPO, CNZ RPE, RZ RPO, RNZ

PCHL,

5. Stack, I/O and Machine Control Instructions PUSH, XTHL, IN, EI, POP, SPHL, OUT, DI, HLT, NOP, SIM, RIM, LXI SP, INX SP, DCX SP DAD SP

Sumantra Dutta Roy, EE, IITB

[email protected]

CAMP:8085 Primer-3

1. Data Transfer Group [No Flags Aected]


1. MOV r1 , r2 r1 r2 2. MOV r, M r (HL) The contents of the memory location stored in the HL pair are copied to register r 3. MOV M, r (HL) r 4. MVI r, 8-bit data r byte 2 5. MVI M, 8-bit data (HL) byte 2 Transfer the byte to the memory location given by the contents of the HL pair 6. LXI rp, 16-bit data rh byte 3 rl byte 2 LXI B, LXI D, LXI H load two bytes into the register pairs BC, DE and HL, respectively. The 8085 convention: the lower-byte of a 2-byte pair is stored rst in memory 7. LDA 16-bit address A (byte 3 byte 2) 8. STA 16-bit address (byte 3 byte 2) A 9. LHLD 16-bit address L (byte 3 byte 2) H (byte 3 byte 2 + 1) 10. SHLD 16-bit address (byte 3 byte 2) L (byte 3 byte 2 + 1) H 11. LDAX rp A (rp), i.e., A (rh rl) The Accumulator is loaded with the contents of the address (2-byte value) stored in the register pair. NOTE: This is not valid for the HL pair ! 12. STAX rp (rp) A, 13. XCHG H D LE i.e., (rh rl) A

Sumantra Dutta Roy, EE, IITB

[email protected]

CAMP:8085 Primer-4

2. Arithmetic Group
[All Flags Aected:] 1. ADD r A A+r NOTE: ADD A is a valid instruction ! 2. ADD M A A + (HL) 3. ADI 8-bit data A A + byte 2 4. ADC r A A + r + cy 5. ADC M A A + (HL) + cy 6. ACI 8-bit data A A + byte 2 + cy 7. SUB r A Ar If the result is negative, the Carry / Borrow ag cy is set. The Carry ag is the Borrow ag. However, the Auxiliary Carry ag does not double up as an Auxiliary Borrow ! 8. SUB M A A (HL) 9. SUI 8-bit data A A byte 2 10. SBB r A A {r + cy } 11. SBB M A A {(HL) + cy } 12. SBI 8-bit data A A {byte 2 + cy } 13. DAA This adjusts the accumulator to packed BCD after the addition of two BCDs. It functions in two steps: (a) If the lower 4 bits of A are greater than 9, or the Auxiliary Carry ag is set, then it adds 6 to the lower nibble of A (b) Subsequently, if the higher 4 bits of A are now greater than 9, or the Carry Flag is set, it adds 6 to the higher nibble of A [Only cy Flag Aected:] 14. DAD rp HL HL + rp
Sumantra Dutta Roy, EE, IITB [email protected]

CAMP:8085 Primer-5 [Flags Aected: ZAP S , no cy !] 15. INR r r r+1 16. INR M (HL) (HL) + 1 17. DCR r r r1 18. DCR M (HL) (HL) 1 [No Flags Aected:] 19. INX rp rp rp + 1 20. DCX rp rp rp 1 i.e., rh rl rh rl + 1 i.e., rh rl rh rl 1

Addition and Subtraction + DAA All Flags ! INR + DCR no cy ! DAD only cy ! INX + DCX no ags !

3. Logical Group
1. ANA r A Ar 2. ANA M A A (HL) 3. ANI 8-bit data A A byte 2 4. ORA r A Ar 5. ORA M A A (HL) 6. ORI 8-bit data A A byte 2 7. XRA r A Ar 8. XRA M A A (HL) 9. XRI 8-bit data A A byte 2
Sumantra Dutta Roy, EE, IITB [email protected]

CAMP:8085 Primer-6 10. CMP r A r, without performing the actual subtraction. This just sets the ags. 11. CMP M 12. CPI 8-bit data 13. RLC Rotate left without Carry ! 14. RAL Rotate Accumulator left through Carry 15. RRC Rotate right without Carry ! 16. RAR Rotate Accumulator right through Carry 17. CMA Complement contents of the Accumulator 18. STC Set the Carry ag 19. CMC Complement the Carry ag AND, OR, XOR cyZP S aected in all, cy reset(0) AND Auxiliary Carry is set(1) any OR (inclusive / exclusive) Auxiliary Carry is reset(0) Comparison All ags Rotation only cy ! CMA No ags ! STC, CMC only cy !

4. Branch Group [No Flags aected !]


1. 2. 3. 4. 5. 6. 7. 8. 9. JMP 16-bit address JC 16-bit address JNC 16-bit address JZ 16-bit address JNZ 16-bit address JP 16-bit address JM 16-bit address JPE 16-bit address JPO 16-bit address 10. 11. 12. 13. 14. 15. 16. 17. 18. CALL 16-bit address CC 16-bit address CNC 16-bit address CZ 16-bit address CNZ 16-bit address CP 16-bit address CM 16-bit address CPE 16-bit address CPO 16-bit address 19. 20. 21. 22. 23. 24. 25. 26. 27. RET 16-bit address RC 16-bit address RNC 16-bit address RZ 16-bit address RNZ 16-bit address RP 16-bit address RM 16-bit address RPE 16-bit address RPO 16-bit address

28. RST n 0 n 7. Restart control is transferred to address n 8. 29. PCHL P Ch H P Cl L


Sumantra Dutta Roy, EE, IITB [email protected]

CAMP:8085 Primer-7

5. Stack, I/O and Machine Control Instructions


[No Flags aected unless explicitly mentioned] 1. PUSH rp Push the register pair contents onto the stack, with the higher-order byte pushed rst 2. POP rp The low and then the high byte are popped from the stack onto the register pair 3. PUSH PSW The Program Status Word comprises the Accumulator (higher-order byte), and the Flags register (lower-order byte) 4. POP PSW [All Flags aected !] 5. XTHL L top of stack H next in line The contents of the HL pair are exchanged with the top of the stack (the lower-order byte is always on top). The contents of SP are not aected 6. SPHL SP h H SP l L The contents of the HL pair are copied onto the Stack Pointer register 7. IN 1-byte port address The port address is duplicated on both the higher-order (A15 A8 ) and lower-order (AD7 AD0 ) address bus 8. OUT 1-byte port address 9. EI The Interrupt Enable Flip Flop is set. and all intrrupts are enabled (the TRAP interrupt is always enabled) 10. DI The Interrupt Enable Flip Flop is reset, and all interrupts are disabled (except the TRAP interrupt, which cannot be disabled 11. HLT Halt and enter Wait State, till an interrupt, or reset 12. NOP No Operation, used to insert precise time delays 13. LXI SP 16-bit address 14. INX SP 15. DCX SP

Sumantra Dutta Roy, EE, IITB

[email protected]

CAMP:8085 Primer-8 16. DAD SP [Only cy Flag aected] HL HL + SP 17. SIM Set Interrupt Mask A suitable bit pattern is loaded into the Accumulator, and then this instruction is to be called. The bit pattern is interpretated as follows: If SDE = 1 only (Serial Data Enable), then whatever is in the SOD SDE R7.5 MSE M7.5 M6.5 M5.5

SOD (Serial Output Data) - 0/1 is latched onto the SOD output line on the 8085. R7.5 is an additional control to reset the RST7.5 ip op. If MSE = 1 only (Mask Set Enable), Mn is masked or disabled if Mn = 1, enabled if Mn = 0. Ths command is also used for serial output. 18. RIM Read Interrupt Mask This command is used to read the status of interrupts 7.5, 6.5 and 5.5, and serial data input. The result of executing this command is a number being loaded into the Accumulator, whose interpretation is as follows: SID represents the serial input bit. SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

In = 1 interrupt n is pending. IE = 1 the Interrupt Enable ip op is set. Mn the corresponding interrupt is masked out.

Notes
All are equal, but some are more equal than others. . George Orwell, Animal Farm. HOLD has a higher priority than any interrupt. LDAX is not meant for the HL register pair. DAD, HLT have a special Bus Idle Machine cycle. The following instructions have a special 6 T-state Opcode Fetch machine cycle: INX, DCX, PCHL, SPHL, PUSH, RST, and All CALL and RETURN instructions (except RET)

Sumantra Dutta Roy, EE, IITB

[email protected]

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