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Lab Sheet 4

The document provides instructions for building a single-cycle MIPS processor in Verilog. It lists the necessary datapath components including a 32-bit ALU, register file, instruction memory, and data memory. It describes resetting the datapath using an active-low reset signal and initializing the instruction memory and data memory. Students are tasked with writing diagnostic programs to test the processor implementation and developing a Verilog controller to generate control signals for the datapath. Component propagation delays must also be modeled in the Verilog code.

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151 views

Lab Sheet 4

The document provides instructions for building a single-cycle MIPS processor in Verilog. It lists the necessary datapath components including a 32-bit ALU, register file, instruction memory, and data memory. It describes resetting the datapath using an active-low reset signal and initializing the instruction memory and data memory. Students are tasked with writing diagnostic programs to test the processor implementation and developing a Verilog controller to generate control signals for the datapath. Component propagation delays must also be modeled in the Verilog code.

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98140207
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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI Second Semester 2012-2013 CS C342 Advanced Computer Organization Lab Sheet

- 4 In this lab you will build a single-cycle processor. You will need to verify that it executes a given subset of the MIPS instruction set.

Datapath Design
Implement the needed components in Verilog. You may use behavioral or a combination of behavioral and structural Verilog features. All Verilog models should correspond to realistic components, such as, registers, comparators, shifters, etc.

Datapath Components
There are a few components you will need for your processor, including the following. Use components created by you in previous labs. 32bit ALU Extender sign/zero extender Multiplexers m16x2, m32x2, m32x3, m32x5, m5x2: multiplexers with various widths and number of inputs 32bit register Register File Shifter logical 32 PC (you have to create this in todays lab) Instruction Memory 32 words deep, 32bit wide (you have to create this in todays lab) Data Memory 32 words deep, 32 bit wide (you have to create this in todays lab)

Resetting and Initializing the Data-paths


Your data-paths must employ an active-low, master reset signal, called Reset_L. This signal should be kept at the de-asserted level at all times, except when the processor is being reset. To reset the processor, drive Reset_L low for at 2 integral clock cycles and then reset Reset_L to high level. The master reset should feed into all reset types of signals of the datapath, such as those of the register file. You have to provide a unit that is external to the main control unit that contains at least one register called IPC. This register supplies the first Program Counter (PC) that your processor should execute after reset". IPC and all other input control signals should be driven by the top level test module of your model. Also write a verilog module which when run will initialize the Data Memory to all zeros and the first location of instruction memory to the machine code corresponding to ADD $2,$3,$4 (machine code shown below) 000000 00011 00100 00010 00000 100000 Opcode Rs Rt Rd Shamt function

Testing and Diagnostic Programs


You should write diagnostic programs to test your MIPS processor. These programs should exercise all instructions your datapath supports.

Single-Cycle Data-Path
Develop an implementation in Verilog of a single-cycle processor for a subset of the MIPS architecture given below.

Supported Instructions
Build a single-cycle datapath that implements the following subset of MIPS instructions. arithmetic (signed) add, sub logical and, or branch beq data transfer lw, sw

Verilog Controller for the Datapath


Use the controller you built in the earlier labs. This CU should take the exact bits from the 32-bit instruction and generate the control signals. You must add any control signals necessary to read instructions from the instruction memory, and the next instruction logic" to generate the Program Counter (PC) of the instruction which needs to be fetched next.

Component Propagations Delays (To be done later)


All of your Verilog components must incorporate reasonable" propagation delays. For each component, think about how that component would be implemented using discrete gates. Use this mental discrete gate implementation to estimate the delays to use. There is no exact right or wrong answer for the delays to use. The delay models may be kept simple, ie, one delay value can be used for an entire component (which should be the maximum worst-case delay). For the datapath controller you should use a delay of 20T.

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