International Journal of Science and Research (IJSR), India Online ISSN: 2319-7064

Quaternary Arithmetic Logic Unit Design Using VHDL

Prashant Y. Shende1, R. V. Kshirsagar
2

Student, M. Tech. Department of Electronics (VLSI), PCE, Nagpur, India 1 Professor and Head, Department of Electronics (VLSI), PCE, Nagpur, India2

Abstract: The arithmetic logic unit (ALU) is the core of a CPU in a computer; the adder cell is the elementary unit of an ALU. The constraints the adder has to satisfy are area, power and speed requirements. The delay in an adder is dominated by the carry chain. Arithmetic operations such as addition, subtraction and multiplication still suffer from known problems including limited number of bits, propagation time delay, and circuit complexity. Carry free arithmetic operations can be achieved using a higher radix number system such as quaternary Signed Digit (QSD). We proposed fast arithmetic logical unit based on quaternary signed digit number system where the carry propagation chain are eliminated, hence it reduce the propagation time in comparison with radix 2 system, each digit can be represented by a number from -3 to -3. In any n digit QSD number, each digit can be represented by a number from the digit set [-3,-2,-1, 0, 1, 2, 3]. Operations on a large number of digits can be implemented with constant delay and less complexity. Keywords: quaternary sign digit, fast computation, multiplier, quaternary logic, Carry/borrow free.

1. Introduction
The various digital systems such as computers and signal processors, arithmetic operation plays important role. The speed of system increases with increasing the speed of addition and multiplication. In conventional binary number system, carry may propagate all the way from the least significant digit to the most significant. Thus the addition time is dependent on the word length. In this paper, we propose a high speed QSD arithmetic logic unit which is capable of carry free addition, borrow free subtraction. The QSD addition/subtraction operation uses a fixed number of minterms for any operand size. In QSD number system carry propagation chain are eliminated which reduce the computation time substantially, thus enhancing the speed of the machine. Signed digit number system offers the possibility of carry free addition. QSD Adder /QSD Multiplier circuits are logic circuits designed to perform high-speed arithmetic operations. In QSD number system carry propagation chain are eliminated which reduce the computation time substantially. There are two steps involved in the carry-free addition. The first step generates an intermediate carry and sum from the addend and augends. The second step combines the intermediate sum of the current digit with the carry of the lower significant digit, thus enhancing the speed of the machine. The paper is structured as follows: Section II presents the basic concept for performing any operation in QSD, first convert the binary or any other input into quaternary signed digit. Section III presents Adder/Substractor Design. Section IV presents multiplier unit, logical unit is present in section V, in section VI present simulation results. Then we provide our conclusions in Section VII.

Signed digit representation of number indicates that digits can be prefixed with a (minus) sign to indicate that they are negative. Signed digit representation can be used to accomplish fast addition of integers because it can eliminate carriers. QSD numbers are represented using 3-bit 2s complement notation. Each number can be represented by

D xi 4i
Where xi can be any value from the set {3, 2, 1, 0, 1, 2,3} for producing an appropriate decimal representation. A QSD negative number is the QSD complement of QSD positive number i.e.3 = -3, 2 = -2, 1 = -1. For digital implementation, large number of digits such as 64, 128, or more can be implemented with constant delay. A high speed and area effective adders and multipliers can be implemented using this technique. For digital implementation, large number of digits such as 64, 128, or more can be implemented with constant delay. A higher radix based signed digit number system, such as quaternary signed digit (QSD) number system, allows higher information storage density, less complexity, fewer system components and fewer cascaded gates and operations. A high speed and area effective adders and multipliers can be implemented using this technique [2, 1]. Also we can obtain redundant multiple representation of any integer Quantity using this QSD number system [3]. Examples of n digit QSD number are as follows: For example:

2. Basic Concept
For performing any operation in QSD, first convert the binary or any other input into quaternary signed digit.

133 .

(133) QSD 1 4 2 3 41 3 4 0

16 12 3 (25)

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Th he basic quate ernary operator rs are very similar to binar ry op perators and the ey are obtained d from Boolean n algebra. ented QSD number. n The mapping 3-bit binary represe between n the 5- bit inp put and the 3-bit output is shown in Table 2.

3. Adder/ Su ubtracter Design D

A carry-free add dition is desira able as the num mber of digits is rge. The carry y-free addition n can achieve e by exploitin ng lar red dundancy of QSD numbe er and QSD addition. Th he red dundancy allows multiple re epresentations of any intege er qu uantity i.e., 61 10 = 12QSD = 22QSD. There e are two step ps inv volved in the carry-free add dition. The first t step generate es an n intermediate carry c and sum from the adden nd and augend ds. Th he second step combines the t intermedia ate sum of th he cu urrent digit with h the carry of the lower sign nificant digit. To T pre event carry fro om further ripp pling, we define e two rules. Th he fir rst rule states that t the magni itude of the in ntermediate sum m mu ust be less tha an or equal to 2. The second d rule states tha at the e magnitude of o the carry must m be less th han or equal t to 1.C Consequently, the magnitud de of the seco ond step outpu ut can nnot be greater than 3 which can be re epresented by a sin ngle-digit QSD D number; henc ce no further carry is required d. In step 1, all pos ssible input pai irs of the adde end and augend ds are e considered [4 4, 6] the output t ranges is from m -6 to 6. he range of the e output is from m -6 to 6 whic ch represent th he Th int termediate carr ry and sum in n QSD format, , some number rs ha ave multiple re epresentations, but only thos se that meet th he de efined rules ar re chosen. Bot th inputs and outputs can b be en ncoded in 3-bit t 2s complem ment binary num mber. Since th he int termediate car rry is always between b -1 an nd 1, it require es on nly a 2-bit bin nary representation [1, 4]. Finally, F five 6 6va ariable Boolea an expression ns can be extracted. Th he int termediate carr ry and sum circ cuit is shown in n Figure 1.

Figure 2: The second st tep QSD adder r -variable Boolean expression ns can be extra acted from Three 5Table 1 figure 2 sho ows the diagram of the sec cond step added. ing between inp puts and outpu uts of the Table 2: The mappi seco ond step QSD adder
QSD A Ai Bi 1 2 1 1 0 2 0 1 1 0 -1 1 2 0 0 1 -1 -1 1 1 0 -1 -1 1 0 1 -2 -1 1 -1 0 -2 -1 1 -2 INPUT B Binary Ai Bi 01 010 01 001 00 010 00 001 01 000 11 010 00 000 01 111 11 001 00 111 11 000 01 110 11 111 00 110 11 110 OUTPUT Decim mal QSD Bi inary Sum m Si Si 3 3 1 111 2 2 0 010 2 2 0 010 1 1 0 001 1 1 0 001 1 1 0 001 0 0 0 000 0 0 0 000 0 0 0 000 -1 -1 1 111 -1 -1 1 111 -1 -1 1 111 -2 -2 1 110 -2 -2 1 110 -3 -3 0 001

The imp plementation o of an n-digit QSD adder r requires n QSD car rry and sum ge enerators and n-1 n second step p added as shown in i Figure 3. The T result turns out to be an n n+1digit number [4].

Figure 1: The T intermedia ate carry and su um generator. In step 2, the in ntermediate car rry from the lo ower significan nt git is added to the sum of th he current digit t to produce th he dig fin nal result. The e addition in this step produces no carr ry be ecause the cur rrent digit can n always abso orb the carry-i in fro om the lower digit. d The Tab ble 1 shows th he outputs of a all po ossible combin nations of a pa air of interme ediate carry (A A) an nd sum (B). Table T 1: The ou utputs of all po ossible combinations of a pair r of int termediate carr ry (A) and sum m (B)
BA -1 0 1 -2 -3 -2 -1 -1 -2 -1 0 0 -1 0 1 1 0 1 2 2 1 2 3

Figure e 3: Five bit QS SD adder

ultiplier Des sign 4. Mu

a generally two methods for a mult tiplication There are operatio on: parallel and d iterative. QSD multiplication can be impleme ented in both w ways, requiring g a QSD partia al product
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Th he result of add dition in this st tep ranges from m -3 to 3. Sinc ce car rry is not allow wed in this step, the result be ecomes a singl le dig git QSD outpu ut. The inputs s, the intermediate carry an nd sum, are 2-bit an nd 3-bit binary y respectively. The output is a

International Journal of Science and Research (IJSR), India Online ISSN: 2319-7064
generator and QSD adder as basic components. A partial product, Mi, is a result of multiplication between an n-digit input, An-1-A0, with a single digit input, Bi, where i = 0.n-1. The primitive component of the partial product generator is a single-digit multiplication unit whose functionality can be expressed as shown in Table 3. Table 3: The outputs of all possible combinations of a pair of multiplicand (A) and multiplier (B)
BA -3 -2 -1 0 1 2 3 -3 9 6 3 0 -3 -6 -9 -2 6 4 2 0 -2 -4 -6 -1 0 1 2 3 3 0 -3 -6 -9 2 0 -2 -4 -6 1 0 -1 -2 -3 0 0 0 0 0 -1 0 1 2 3 -2 0 2 4 6 -3 0 3 6 9
3 4 6 9 1 1 ,03 10 2 2 ,12 21,3 3 11 10 12 21

An nxn-digit QSD multiplication requires n partial product terms. In an iterative implementation, a 2ndigit QSD adder is used to perform add-shift operations between the partial product generator and the accumulator. After n iterations, the multiplication is complete. In contrast, a parallel implementation requires n partial product circuits and n-1 QSD adder units.

The single-digit multiplication produces M as a result and C as a carry to be combined with M of the next digit. The range of both outputs, M and C, is between -2 and 2. According to Table 5, and using the same procedure as in creating Table 1 and 2, the mapping between the 6-bit input, A and B, to the 6-bit output, M and C, results in six 6varible Boolean expressions which represent a single-digit multiplication operation. The diagram of a single-digit QSD multiplier is shown in Figure 4.

Figure 4: A Single- digit QSD Multiplier The implementation of an n-digit partial product generator uses n units of the single-digit QSD multiplier. Gathering all the outputs to produce a partial product result presents a small challenge. The QSD representation of a single digit multiplication output, shown in Table 4, contains a carry-out of magnitude 2 when the output is either -9 or 9. This prohibits the use of the second step QSD adder alone as a gatherer [4, 5]. In fact, we can use the complete QSD adder from the previous section as the gatherer. Furthermore, the intermediate carry and sum circuit can be optimized by not considering the input of magnitude 3. The QSD partial product generator implementation is shown in Figure 5. Table 4: The QSD representation of a single-digit multiplication output
SUM -9 -6 -4 -3 -2 -1 0 1 2 QSD represented Number QSD coded number

Figure 5: The n-digit QSD partial product generator

A binary reduction sum is applied to reduce the propagation delay to 0 (log n). The schematic of a 4x4 parallel QSD multiplication is shown in Figure 6.

2 1 33 1 2,22 10 0 3 ,11
0 2 ,1 2 01 ,1 3 00 1 3 ,01 1 2 ,02

21 12 10 11 02 01
00 01 02

Figure 6: The 4x4 parallel QSD multiplication circuit

5. Logic Unit Design

The quaternary logic unit includes the inverter, MAX function implementation and MIN function implementation
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wh hich are similar to the OR function and AND functio on res spectively. Th he quaternary logic l levels ar re expressed i in ter rms 2-bit binar ry and same binary AND an nd OR function ns can n be used to re ealiase MIN an nd MAX functi ion respectively y. Th he truth table fo or inverter, MA AX, MIN funct tion is shown i in tab ble-5. Table 5: Tru uth Table of In nverter, Max fu unction, Min function

7. Conclusion
The prop posed QSD ar rithmetic logic unit is better than t other binary arithmetic a logic c unit in terms of number of f gates and higher number of b bits operation within const tant time. Efficient design for adder block to t perform ad ddition or cation will inc crease operatio on speed. QSD D number multiplic uses 25% less space than BSD to o store numbe er, higher number of gates can be b tolerated for r further improv vement of QSD adder.

Refere ences
[1] Na agamani A. N N, Nishchai S, Quaterna ary High Performance Ar rithmetic Logic Unit Desig gn, 14th uromicro Conf ference on Digital D System m Design, Eu 2011. eena Rani, L Laxmikant Sin ngh, Neelam Sharma, Re FPGA Implem mentation of f fast Adde er using Qu uaternary Sig gn Digit Nu umber System m, 2009 Int ternational con nference on Trend T in Elect tronic and Ph hotonic Deice & Systems (EE ECTRO-2009). Pra anali S.Kamb ble & S.M.Ch houdhary, R Review of VH HDL Impleme entation of Qu uaternary Sign ned Adder Sy ystem, Interna ational Journal on Advanced Electrical and Electronics Engineering, (IJAEEE), ( ISS SN (Print): ume-1, Issue-1, , 2012 2278-8948, Volu ongpol Ongw wattanakul Ph haisit Chewp puttanagul, So Da avid J. Jackso on, Kenneth G. Ricks, Q Quaternary Ar rithmetic Logi ic Unit on a Programmab ble Logic De evice, Electri ical and Com mputer Enginee ering The Un niversity of Al labama, Tusca aloosa, AL 354 487-0286, US SA. Ifa at Jahangir, D Dihan Md. Nu uruddin Hasan n, Nahian Alam Siddiquet , Shajid lslar rn, Md. Mehe edi Hasan, D Design of Qua aternary Seque ential Circuits s Using a Ne ewly Proposed d Quaternary Algebra, A Proce eedings of 2009 12th Intern national Confe erence on Com mputer and Inf formation Te echnology, (ICCIT ( 2009 9) 21-23 De ecember, 2009, , Dhaka, Bangl ladesh Va asundara Patel l K S, K S Gurumurthy, G D Design of High Performance Quaternary y Adders, Int ternational Jou urnal of Comp puter Theory and a Engineerin ng, Vol.2, No o.6, December, , 2010, 1793-8201

6. Results
he quaternary based arithme etic unit is wr ritten in VHD DL Th an nd synthesized on SPARTAN N 3(3 xc3s50-5pq208) FPGA A de evice using Xilinx project navigator n tool. Table 6 show ws the e LUT utiliza ation and dela ay performanc ce of the QSD D AL LU. The delay y comparison graph g is shown n in figure 7 an nd fig gure 8 shows the t number of f LUT used by y the arithmeti ic un nits. The QSD number is cap pable of repres senting twice a as mu uch magnitud de in each digit compared to the binar ry rep presentation. The T overall dela ay of the QSD ALU is total o of co onversion delay y and computat tion delay.
8 7 6 5 4 3 2 1 0 AD DD MUL INV V MAX MIN

[2]

[3]

[4]

[5]

Figure 7: Gra aph showing tim ming delay of arithmetic unit ts 1000 800 600 400 200 0 ADD MUL INV MAX MIN M Figure 8: The number n of LUT T used by the arithmetic a units s. Table 6: Ti iming delay an nd number of LTU L used in SPART TAN 3
Opcode 0 1 10 11 100 Alu unit Delay D LTU ut tilization ADD 5.146 142 MULTIPLY M 5 ns 5.98 972 INVERTER 7. .665 ns 2 MAX/OR 7. .842 ns 2 MIN/AND 7. .842 ns 2

[6]

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