CpE358/CS381 Switching Theory and Logical Design Class 13

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-452

Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-453

Course Roadmap

Combinatorial Circuits

Logic Circuits with gates Logic Circuits with memory

Sequential Circuits

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-454

Course Roadmap

Combinatorial Circuits

Logic Circuits with gates Logic Circuits with memory Clocked Memory Synchronous

Sequential Circuits

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-455

Course Roadmap

Combinatorial Circuits

Logic Circuits with gates Logic Circuits with memory Clocked Memory

Sequential Circuits

Asynchronous Synchronous

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-456

Mealy/Moore Models
Output is a function of state only = Moore Model

State

Outputs

State Transition Controls

Inputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-457

Mealy/Moore Models
Output is a function of state and inputs = Mealy Model, a more generic model

State

State Transition Controls Output Logic

Inputs

Outputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-458

Rearranging Circuit Model

State Transition Controls

State

Inputs

Output Logic

Outputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-459

Rearranging Circuit Model

State Transition Controls

Output Logic

Outputs

State

Inputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-460

Rearranging Circuit Model

Inputs

Combinational Logic

Outputs

State

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-461

Synchronous Sequential Circuit

JJ G X
n inputs

Combinational Circuit

J G Z
m outputs

Storage Element(s) Clock

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-462

Asynchronous Sequential Circuit

JJ G X
n inputs

J G y

Combinational Circuit

J G Z
m outputs

JG Y

k inputs Delay(s)

k outputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-463

Asynchronous Sequential Circuit

JJ G X
n inputs

J G y

Combinational Circuit

J G Z
m outputs

JG Y

k inputs Delay(s) Secondary variables Excitation variables

k outputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-464

Asynchronous Sequential Circuit

JJ G X
n inputs

J G y

Combinational Circuit

J G Z
m outputs

JG Y

k inputs Delay(s) Secondary variables Excitation variables

k outputs

Change of input variable(s) creates (delayed) change of secondary variable(s)

www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-465

Stability Condition
With no change in X input, Z output and Y states attain constant values

JJ G JJJ G J G JJG JG JJG X = C X Z CZ , Y CY

JJ G X
n inputs

J G y

Combinational Circuit

J G Z
m outputs

JG Y

k inputs Delay(s) Secondary variables Excitation variables

k outputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-466

Stability Condition
With no change in X input, if Y states do not attain constant values, system is JJ G JJJ G JG J G unstable

X = CX

but Y y

JJ G X
n inputs

J G y

Combinational Circuit

J G Z
m outputs

JG Y

k inputs Delay(s) Secondary variables Excitation variables

k outputs

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-467

Steady-State Condition

JJ G X
n inputs

J G y

Combinational Circuit

J G Z
m outputs

JG Y

k inputs Delay(s) Secondary variables Excitation variables

k outputs

J G JG y =Y
In steady-state, delays become irrelevant
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-468

Single Input Changing Condition

Circuit delays can never be equal, so only one variable can change at a time (compared to time to reach stable state)

JJ G X
n inputs

D( X i )
Combinational Circuit

D( X i ) D( X j )
J G Z
m outputs

J G y

D( X j )

JG Y

k inputs

k outputs

D( y p )
Delay(s) Secondary variables

D( y q )Excitation
variables

D( y p ) D( y q )
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-469

Analysis of Asynchronous Circuits

Identify feedback loops to be able to find excitation and secondary variables:

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-470

Analysis of Asynchronous Circuits

Identify feedback loops to be able to find excitation and secondary variables: y1 y2 x Y2 Y1

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-471

Analysis of Asynchronous Circuits

y1 y2 x Y2 Y1

Write Boolean functions expressing excitation variables in terms of input and secondary variables:

Y1 = ( xy1 ) + ( x ' y 2 )

Y2 = ( xy '1 ) + ( x ' y 2 )

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-472

Analysis of Asynchronous Circuits

Y1 = ( xy1 ) + ( x ' y 2 ) Y2 = ( xy '1 ) + ( x ' y 2 )
Plot excitation variable in a map, as a function of input and secondary variables: input(s)
y1y2\x 00 0 0 1 1 0 1 0 0 1 1 y1y2\x 00 01 11 10 0 0 1 1 0 1 1 1 0 0

secondary variable(s)

01 11 10

Y1

Y2

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-473

Analysis of Asynchronous Circuits

Y1 = ( xy1 ) + ( x ' y 2 ) Y2 = ( xy '1 ) + ( x ' y 2 )
Plot excitation variable in a map, as a function of input and secondary variables. Create transition table from excitation variable map:
y1y2\x 00 01 11 10 0 0 1 1 0 1 0 0 1 1 y1y2\x 00 01 11 10 0 0 1 1 0 1 1 1 0 0 y1y2\x 00 01 11 10 0 00 11 11 00 1 01 01 10 10

Y1

Y2

Transition table

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-474

Analysis of Asynchronous Circuits

Y1 = ( xy1 ) + ( x ' y 2 ) Y2 = ( xy '1 ) + ( x ' y 2 )
Plot excitation variable in a map, as a function of input and secondary variables. Create transition table from excitation variable map. And mark the stable conditions:
y1y2\x 00 01 11 10 0 0 1 1 0 1 0 0 1 1 y1y2\x 00 01 11 10 0 0 1 1 0 1 1 1 0 0 y1y2\x 00 01 11 10 0 00 11 11 00 1 01 01 10 10

Y1

Y2

Transition table

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-475

Analysis of Asynchronous Circuits

y1y2\x 00 01 11 10 0 0 1 1 0 1 0 0 1 1 y1y2\x 00 01 11 10 0 0 1 1 0 1 1 1 0 0 y1y2\x 00 01 11 10 0 00 11 11 00 1 01 01 10 10

Y1

Y2

Transition table

Consider the effect of a change in the input variable x=0, y1y2=00, stable state
Input, x 0 1 1 State y1y2 00 00 01 Y1Y2 00 01 01 Condition Stable State Transitory condition Stable State

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-476

Analysis of Asynchronous Circuits

y1y2\x 00 01 11 10 0 0 1 1 0 1 0 0 1 1 y1y2\x 00 01 11 10 0 0 1 1 0 1 1 1 0 0 y1y2\x 00 01 11 10 0 00 11 11 00 1 01 01 10 10

Y1 State table for asynchronous circuit

Present state 00 01 10 11

Y2

Transition table

Next state x=0 00 11 00 11

Next state x=1 01 01 10 10

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-477

Analysis of Asynchronous Circuits

y1y2\x 00 01 11 10 0 0 1 1 0 1 0 0 1 1 y1y2\x 00 01 11 10 0 0 1 1 0 1 1 1 0 0 y1y2\x 00 01 11 10 0 00 11 11 00 1 01 01 10 10

Y1 State table for asynchronous circuit

Present state 00 01 10 11

Y2

Transition table

Next state x=0 00 11 00 11

Next state x=1 01 01 10 10

Each line must contain present state for (at least) one of the input conditions to ensure stability

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-478

Analysis of Asynchronous Circuits Problem 9-2

Derive transition table and determine the sequence of internal states for input sequence 00, 10, 11, 01, 11, 10, 00 x1

x2 Y1

Y2

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-479

Analysis of Asynchronous Circuits Problem 9-2

x1

x2 Y1

Y2

Excitation variables are given and feedback loops follow. Derive functions for excitation variables:

Y1 = (( x '1 x2 )'( x2 y1 )')' = x '1 x2 + x2 y1 Y2 = ( x '2 ( x1y 2 )')' = x1y 2 + x2

www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-480

Analysis of Asynchronous Circuits Problem 9-2

Y1 = (( x '1 x2 )'( x2 y1 )')' = x '1 x2 + x2 y1 Y2 = ( x '2 ( x1y 2 )')' = x1y 2 + x2
Plot excitation variables in a map, as a function of input and secondary variables:
x1x2: 00 y1y2 01 11 10 00 0 0 0 0 01 1 1 1 1 11 0 1 1 0 10 0 0 0 0 x1x2: 00 y1y2 01 11 10 00 0 0 0 0 01 1 1 1 1 11 1 1 1 1 10 0 1 1 0

Y1

Y2

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-481

Analysis of Asynchronous Circuits Problem 9-2

x1x2: 00 y1y2 01 11 10 00 0 0 0 0 01 1 1 1 1 11 0 1 1 0 10 0 0 0 0 x1x2: 00 y1y2 01 11 10 00 0 0 0 0 01 1 1 1 1 11 1 1 1 1 10 0 1 1 0

Y1 Create transition table from excitation variable map. And mark the stable conditions:
x1x2: 00 State 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

Y2

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-482

Analysis of Asynchronous Circuits Problem 9-2

Transition table:
x1x2: 00 y1y2 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

State table:
Present state 00 01 10 11 Next state, x1x2= 00 00 00 00 00 01 11 11 11 11 10 00 01 00 11 11 01 11 10 01

With inputs 00, 10, 11, 01, 11, 10, 00:

00 10 11 00 00 00 01 01 11 10 01 01 11 01 00 01 00

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-483

Analysis of Asynchronous Circuits Problem 9-2

Transition table:
x1x2: 00 y1y2 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

Flow table: Expressed with Symbolic state names

x1x2: a State b c d

00 a a a a

01 c c c c

11 b c c d

10 a b b a

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-484

Flow Tables
Problem 9.2:
x1x2: 00 y1y2 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

Previous example:
y1y2\x 00 01 11 10 0 00 11 11 00 1 01 01 10 10

x1x2: a State b c d

00 a a a a

01 c c c c

11 b c c d

10 a b b a

y1y2\x A B C D

0 A C C A

1 B B D D

Primitive flow table: 1 stable state per row

www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-485

Back to the Races

State Variable 1

subsystem1 Input 1-bit change

Asynchronous Logic subsystem2 State Variable 2

Which occurs first? What effect does the order of change have on system operation?

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-486

Race Conditions in Asynchronous Circuits

Consider Problem 9.2:
x1x2: 00 y1y2 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

System is in state 00 with input 00, a stable condition.

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-487

Race Conditions in Asynchronous Circuits

Consider Problem 9.2:
x1x2: 00 y1y2 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

System is in state 00 with input 00, a stable condition. Input is changed to 01, which should lead to state 11 But: which variable changes first: y1 or y2? And does it make any difference to the resulting state?

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-488

Race Conditions in Asynchronous Circuits

Consider Problem 9.2:
x1x2: 00 y1y2 01 11 10 00 00 00 00 00 01 11 11 11 11 11 01 11 11 10 10 00 01 01 00

System is in state 00 with input 00, a stable condition. Input is changed to 01, which should lead to state 11 But: which variable changes first: y1 or y2? And does it make any difference to the resulting state? In this case, if either variable changes before the other, the system may briefly visit state 01 or 10, but the end result is the same the systems final state is 11 This is a noncritical race
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-489

Race Conditions in Asynchronous Circuits

Consider this transition table:
x1x2: 00 y1y2 01 11 10 0 00 1 11 01 11 10

System is in state 00 with input 0, a stable condition. Input is changed to 1, which should lead to state 11 But: which variable changes first: y1 or y2? And does it make any difference to the resulting state?

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-490

Race Conditions in Asynchronous Circuits

Consider this transition table:
x1x2: 00 y1y2 01 11 10 0 00 1 11 01 11 10

System is in state 00 with input 0, a stable condition. Input is changed to 1, which should lead to state 11 But: which variable changes first: y1 or y2? And does it make any difference to the resulting state? 0 0 1 0 1 1 If y1 changes first:

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-491

Race Conditions in Asynchronous Circuits

Consider this transition table:
x1x2: 00 y1y2 01 11 10 0 00 1 11 01 11 10

System is in state 00 with input 0, a stable condition. Input is changed to 1, which should lead to state 11 But: which variable changes first: y1 or y2? And does it make any difference to the resulting state? 0 0 1 0 1 1 If y1 changes first: If y2 changes first: 0 0 0 1 1 1

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-492

Race Conditions in Asynchronous Circuits

Consider this transition table:
x1x2: 00 y1y2 01 11 10 0 00 1 11 01 11 10

System is in state 00 with input 0, a stable condition. Input is changed to 1, which should lead to state 11 But: which variable changes first: y1 or y2? And does it make any difference to the resulting state? 0 0 1 0 1 1 If y1 changes first: If y2 changes first: 0 0 0 1 1 1 If y1 and y2 change simultaneously, system reaches correct state This is a critical race
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-493

Cycles and Races

Avoid critical races by directing system through a cycle:

x1x2: 00 y1y2 01 11 10

0 00

1 11 01 11 10

x1x2: 00 y1y2 01 11 10

0 00

1 01 11 11 10

x1x2: 00 y1y2 01 11 10

0 00

1 01 11 10 01

Multiple possible stable states between 00 and 11 create the problem 0 0 { 0 1, 1 0 , 1 1 } ?

Intermediate state is unstable, forcing transition to desired state 0 0 0 1 1 1

But there must be a stable state, or system is unstable

0 0 0 1

0 1

1 1

1 0

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-494

Stability Issues in Asynchronous Circuits

Consider: x2

x1 Y

Y = (( x '1 x2 )'( x2 y1 )')' = x '1 x2 + x2 y '

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-495

Stability Issues in Asynchronous Circuits

Consider: x2

x1 Y

Y = (( x '1 x2 )'( x2 y1 )')' = x '1 x2 + x2 y '

Transition table:
x1x2: 0 y 1 00 0 0 01 1 1 11 1 0 10 0 0

Y
www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-496

Stability Issues in Asynchronous Circuits

Consider: x2

x1 Y

Y = (( x '1 x2 )'( x2 y1 )')' = x '1 x2 + x2 y '

Transition table:
x1x2: 0 y 1 00 0 0 01 1 1 11 1 0 10 0 0

There are no stable states for input 11

www.UandiStar
1-497

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Early Asynchronous Sequential Logic

N.O. N.C.

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-498

Early Asynchronous Sequential Logic

N.O. N.C. +V

N.O. N.C. +V

N.O. N.C. +V (xy)

x y Some not-so-early asynchronous logic devices: Mechanical pinball machines Automatic transmissions (using fluid and hydraulic relays)
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-499

Asynchronous Logic With Latches

Previously seen circuit S Q

Q R

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-500

Asynchronous Logic With Latches

Previously seen circuit S Q

Q R With explicit feedback S R Q y Y Q

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-501

Asynchronous Logic With Latches

S R y Transition table:
SR: 0 y 1 00 1 1 01 1 1 11 0 1 10 0 0

Y Q

Y = S '+ Ry if (S+R)=1

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-502

Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-503

Homework 13 due in Class 15

Show all work Problems 9-6, 9-9

www.UandiStar

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-504