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Tutorial-1 Low Noise Amplifier (LNA) Design

By Rashad.M.Ramzan [email protected] Objective:
Low noise amplifiers are one of the basic building blocks of any communication system. The purpose of the LNA is to amplify the received signal to acceptable levels with minimum self-generated additional noise. Gain, NF, non-linearity and impedance matching are four most important parameters in LNA design. The objective of this tutorial is to outline the basic tradeoffs between different amplifying topologies w.r.t gain, NF and impedance matching. After this comparison it is concluded that inductor degenerated common source topology gives the best performance to meet the gain, NF, and impedance matching goals with minimum power consumption in case of narrowband designs.

Goals:
After this tutorial, students should be able to Calculate the gain, input impedance and NF of common gate, common source, and shunt feedback amplifiers. Understand the basic equations and tradeoff between different LNA topologies. understand the tradeoff between the gain, NF, and impedance matching. A supplement tutorial LNA lab is also part of this course which takes the circuit from Problem-1.8 and guides through different analyses to design a practical LNA.

Perform the calculation for inductor degenerated common source topology and

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Problem-1.1(Tutorial)
NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS transistor is in saturation.

a) Consider simplified square law model. (HW)

ID =

Kn (VGS VT ) 2 2

b) Consider the short channel effects as (Tutorial)

K n (VGS VT ) 2 2 1 + (VGS VT ) = Velocity Saturation, Mobility Degradation ID = VGS VT = 0.2V and = 0.1V 1
Observe that this transistor is not a very short channel device as << 1. c) What conclusion can be drawn from part b) about the bias current and transconductance of the transistor for higher IP3?

Solution: a). Homework answer: IP3 = b).

VDD RL
--------------(1)

y ( x) = 0 + 1 x(t ) + 2 x 2 (t ) + 3 x 3 (t )

x(t)

x(t ) = A cos 1 t + A cos 2 t AIP 3 =

4 1 3 3

VGS

NMOS

DC-bias

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ID =

K n (VGS VT ) 2 1 + (VGS VT )
2

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Here we assume a small signal x(t) around the bias (VGS VT), so

K [(VGS VT ) + x(t )] ID = n 2 1 + (VGS VT + x(t ))

2

we define

VGS VT = V
2

--------------- Bias voltage --------------------------------------------------------------(2)

2

K [x(t ) + V ] ID = n 2 ( x(t ) + V ) + 1

K R ( x(t ) + V ) Vo = I D RL Vo = n L 2 1 + ( x(t ) + V )

and we put

K n RL =K 2

<< 1 so

(x(t ) + V ) is also small

1 = 1 1+ 2

1 ( x(t ) + V ) 1 1 + ( x(t ) + V ) 2

( x(t ) + V ) 2 Vo = K ( x(t ) + V ) 1 2 2 3 K Vo = K ( x(t ) + V ) ( x(t ) + V ) 2 K 3 K V o = K V 2 V 3 + 2 K V V 2 x (t ) 2 2

3 K K 3 +K V x 2 (t ) x (t ) 2 2
Comparing (1) & (3) -----------------------------(3)

1 = 2 KV

3 K 3 K V V 2 , 2 = K 2 2
4 3 2 Kv

3 =

K 2

AIP 3 =

4 1 = 3 3

3 KV 2 8 2V 2 = 3V 2 K 3 2
As << 1 3V can be ignored.
2

AIP 3 =

8 2 V 16 V = 3 3

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AIP 3 =

16 V 16 (VGS VT ) = 3 3

-------------------------------(4)

Please, note that this formula only holds for small value of . For larger values compare the lecture notes.

In any case a large gate bias voltage (VGS VT) improves IP3.
Put

V = 0.2V, = 0.1 V -1
16 0.2 = 3.27Volts 3 0 .1

AIP 3 =

3.27 2 1 . 1mW 20dBm IIP3(dBm) = 10 log 50 2

c). From

gm =

K n (VGS VT )(2 + (VGS VT ) ) . 2 (1 + (VGS VT ))2

K (VGS VT ) ID = n 2 1 + (VGS VT )
2

the NMOS transconductance can be found as

By comparison of those two formulas we find

1 + (VGS VT ) VGS VT ID = (VGS VT ) 2 + (VGS VT ) 2 gm

and hence, (4) can be rewritten as

AIP 3

32 I D 3 g m

As shown, IIP3 is decided by the ratio ID/gm which is constant for a given gate bias voltage. Using e.g. a wider transistor does not change this ratio and only the power consumption is increased.

Problem-1.2 (Tutorial)
It is preferred in current RF designs that the input of LNA be matched to 50 . The easiest way is to shunt the gate with a resistor of 50 . a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that Rsh=RL for NF derivation. b) What are the disadvantages of shunt resistor with reference to gain and NF?
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Solution: a). (Please read assumption in the problem statement carefully)

VDD

V 2 n , Rs

Rs Rsh
2

D gmVgs

Vout

V
S

n , Rsh

i 2d

RL

Vin

Rs Zin Rsh

RL Vout

RL is noiseless

(Biasing not shown)

F=

Total output noise power Output noise due to input source

V 2 m , Rs = 4kTRs f

Gain Gate = g m RL
Rsh A = g m RL R +R s sh A = gm
2

V 2 m , Rsh = 4kTRsh f
i 2 d = 4kTg m f

for Rsh = Rs

RL 2

Using superposition, considering one at a time and shorting / opening other sources.

on , Rs

Rsh = V n , Rs g m RL R +R sh s
2 2 2

on , Rsh

Rs = V n , Rsh g m RL R +R sh s
2 2 2

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V 2 no ,d = i 2 d R 2 L
F= V 2 on , Rs + V 2 on , Rsh + V 2 no ,d V 2 on , Rs =1+ V 2 on , Rsh + V 2 o ,d V 2 on , Rs

g 2 m R 2 L R 2 sh 4kTRsh f 2 ( Rs + Rsh ) 4kTg m f R 2 L + F =1+ g 2m R2L R2s g 2m R2L R2s kTR f 4kTRs f 4 S (Rs + Rsh )2 (Rs + Rsh )2
In case of impedance match Rs = Rsh
2 2 gm gm RL RL 4 = 2+ = 2+ F = 1+1+ 2 2 2 2 2 g R R g RL g m Rs Rs m S 2 L Rs m 4RS 4

b).
- Poor Noise Figure - Input signal attenuated by voltage divider - Rsh adds extra noise. - At high frequency, shunt L is needed to tune out Cgs - Reduced gain.

Problem-1.3 (Tutorial)
Another approach to get 50 input impedance match is shunt feedback amplifier shown below.

a) Calculate the gain, input impedance and NF neglecting the gate noise. The gate-drain, gate-bulk, and gate-source capacitance can be neglected as well. b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?

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Solution:
Rs

n , RF

RF gmVgs

Vout

RF RL Rs Vin Zin

V 2 n , Rs

I 2 nD

RL Vout

(Equivalent noise model ignoring gate noise), RL is noiseless

(Biasing not shown)

I 2 nD = 4kTg m f ,V 2 RS = 4kTRS f
V 2 n , out A 2 v ,tot V 2 RS Total input noise power Output noise power due to input source

F=

Here Av,tot = Gain from Vin to Vout Again using superposition theorem

F=

V 2 n , out A 2 v ,tot V 2 RS

Vn

2 RS , out

+ Vn

2 RF , out

+ Vn

2 D , out

A 2 v ,tot V 2 RS

Gain Calculation

Vin = iin (RS + RF ) + Vout Vout = (iin g mVgs )RL

Iin RF Iin Rs Vout RL

Vgs = iin RF + Vo Av ,tot = Vout RL (1 g m RL ) = Vin RS + RF + RL + g m RS RL g m RL g m RL RS 1 + g m RS + 1 + RL + RF RF RF + RL 1 + g m RL

iin Vin

If RF>>RS & gmRF>>1

Av ,tot =

Rs Vgs

RF

Vout gmVgs RL

Av ,tot g m RL
Also

Z in =

By ignoring Cgs, we have considered real part only.

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For source resistance

V 2 nRS ,out = A 2 v ,tot V 2 nRS

For feedback resistance

---------------(1)

Rs Vgs

RF V

RF

V 2 RF ,out
gmVgs RL

Vgs = iRS = iRF VRF + VRF ,out VRF ,out = RL (i g mVgs ) VRF ,out = VRF
1 1+
2

RS + R F RL (1 + g m Rs )

= VRF

RL (1 + g m RS ) RF

n , RF ,out

R = V n , RF L (1 + g m RS ) RF
i Rs Vgs RF gmVgs

---------------------(2)

Similarly

V 2 nD ,out I 2 n,D
RL

VnD ,out RL

+ I nD + g mVgs +
VnD ,out RS + R F
I n,D

VnD ,out RS + R F

=0

Vgs = RS
VnD ,out =

g R 1 1 + + m S R L RS + R F RS + R F
2

I nD RL

So,

V 2 nD ,out = I 2 nD RL

------------------------------------------(3)

Combaining (1) (2) & (3)

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F = 1+

R V 2 n , RF L (1 + g m R S ) RF
A 2 v ,tot V 2 n , RS

I 2 nD R 2 L A 2 v ,tot V 2 n , RS
&

Av ,tot = g m RL , V 2 n , RS = 4kTRS f , V 2 M , RF = 4kTRF

I 2 nD = 4kTg m

R F = 1+ S RF
b).
NF

1 1 + g m RS

+ g m RS

gmRS & RF usually

RS = 50

- Better performance than CS amplifier - RF induces noise - At higher f

a shunt inductor needed to tune out Cgs

- Broadband Amp @ Lower frequency - To make NF

RF > RS and gmRS >> 1

Problem-1.4 (HW)
Common gate amplifier also offers 50 input impedance match and solves the input matching problem.

c) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to source capacitance. a) What are the disadvantage of common gate amplifier with reference to gain and NF?

Problem-1.5 (Tutorial)
The disadvantages of the amplifiers discussed in Problem-2, 3 & 4 can be circumvented by using the source degenerated LNA shown below.

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a) Calculate the input impedance. This inductor source degenerated amplifier presents a noiseless resistance for 50 for input power match. How we can cancel the imaginary part of complex input impedance so that the LNA presents 50 real input resistance at input port. b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to source capacitance. c) Cgd bridges the input and output ports. The reverse isolation of this LNA is very poor. Why reverse isolation is important? Suggest the modification to improve reverse isolation.

Solution: a).
VS Rs Lg iin io Vout VS Ls Rs Lg

VDD RL Vout Ls (Biasing not shown)

gmVgs Zin Vgs Vin

From model above we can write

1 Vin = iin ( jLg + jLs ) + iin j c + io jLs ---------------(1) 1 --------------------------------------(2) io = g mVgs = g m iin jC gs
Substituting (2) in (1)

g L 1 Vin = iin j (Lg + Ls ) + + m s jC gs C gs

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Z in =

Vin g L 1 = j (Lg + Ls ) + + m s iin jC gs C gs

Z in = j (Lg + Ls ) +

g L 1 + m s jC gs C gs

For matching Lg + Ls are canceled out by Cgs. So at frequency of interest

o (Lg + Ls ) =
And

1 1 2 o = (Lg + Ls )C gs o C gs
gm Ls C gs

RS = 50 =

Notes:
a). Ls is typically small and may be realized by the bond wire for source. b). Lg can be implemented by spiral/external inductor.

b).
From part a)

Z in = j (Lg + Ls ) +

g L 1 + m s jC gs C gs

Reference: For series RLC Circuit R L

We can draw this circuit as

Vin

C VC

Rs Vin
Here

Lg + Ls Zin

gm

Ls C gs

Cgs Vgs

Qs =

1 L o L 1 = = R C R o RC

and VC = QSVin

Qin =

o (L g + L s )
RS + g m LS C gs

o (L g + L s ) RS + T LS

Q T

gm C gs

frequency of current gain equal 1

Qin =

o R + S

g m LS C gs

C gs

for match load

RS =

g m LS C gs

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Qin =

1 2 o Rs C gs

Gain

Vgs = QinVin

Vout Rs Vin Zin Lg Vgs Ls RL

I g m = out V gs
Gm = I out V gs g m = = Qin g m V in V in

G m = Qin g m
Vout = G m R L where Gm = Qin g m Vin

so,

Noise Figure:

F=

Total noise power at output noise power at output due to input source
=1+ V 2 nD ,OUT V 2 nRS ,OUT
i 2 n , D = 4kTg m f

For this calculation we ignore channel noise.

F=

V 2 nRS ,OUT + V 2 nD ,OUT V 2 nRS ,OUT

V 2 nD ,OUT = i 2 n , D R 2 L V 2 nRS ,OUT = V 2 n , RS G 2 m R 2 L

F = 1+ V
2 i n2, D R L 2 n , RS

V 2 n , RS = 4kTRS f

&

Gm = Qin g m

Q g R

2 in

2 m

2 L

i 2 n , D = 4kTg m , V 2 n , RS = 4kTRS

F = 1+

2 g m R S Qin

Notes:
- Very good NF value - Narrow band matching - NF

with Q 2

- The Q is dependent upon Lg + Ls, Ls usually small so Q depends mainly upon Lg

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C). Drawbacks
i).

VDD RL Vout Ls
RL generates noise so replace RL with LD so thats

VDD LD VS Rs Lg Ls CL

VS

Rs

Lg

o =

1 LD C L

The CL can be considered the input capacitance of the following mixer or filter.

VDD
ii).

LD Reverse Isolation Vout Cgd Rs Vb Lg Ls

CL

Lo
Reverse isolation depends upon capacitance between output and input. To make it less the cascode architecture can be used.

(Final Design)

Problem-2.6 (HW)
Fill-in the Table below, use the data from Problem-2.4, 2.5, 2.6 and 2.7

Type of LNA Shunt Resistor

Zin Rsh

Noise Factor

Gain

NF (dB)

2+

4 g m RS

g m RL 2

Common Gate Shunt Feedback Source Degenerated

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a) Calculate the NF for all above amplifiers. Assume =2, gm = 20mS, Rs = 50, RF = 500, and Qin = 2. b) Which is the best topology for Narrow Band LNA design at high frequency?

Problem-1.7 (Tutorial)
Real Design: We will design the inductor-source-degenerated LNA shown in Fig below to meet the specification outlined for IEEE802.11b standard. The first cut approximate values are calculated as a starting point for simulation. In LAB3: Design of LNA you will take the same design and modify these component values to meet the specification. LNA Specification: NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, Centre Frequency = 2.4 GHz S11 < -20dB, S22 < -10dB, Load Capacitance = 1pF Technology Parameters for 0.35um CMOS:

Leff = 0.35 m, nCox = 170 A V 2 , Cox = 4.6 mF m 2 , p Cox = 58 A V 2 , = 2

Solution:
Technology 0.35m CMOS:
2 2 o Cox = 170 A V , p Cox = 58 A V , 2 C = mF m = L = m 4 . 6 , 2 , 0 . 35 ox eff

Design Parameters

NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, f0 = 2.4 GHz

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VDD RREF M3 RBIAS RS CB Lg LD M2 Vout M1 Ls CL = 10pF

Vin

Component Description
Ls Matches input impedance Lg Sets the Resonant Frequency fO = 2.4 GHz M3 Biasing transistor which forms current mirror with M1 Ld Tuned output increases the gain and also work as band pass filter with CL M2 Isolates tuned input from output to increase reverse isolation, also reduces the effect of Miller capacitance Cgd CB BC blocking capacitor chosen to have negligible reactance at fO = 2.4 GHz RBIAS Large enough so that its equivalent current noise is small enough to be ignored. (Dont consider it as voltage noise source. Why??)

Design Procedure
Size of M1: From the noisy two-port theory (see the course book or lecture notes):

Gopt = C gs

1 2 1 C = 5 50

----------------------(1)

C gs 4 pF WM 1 3C gs / 2C OX Leff 4 mm ( not feasible huge size, huge power ! )

We will not go for global minimum noise figure. Instead, we will look into the constraint power design approach. Solution: LNA NF will be optimized for given power that is less than the global minimum. In this case the optimum transistor width is

Wopt =

1 3o Leff Cox RS
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while the minimum power-constraint NF :

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Fmin, p = 1 + 2.4

Fmin, p = 1 + 5.6 T T C 1 C

16/18

---------------(A)

As compared to (A) from (1) we can derive

Fmin = 1 +

2 5 T

) = 1 + 2.3

Fmin = 1 + 2.3

-------------------------------------------------(B)

(A) is minimum NF for a given power consumption. (B) is global minimum noise figure. In practice the difference is usually 0.5dB to 1dB (no big deal for Lower Power)

Step - 1:

I1 = I 2 = 5mA (Limited Power consumption)

Step - 2:

WM 1 =

1 3 0 L eff C ox R S
RS = 50, Cox = 4.6 mF m 2 , n Cox = 170 A V , Leff = 0.35m, o = 2f o , f o = 2.4GHz

WM 1 =

1 3 0.35 4.6m 50 o

WM 1 = 3.9 10 4 WM 1 = 3.9 10 4 = 390m

Step - 3:

2 C gs1 = WM 1 Leff Cox 3 C gs1 = 2 390 0.35 4.6m = 0.41 pF 3

or

W g m1 = 2 n C ox I DM 1 L M1

g m1 =

2 I DM 1 VGS VT

(for short channel model)

390 g m1 = 2 170 5m = 43 mA V 0.35

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g m1 43 mA V = = 104G rad Sec C gs1 0.41 pF

Assuming Now

=2 o T

Fmin = 1 + 5.6

Fmin = 1 + 5.6 NF 2.55dB

2 2.4G 2.55dB 104G

This NF is very close to the specified value. If we increase ID then T should increase slightly as well and hence, a lower NF value can be achieved at expense of more power. Step - 4: Source and gate inductance such that they cancel Cgs and set

50 input impedance

o = 2f o = 2 2.4 = 15G rad Sec

From previous problem
R S = RTransformed = g m LS T LS C gs

LS =

RS

50 0.5nH 100G

LS = 0.5nH can be implemented using the bond wire.

1 + = L L g s Now 02 C gs1

Lg + Ls =

1 = 10.81nH (15G ) 0.41 pF

2

Lg 10nH
Step - 5:

Ld = Ld =

1 o 2C L
2

Q C L = 1 pF

1 4.4nH (15G ) 1 pF

Ld = 4.4nH
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Step - 6: Size of M3 is chosen to minimize power consumption

W M 3 = 70m, R REF = 2k I 3 = 0.6mA

R BIAS = 2k
(Large enough so that its equivalent current noise can be neglected) so good value @ 2.4G

C B = 10 pF ( X C 6.6
Step - 7: Size M2 = M3

XB =

1 = 6.6 ) 2f o C B

So that they can have shared Drain Area.. (Note: We will simulate same LNA circuit in LAB # 2)

Problem-1.8 (Point to Ponder):

Connecting two inductor-source-degenerated LNAs as shown beneath makes a differential LNA. The differential LNA has the advantage of a higher common mode rejection ratio and less sensitivity to the ground inductance variation Ls compared to its single-ended counterpart.

a) Compare intuitively the NF of single ended and differential amplifier if both have same power consumption. b) If low power is not a parameter on interest, which LNA has lower NF?

Instructions:
For hand calculation of NF you can ignore the gate noise of the device and noise generated by the load resistance RL.

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