Low Power Cascode Operational Transconductance Amplifier with Group Delay and Significant Gain Abstract- In this paper

with design and analysis of folded cascode operational transconductance amplifier (OTA). A new technique is used to design for high DC gain reduced leakage power CMOS circuits without affecting dynamic power dissipation .The name of applied technique is MTCMOS, which gives the high DC gain (90db) with the reduced low power consumption (15.37ns) and reduced leakage current (166pa). The proposed OTA is simulated at 45nm CMOS technology and the circuit is operated at 1.8V supply using cadence software. We designed analog circuit with extremely low leakage current as well as high current driving capability for the large input voltage. High speed with very low group delay (1.19*10-9) is achieved by proposed paper. So the delay of the circuit is 10% reduced. Keyword-CMOS design, Wilsson current mirror, MTCMOS technique. 1. IntroductionThe CMOS technology is scaling down increasing market for portable electronic equipment, which gives the design of high performance with low voltage, low power. The OTA is an opamp without an output buffer so it can drive only loads. It is also called a voltage controlled current source (VCCS) because its differential input voltage produces an output current. In analog circuits OTA is important building. It faces many difficulties in low voltage design providing low power consumption and high gain [1]. Presented paper remove this type of difficulties and gives the high gain, low power consumption and low voltage this paper is based on the new technique i.e. MTCMOS technology. The operational transconductance amplifier (OTA) is a basic element in this type of circuit whether for ADC design switched capacitors technique is used. We aim to design a folded cascode OTA circuit insight of sigma delta analog to digital converter design using for wide band radio applications [2]. The OTA is an important bottleneck for various analog systems and circuits. It is mainly used as active element in variable gain amplifiers, data converters, interface circuits, continuous time oscillators, switched capacitor filters and sample and hold circuits [3, 4, and 5]. In references [6] folded cascode OTA proposed in which input terminals self cascode but the remains of the circuit self cascode is used since the overall circuit works as load. In references [7, 8] to have high output impedance and thereby high gains, cascading is done, where two mosfet are placed one above the other. Folded cascode OTA is used for high speed applications and takes this type of capability to provide high gain and large bandwidth [9]. These papers were proposed in a simple OTA with low supply voltage and high gain [10]. The proposed folded cascode OTA using stacking technique. At input terminals stacking is not used but on rest of the circuits stack is used but on rest of the circuits stack is used because this whole circuit work as load[11]. This paper was proposed a temperature folded cascode operational transconductance amplifier (OTA) for high temperature applications such as hybrid electric

vehicles [12]. In [13] folded cascode OTA comes from folding down P-channel cascode active loads of a differential pair and changing the MOSFET to N-channel. In analog circuits has given a decisive boost towards low voltage low power design [14] [15]. This paper was presented application of the adaptive biasing technique implementation of a fully differential adaptive bias OTA and DC enhancement through negative load impedance compensation [16]. Enhance the gain is by increasing the output resistance at the output stage by cascading the transistor but in turn suppressing the voltage swing [17]. Infinite impedance two input voltage are needed to design an ideal OTA, it means no input current is supplied. To control an ideal current source the differential signal between these two inputs is used and we take infinite input range, it means output voltage is not proportional related to output current. It acts as an output function. Transconductance is the proportionality factor between input differential voltage and low output current. To design the real OTA, we need the circuitry to produce an internal representation of the input differential voltage and to provide current to the output by processing the input voltage with low input current over wide common input range ,it means not dependent on output voltage. In OTA maximum output current with the inductance can adjust because an OTA can be used without feedback [18].

In+ Gm*VIN InOut

Figure1-Basic operational transconductance amplifier 2. Basic configuration of OTAAn OTA is an amplifier where except the input and output nodes all nodes are low impedance. OTA's transconductance can be adjusted by the bias current this is a great feature of it. OTA can be tuned by changing the bias current I bias by Filters. The input signal amplitude and the parasitic input/output capacitances are the two practical concerns when designing an OTA for filter applications are. OTA gain to become non-linear is done by large signals. The external capacitance should be large compared to the input or output parasitic of the OTA. Filter's maximum frequency is limited by this and causes amplitude or phase errors. Proper selection of I bias can reduce these errors to much extent. Simple OTA performance is limited by its input and output voltage swing. Folded Cascode OTA is used which is much improved to overcome these limits of simple OTA.

The folded cascode OTA is shown in Fig. 2 The name folded cascode comes from folding down n-channel cascode active loads of a diff-pair and changing the MOSFETs to pchannels. The output Voltage of the OTA is given by:

The Unity gain frequency of the OTA is

Gm is computed as: ) The open loop voltage gain is given by{ }

Where gm9, gm4 and gm6 are transconductance of M9, M4 and M6 transistors respectively. ID is the bias current flowing in M4, M6, and M9 MOSFETs. Like, CL is the capacitance at the output node. N and P are the parameters related to channel length modulation respectively for PMOS and NMOS devices. Taking the complementarities between the M4 and M6 Transistors into account:

The gain expression becomes: { }

3. Main features of the circuit3.1. Power dissipation of circuitThe maximum power allowed to dissipate in a circuit is defined as,
( )

Where is the power dissipation, is the maximum junction temperature [13]. is ambient temperature. ja is the thermal resistance; depends on parameters such as package material, die size and package size. The smaller die size and package, the higher is gained then the power dissipation will be reduced .Total power dissipation in a device can be calculated as

is the quiescent power dissipated in a circuit with no load connected at the output. Is the power dissipated in the circuit with a load connected to the output and this power cannot be dissipated by the load. = supply current total supply voltage with no load. =output current voltage difference between supply voltage and output voltage of the same supply. 3.2. Power supply rejection ratio (PSRR)This is also called a supply voltage rejection ratio (SVRR) or power supply sensitivity (PSS). If a power supply voltage contains an incremental component V due to noise, a corresponding voltage will appear at the op-amp. The PSRR is defined as where is the differential gain. It is common to the express the PSRR is decibels, then ( ) At the simulation of the proposed circuit is achieved PSRR is given below. We have achieved the improved PSRR [2].

Figure2 - shows the PSRR of the circuit 4. Proposed circuit with applied techniqueThe folded cascode OTA is shown in figure 5. The circuit is "folded cascode" called because in this we fold n-channel cascode active loads of diff-pair and MOSFETs are switched to pchannels. There is a differential stage in folder cascode having M9 and M10 PMOS transistor to charge Wilson mirror.M5-M6-M7-M8 transistors are given DC biased voltages by MOSFETs M11 and M12.For MTCMOS technique M13 and M14 transistors are used. Transistors M13 M14 are inserted in the circuits. These transistors are used to remove the drawback of dc gain. To convert the diff-amplifier drain current to gmVin, AC input voltage is applied between V+ and V-.MOSFETs M1 to M6 is mirrored by this differential drain current [19]. This AC differential drain current is mirrored in the cascaded MOSFETs M1 to M6. To increase the DC gain of the circuit we apply the MTCMOS technique. In MTCMOS technique, transistors of low threshold voltage become disconnected from power supply by using high threshold sleep transistor on the top and bottom of the logic circuit. Logic Transistor having low threshold voltage (low-Vth) is used to design logic. The sleep transistors are controlled by the sleep signal. During the active, the sleep signal is disserted, causing both high Vt transistor to turn on and provide a virtual power and ground to the low Vt. When the circuit is inactive sleep signal is asserted forcing both High Vt transistor to cut-off and disconnect power lines from the low Vt logic. This results a very low sub-threshold leakage current power to ground when the circuit is in standby mode.

S
Virtual V dd

Low VT
Input
CMOS

Output

Logic
Virtual gnd

Figure4- Shows the basic block diagram of the applied technique

m13 Virtual

m1

m3

m 2 m5

m4

m6 m12

m9

m10

m7

m8

m11

Virtual gnd S m14

Gnd Figure5-Proposed folded cascode OTA

5. Simulated results-Using 45nm CMOS technology, we have designed a new operational

transconductance amplifier in fig 5 which is simulated at 1.8V supply voltage by the help of the cadence tool. Fig (OTA) contains the transistor that all have the same sizing. Fig 2 shows the PSRR (Power Supply Rejection Ratio) which is showing 125db which is achieved better than latest paper. Fig3 shows the CMRR (Common Mode Rejection Ration). Fig 4 shows the ICMR of the OTA. Fig6 shows the DC gain and the phase margin. Fig1 shows the group delay of the circuit. Fig 8 shows the input noise of the circuit. Fig 9 shows the output noise of the circuit. Fig 10 shows the leakage current of the output waveform. Fig11 shows the magnitude of the circuit.

Figure6- shows the dc gain and phase margin of the circuit

Figure 7-shows the group delay of the circuit

Figure 8- shows the input noise of the circuit

Figure9-shows the output noise of the circuit

Figure10-shows the leakage current of the waveform

Figure11-shows the magnitude of the circuit

Figure 12-shows the phase noise of the circuit

Figure 13-shows the power consumption of the circuit

Figure 14-shows the input output waveform

Table 1 Simulation results of parameters

Parameter Process technology Power supply Transistor count Dc gain(db) Group delay(GHz) Input noise(Hz) Output noise(Hz) Leakage current(pa) Magnitude(mv) Phase noise(Hz) Power consumption(ns) Simulated Results 45nm 1.8v 14 90 1.19 40 39.65 166 56 39.58 15.37

6. Conclusion-

A new design scheme for CMOS folded cascode transconduction operational amplifier using the MTCMOS technique is proposed. By help of this technique is achieved input noise (40 Hz) and output noise (39.65 Hz). Phase noise (39.58 Hz) effect is also reduced in proposed folded cascode OTA. Table 1 shows the simulation results of the parameters of the proposed circuits. This technique is also capable to best PSRR; the achieved PSRR is 125 db. Magnitude (56mv) of this circuit is achieved by help of this technique .The designed folded cascode OTA is applicable in systems requiring the efficient operation with very low power consumption (15.37ns). 7. References[1] [2] Soni H, Dhavse N, Design of OTA using 0.35 m technology. International journal of widsom based computing vol1, 28-31, and 2011. Raghuwar sharan gautam, P.K. Jain, D.S. ajnar Design of low voltage folded cascode operational transconductance amplifier with optimum range of gain GBW in 0.18 m technology. International journal of engineering research and applications (IJERA) vol 2, issue 1, 566-570, 2012. Tien-yu lo and chang-chih hung, A wide tuning range Gm-C continuous time analog filter. IEEE transaction circuit systems 1, vol 54,713-722, 2007. Stainslaw Szc zepanski, Bogdan Pankiewcz, Slawomir Koziel. Programmable feed forward linearized Cmos OTA for fully differential continuous-time filter design. International journal of circuit theory and design, 2009. Antonio J, Lopoz-Martin, Jaime Ramirez-angulo,Chandrika durbha, Ramon Gonzalez carvajal, A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion. IEEE journal of solid-state circuits, vol 40, 10781083, 2005. Swati Kundra, Priyanka soni, Rohaila Naaz, Folded cascode OTA using self casecode technique.International journal of scientific and research publication, vol 2, 2012. E Sanchez, Sineneio, Low voltage analog circuit design techniques. IEEE Dallas CAS workshop, 2000. S.S.Rajput, S.S. Jamuar, Design techniques for low voltage analog circuit structures. IEEE, Malasiya, 2001. M. Kumar, Design of fully differential operational amplifier with high gain, large bandwidth and large dynamic range. Thesis, 81 pages, 2009. Shweta karnik, Ajay Kumar kushwaha, Pramod Kumar Jain, D.S. Ajnar, Design of operational transconductance amplifier in 0.18 m technology. International journal of modern engg. Research (IJMER), vol 2, and 2249-6645. Swati kundra, Priyanka soni, Anshul kundra, Low power folded cascode OTA. International journal of VLSI design and communication systems (VLSICS), Vol.3, 2013. C.Su, B.J. blalock, S.K. Jslam, L.Zuo, L.M.Tolbert. A high temperature folded cascade OTA is 0.8 m BCD-on-SOI 2009.

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