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This document discusses digital integrated circuits including content-addressable memories (CAMs), read-only memories (ROMs), and programmable logic arrays (PLAs). CAMs extend ordinary memory to allow matching of stored data to search keys. ROMs are non-volatile memories that store data using the presence or absence of transistors. PLAs implement logic functions using a sum-of-products approach with AND and OR planes.

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94 views29 pages

Lec14 PDF

This document discusses digital integrated circuits including content-addressable memories (CAMs), read-only memories (ROMs), and programmable logic arrays (PLAs). CAMs extend ordinary memory to allow matching of stored data to search keys. ROMs are non-volatile memories that store data using the presence or absence of transistors. PLAs implement logic functions using a sum-of-products approach with AND and OR planes.

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Kavicharan Mummaneni
Copyright
© Attribution Non-Commercial (BY-NC)
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Digital Integrated Circuits Lecture 14: CAMs, ROMs, and PLAs

Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University [email protected]

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Outline

Content-Addressable Memories Read-Only Memories Programmable Logic Arrays

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CAMs

Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key
adr data/key

read CAM write match

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10T CAM Cell

Add four match transistors to 6T SRAM 56 x 43 unit cell


bit word bit_b

cell

cell_b

match

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CAM Cell Operation


Read and write like ordinary SRAM For matching:


address row decoder

CAM cell clk


weak

miss match0 match1 match2 match3

Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate
read/write

column circuitry data

Miss line

Pseudo-nMOS NOR of match lines Goes high if no words match


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Read-Only Memories

Read-Only Memories are nonvolatile

Retain their contents when power is removed Presence or absence determines 1 or 0

Mask-programmed ROMs use one transistor per bit

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ROM Example

4-word x 6-bit ROM


Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010

Represented with dot diagram Dots indicate 1s in ROM


A1 A0 weak pseudo-nMOS pullups

2:4 DEC

ROM Array

Y5

Y4

Y3

Y2

Y1

Y0

Looks like 6 4-input pseudo-nMOS NORs


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ROM Array Layout

Unit cell is 12 x 8 (about 1/10 size of SRAM)

Unit Cell

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Row Decoders

ROM row decoders must pitch-match with ROM

Only a single track per word!

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Complete ROM Layout

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PROMs and EPROMs

Programmable ROMs

Build array with transistors at every site Burn out fuses to disable unwanted transistors Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash
Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO2) n+ p n+ bulk Si

Electrically Programmable ROMs


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Building Logic with ROMs

Use ROM as lookup table containing truth table


n inputs, k outputs requires __ words x __ bits Changing function is easy reprogram ROM n inputs, k outputs, s bits of state Build with ________ bit ROM and ____ bit reg
inputs n 2n wordlines ROM Array

Finite State Machine


inputs n ROM k s state


k outputs

outputs k s

DEC

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Building Logic with ROMs

Use ROM as lookup table containing truth table


n inputs, k outputs requires 2n words x k bits Changing function is easy reprogram ROM n inputs, k outputs, s bits of state Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
inputs n 2n wordlines ROM Array

Finite State Machine


inputs n ROM k s state


k outputs

outputs k s

DEC

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Example: RoboAnt
Lets build an Ant Sensors: Antennae (L,R) 1 when in contact Actuators: Legs Forward step F Ten degree turns TL, TR Goal:

make our ant smart enough to get out of a maze

Strategy: keep right antenna on wall (RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman)
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Lost in space

Action: go forward until we hit something Initial state

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Bonk!!!

Action: turn left (rotate counterclockwise) Until we dont touch anymore

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A little to the right

Action: step forward and turn right a little Looking for wall

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Then a little to the left

Action: step and turn left a little, until not touching

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Whoops a corner!

Action: step and turn right until hitting next wall

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Simplification

Merge equivalent states where possible

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State Transition Table


S1:0 00 00 00 01 01 01 10 10 11 11 11 L 0 1 0 1 0 0 X X 1 0 0 R 0 X 1 X 1 0 0 1 X 0 1 S1:0 00 01 01 01 01 10 10 11 01 10 11 TR 0 0 0 0 0 0 1 1 0 0 0 TL 0 0 0 1 1 1 0 0 1 1 1 F 1 1 1 0 0 0 1 1 1 1 1

Lost

RCCW Wall1 Wall2

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ROM Implementation

16-word x 5 bit ROM


S1 S0 L R 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

L, R

ROM S'1:0 S1:0

TL, TR, F

4:16 DEC

S1' S0' TR'TL' F'

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ROM Implementation

16-word x 5 bit ROM


S1 S0 L R 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

L, R

ROM S'1:0 S1:0

TL, TR, F

4:16 DEC

S1' S0' TR'TL' F'

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PLAs

A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms bc
AND Plane OR Plane

Example: Full Adder

s = abc + abc + abc + abc cout = ab + bc + ac


a b
Inputs

ac ab abc abc abc abc

Minterms

s
Outputs

cout

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NOR-NOR PLAs

ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient Use DeMorgans Law to convert to all NORs
AND Plane OR Plane AND Plane OR Plane

bc

bc

ac ab abc abc abc abc

ac ab abc abc abc abc

c s cout

c s cout

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PLA Schematic & Layout


AND Plane OR Plane

bc ac ab abc abc abc

abc

c
s

cout

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PLAs vs. ROMs


The OR plane of the PLA is like the ROM array The AND plane of the PLA is like the ROM decoder PLAs are more flexible than ROMs

No need to have 2n rows for n inputs Only generate the minterms that are needed Take advantage of logic simplification

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Example: RoboAnt PLA

Convert state transition table to logic equations


S1:0 00 00 00 01 01 01 10 10 11 11 11 L 0 1 0 1 0 0 X X 1 0 0 R 0 X 1 X 1 0 0 1 X 0 1 S1:0 00 01 01 01 01 10 10 11 01 10 11 TR 0 0 0 0 0 0 1 1 0 0 0 TL 0 0 0 1 1 1 0 0 1 1 1 F 1 1 1 0 0 0 1 1 1 1 1

TR = S1 S0 TL = S0 F = S1 + S0
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RoboAnt Dot Diagram


AND Plane OR Plane

S1' = S1 S0 + LS1 + LRS0 S 0' = R + LS1 + LS0 TR = S1 S0 TL = S0 F = S1 + S0


S0 S1 S0 LS0 LS1 R LRS 0 LS1 S1 S 0

S1

S0

R S1 ' S0 ' TR TL F

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