Scribd Logo
Upload

Welcome to Scribd!

  • 42 views

    Lab Tutorial

    Uploaded by

    ahmedshah512
    This document provides instructions for completing Lab 1, which involves designing an AND gate in Verilog using the MAX+PLUS II software. Students are instructed to: 1) Open a new project called "andgate" in MAX+PLUS II. 2) Input the Verilog code for an AND gate into a text editor. 3) Save the Verilog file as "andgate.v" and compile the code using the functional SNF extractor. 4) Simulate the design by setting input signals a and b manually and checking the output matches the AND truth table.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Lab Tutorial

    Uploaded by

    ahmedshah512
    42 views9 pages
    This document provides instructions for completing Lab 1, which involves designing an AND gate in Verilog using the MAX+PLUS II software. Students are instructed to: 1) Open a new project called "andgate" in MAX+PLUS II. 2) Input the Verilog code for an AND gate into a text editor. 3) Save the Verilog file as "andgate.v" and compile the code using the functional SNF extractor. 4) Simulate the design by setting input signals a and b manually and checking the output matches the AND truth table.

    Original Description:

    ece lab tutorial

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document provides instructions for completing Lab 1, which involves designing an AND gate in Verilog using the MAX+PLUS II software. Students are instructed to: 1) Open a new project called "andgate" in MAX+PLUS II. 2) Input the Verilog code for an AND gate into a text editor. 3) Save the Verilog file as "andgate.v" and compile the code using the functional SNF extractor. 4) Simulate the design by setting input signals a and b manually and checking the output matches the AND truth table.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views9 pages

    Lab Tutorial

    Uploaded by

    ahmedshah512
    This document provides instructions for completing Lab 1, which involves designing an AND gate in Verilog using the MAX+PLUS II software. Students are instructed to: 1) Open a new project called "andgate" in MAX+PLUS II. 2) Input the Verilog code for an AND gate into a text editor. 3) Save the Verilog file as "andgate.v" and compile the code using the functional SNF extractor. 4) Simulate the design by setting input signals a and b manually and checking the output matches the AND truth table.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 9

    ECE 274 Tutorial for Lab1

    This Course will use MAX+PLUS II software for Verilog design. In the first lab, please generate a AND gate step by step follow the following instructions: 1: Open the MAX+PLUS II software and generate a new project choose File Project to generate project andgate

    2: Open the text editor and input the Verilog code for AND gate: module andgate(a,b,c); input a, b; output c; reg c; always @(a or b) begin c = a & b; end endmodule andgate takes three arguments: two of them are inputs and the third is the output, which is specified in the header of the module. ~ operator negates the input . & operator ANDs two inputs , | operator ORs two inputs, while ^ operator performs a logical XOR on two inputs. Hence, ~ (a | b) implements a NOR function where a and b are taken to be two inputs. Verilog uses C-style comments. // marks the beginning of a line of comments. Moreover, anything between /* and */ is also treated as a comment. always is a statement that lets you define blocks of code, in which assignments will only happen as selected signals (specified in the header of the statement) change.

    For example: input a, d reg out always @(a or d) begin out = d; end sets out to d only if the value of a or the value of d changes. Notice a slightly different syntax (were using the word or as opposed to the symbol |, and = instead of assign). Notice that all signals on the left-hand side of the = sign inside always blocks must be declared as reg, not wire. If you need to perform more than one operation under the always block, you need to enclose the operations with begin and end. always is most often combined with if (and possibly else if and else) to create powerful sequential logic systems. Study the following example: always @(a) begin if (a==2b01) begin b = 2b01; end else if (a>2b01) begin b = a; c = 1; end end

    3. Save the Verilog code as .v file. Please pay attention here; the file name must be the same as the module name. So this will be saved as andgate.v

    4. Use the compiler to compile the code:

    Choose Processing Functional SNF Extractor

    Click Start to run the compiler.

    The compiler will show there are no errors if the code is OK. 5. Simulation First, choose the Waveform Editor.

    Then choose node and select Enter Nodes From SNF

    Click list.

    Click >> button. All the input and output pins will be showed in the window selected nodes & groups.

    Save as andgate.scf

    Change the input signals a and b manually to a=0, b=0, a=0, b=1, a=1, b=0, a=1, b=1, 20 ns a period.

    Choose Simulator

    Set end time to 100ns and click start,

    Check the result waveform with the and truth table. And show the result to TA.

    By doing the design of andgate you will become familiar with the software and Verilog language. Please design the OR and Inverter gate using Verilog by yourself. Compile the code and check the waveform. Show the result to TA.

    You might also like