Power Integrity
Power Integrity
Agenda
PI Fundamentals (What is it and Why do we care. ) Pre R oute IR A nalysis Pre R oute A C Post R oute IR V erif ication Post R oute A C A nalysis V erif ication
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S i m u l t aneo u s S w i t c h i ng N o i s e (S S N )
N oise caused b y sev eral driv ers switching at the same time
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S i m u l t aneo u s S w i t c h i ng N o i s e (S S N )
1 B it 5 B i ts 2 2 B i ts
T hi s i s the no i se g enerated w hen al l the bi t are ru nni ng w i th the sam e pattern M o re bi ts sw i tchi ng - > H i g her no i se l ev el s
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S S N E y e D i agr am : 2 2 B i t S w i t c h i ng
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S S N E y e D i agr am : 1 1 2 B i t S w i t c h i ng
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W h at i s P o w er I nt egr i t y ?
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P o w er S y s t em
D es i gn
V R M
B u l k C aps
C eram i c C aps PC B
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W h at ar e w e m i s s i ng?
PC B V R M Pl ane C ap
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W h at ar e w e m i s s i ng?
LVIA RVIA
LPlane RPlaneCPlane
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Pre Route I R A n a ly s is
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E x am p l e f o r p r e- r o u t e I R anal y s i s
T his system consists of a ceramic B G A with 2 30 0 Pins C ore current of 30 amp s, 1 .2 V olts, 6 0 p ins S tack up is 1 2 0 mills thick M in V ia siz e is 2 2 rd8 ,
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H o w m u c h c u r r ent c an a 2 2 r d8 V i a h andl e ?
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H o w m u c h c u r r ent c an a 2 2 r d8 V i a h andl e ?
We have 30 amps/60 pins - > 0. 5 amps per pin Whic h is ~ 3mV d r o p ( b o t h G N D + P WR )
U sing t he I P C 2 2 2 1 c har t w it h 1 0 D eg C r ise t he c u r r ent mu st b e l ess t han 0. 7 5 A mps 0. 5 amps < 0. 7 5 amps
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W h i c h l ay er s h o u l d b e u s ed f o r t h e p l ane?
We hav e ~ 3mV of drop f rom the top of the stack up to the b ottom T his is 0 .2 5 % way would hav e ~ of this drop of the 1 .2 V sup p ly
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H o w
A ssu me
m u c h c u r r ent c an a t r ac e c ar r y ?
o z C u ( ~ 0. 7 mil l s t hic k )
- > 1 . 7 w it h 1 8 mV d r o p/in
ht t p : / / c ir c u it c a l c u l a t or . c om / w or d p r e s s / ? s = v ia + c u r r e nt + c a l c
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W h at w ei gh t C u s h o u l d b e u s ed , , 1 , 2 ?
A ssu me 2 o z C u ( ~ 2 . 8 mil s t hic k ) H o w w id e w o u l d my t r ac e need t o b e t o c ar r y t he 30 A mps? I nt er nal Wid t h - > 1 . 08 w it h 7 mV d r o p/in E x t er nal d r o p/in
- > 4 1 7 mil s w it h 1 8 mV
ht t p : / / c ir c u it c a l c u l a t or . c om / w or d p r e s s / ? s = v ia + c u r r e nt + c a l c
P resenta tion_ ID 2006 Cisco Systems, Inc. All rights reserved. Cisco Conf identia l
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H o w
m u c h dr o p i s o k ?
A ssume the allowab le v oltag e v ariation at the B G A is + / -2 .5 % We can allocate + / -1 .0 % Which leav es + / -1 .5 % 1 % = 1 2 mV total to A C to IR drop N oise
We hav e 3 mV f or the V ias, and 7 mV with the 2 oz Internal 1 inch f eed trace Is this too close? H ow can we imp rov e this ?
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P o s t r o u t e t o o l s f o r I R anal y s i s
S ig rity Power D C C adence IR
www.cadence.c o m / http://www.sigrity.com/products/powerdc/powerdc.htm
http://www.a pa che-da .com/a pa cheda /H ome/P roductsa n dS ol ution s/S ystemP owerN oiseR el ia b il ity/S en tin el -P I .html
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T h e p o s t r o u t e I R p r o c es s (S i gr i t y P o w er D C )
T ranslate the p ost route desig n D ef ine the sources (V R M and connectors)
D ef ine the current sink f or loads, and sp ec the distrib ution of these if p ossib le M ak e sure the stack up C u thick ness matches S et the ap p rop riate limits f or the simulation Full p ost route f or IR drop
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P o s t R o u teIR
V er i f i c at i o n
D id we f all b elow the p re-route C u width recommendations? D oes the V R M H ow much current can the v ias handle?
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VRM S e n s e p o in t
neck do w n
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2 3 m V
V R M S e ns e p oint c l os e t o V R M ou t p u t
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T hi s i s 0 .0 6 % 1 .2 V su ppl y
T he f eedback l o cati o n cau sed the V R M to i ncreased v o l tag e by 2 3 m V to co m pensate f o r the D C L o ss o f the PD S. o f the
V ol t a ge inc r e a s e d a t V R M ou t p u t b y 3 5 m V
VRM S e n s e p o in t c lo s e to B G A
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T he Po st ro u te si m u l ati o ns sho w that these v i as hav e as m u ch as 4 .8 am ps. T hi s w o u l d cau se a l arg e tem p ri se f o r the v i as.
D C
cu rrent >3 A
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W here (t) i s the m ateri al resi sti v i ty L l eng th o f the co ndu cto r A i s the cro ss secti o nal area.
T o m in im iz e I R d r op , r ed u c e D C r esist a n c e.
For example: 1 0 x1 0 s q u are
5 0 %
r ed u c t ion in I R
d r op w it h 2 oz ov er 1 oz
W h a t w ou l d t h e r esist a n c e of a 1 x 1 sq u a r e b e?
P resenta tion_ ID 2006 Cisco Systems, Inc. All rights reserved. Cisco Conf identia l
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V p1 p0
IR
d rop w ith 1 oz C u
V p 1 p 0 , L a y e r _ P 2 1 ,
90mV I R
d r o p
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V p1 p0
IR
d rop w ith 2 oz C u
V p 1 p 0 , L a y e r _ P 2 1 ,
4 5 mV I R
d r o p
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area h elp
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V p 1 p 0
I R dr o p w i t h 1 O z C u
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S m al l er Ant i P ad r es u l t s
I R dro p = 1 .0 0 .8 9 3 = 1 0 7 m V
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L ar ger Ant i P ad r es u l t s
I R dro p = 1 .0 0 .8 8 3 = 1 1 7 m V
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P o s t r o u t e w i t h t h e AS I C p ac k age
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P os t rout e c urren t d en s i t y w i t h t h e A S I C pa c k a g e a n d P C B
4 2
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Pre Route A C A n a ly s is
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P r e R o u t e AC
Anal y s i s
H ow much Inductance does a X mil trace hav e? H ow much Inductance does a 2 2 rd8 V ia hav e ? Which layer should the C ap s b e mounted on? Which layer should the p lane b e p oured on?
D ef ining the PD S targ et imp edance v s f req uency What cap s meet the p re-route req uirements? S p ice S imulation
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H o w m u c h I ndu c t anc e do es a 2 2 r d8 V i a h av e?
s
W he r e h is t he he ight of v ia s is t he s e p a r a t ion of t he v ia s r is t he r a d iu s of t he v ia hol e s . .
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H o w m u c h I ndu c t anc e do es a X m i l u S t r i p t r ac e h av e?
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W h i c h l ay er s h o u l d t h e C ap s b e m o u nt ed o n?
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C er am i c D ec o u p l i ng C ap ac i t o r s
I d e a l
Re a l i t y Cc Rc E S R
Lc
E S L
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D ec o u p l i ng C ap ac i t o r s E f f ec t o f E S L
Impedance plot
1.000E+ 00
PCB 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1
1.000E-01
(n o n e ) (n o n e ) (n o n e ) (n o n e )
1.000E-02
T o ta l T a rg e t Pl a n e R e s
1.000E-03
1.000E-04 1.00E+ 03
1.00E+ 04
1.00E+ 05
1.00E+ 06
1.00E+ 07
1.00E+ 08
1.00E+ 09
1.00E+ 10
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D ec o u p l i ng C ap ac i t o r s E f f ec t o f E S R
Impedance plot
1.000E+ 00
PCB 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 1 1 -2 3 3 0 -0 1 (n o n e )
1.000E-01
(n o n e ) (n o n e ) (n o n e ) T o ta l
1.000E-02
T a rg e t Pl a n e R e s
1.000E-03
1.000E-04 1.00E+ 03
1.00E+ 04
1.00E+ 05
1.00E+ 06
1.00E+ 07
1.00E+ 08
1.00E+ 09
1.00E+ 10
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D ec oupl i n g C a pa c i t or M oun t i n g
LMounting _ loop = LPad + LTrace + LVia1 + LVia 2 Lmutual RMounting _ loop = RPad + RTrace + RVia
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W h i c h l ay er s h o u l d t h e C ap s b e m o u nt ed o n?
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W h i c h l ay er s h o u l d t h e C ap s b e m o u nt ed o n?
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Addi ng a 1 u F 0 4 0 2 t o t h e P l o t
E SR = 0 .1 0 9 O hm s, E SL = 0 .7 nH
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Addi ng a 4 7 0 u F S M , 2 8 1 6 t o t h e P l o t
E SR = 0 .0 1 8 , E SL = 2 .2 nH
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E x am p l es o f c ap ac i t o r m o u nt i ng
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W h i c h l ay er s h o u l d t h e p l ane b e p o u r ed o n?
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M o u nt i ng L / R f o r o u r 6 0 p i n C o r e
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F r eq u enc y do m ai n v i ew
o f o u r m o u nt i ng L / R
D o g B o n e ( ~ 2 5 + 2 5 mi l s )
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F r eq u enc y do m ai n v i ew
Vi a i n P a d
o f o u r m o u nt i ng L / R
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W h at i s t h e P C B T ar get I m p edanc e ?
ZT arg et dV Allowable _ Voltage _ delta = = dI Current _ step
PD S imp edance b elow a T arg et imp edance Power noise rip p le v oltag e to min B asically f lat v s Freq uency Z targ et = 2 .4 m O hms
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E x am p l e o f I O
D r i v er S w i t c h i ng C u r r ent
Dr iv e r ou t p u t v ol t a ge Dr iv e r ou t p u t c u r r e nt
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T ar get I m p edanc e r el ax at i o n
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R el ax ed t ar get i m p edanc e
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P r e-r o u t e c ap ac i t o r s el ec t i o n
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P r e-r o u t e c ap ac i t o r s el ec t i o n
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Addi ng t h e m o u nt i ng L / R
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2 0 1 5 1 0 5 0 -1 0 3 0 2 0 1 0 0 -2 0
2 0 1 5 1 0 5
1 0
2 0
0 -2 0 1 5 1 0 5 0 -2 0
-1 0
1 0
Rising Edge [C K]
F a l l ing Edge [C K]
-1 0
1 0
2 0
-1 0
1 0
2 0
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Post Route AC V er i f i c a ti on
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P o s t r o u t e AC p o w er i nt egr i t y
Power-S I
p r o c es s
A l l eg ro
S-P a r a m
e te r
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O u r p o s t r o u t e AC P I p r o c es s
T ranslate the p ost route D esig n (B R D C reate sp ice models f or cap s (.cir) to S PD )
D ef ine the p orts f or s-p arameter ex traction (V R M , IC ..) M ak e sure the stack up C u thick ness matches Full Post route A C ex traction S et the ap p rop riate f req uency limits f or the simulation
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P o s t R o u t e S i m u l at i o n
Sp i c e S-P a r a m e te r
V R M
PC B
S-P a r a m
e t e r
PK G
D i e, w i th si nk
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P o s t r o u t e ex am p l es
Example 1: Example 2 : Example 3 : H o w lay er s elec t i o n c an ef f ec t y o u r d es i g n . b y ad d i n g v i as t o t h e d es i g n .
L o w er i n g B G A mo u n t ed L / R
Exc i t at i o n o f a po w er s y s t em r es o n an c e.
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E x am p l e 1 : H o w l ay er s el ec t i o n c an ef f ec t y o u r des i gn.
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M o u nt i ng ef f ec t s f o r L ay er 2 7
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Example 1:
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M o u nt i ng ef f ec t s f o r L ay er 2
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F r eq u enc y do m ai n c o m p ar i s o n
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T r ans i ent C o m p ar i s o n o f M o u nt i ng L ay er
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M o u nt i ng ef f ec t s (2 x V i as f o r L ay er 2 7 )
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M o u nt i ng ef f ec t s (2 x V i as f o r L ay er 2 7 )
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T r ans i ent C o m p ar i s o n o f M o u nt i ng L ay er
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E x am p l e 3 : E x c i t at i o n o f a p o w er s y s t em
r es o nanc e.
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E x c i t i ng a P D S s y s t em
R es o nanc e
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E x c i t i ng a P D S s y s t em
R es o nanc e
V R M
PC B
PK G
1 0 M H z V S 3 6 M H z t r ia ngu l a r w a v e 1 0 A
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Example 3 :
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S u m m ar y
PI Fundamentals (What is it and Why do we care. ) Pre R oute IR A nalysis Pre R oute A C Post R oute IR V erif ication Post R oute A C A nalysis V erif ication
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D r B o b E v a n s , N C S U C l a s s N o t e s , 2 0 0 3 . H .W . J o h n s o n a n d M . G r a h a m , H i g h S p e e d D i g i t a l D e s ig n , A h a n d b o o k o f b la c k m a g ic , P re n tic e H a ll, I S B N 0 -1 3 -3 9 5 7 2 4 -1 , 1 9 9 3 R .K . P o o n , C o m p u t e r C i r c u i t s E l e c t r i c a l D e s i g n , 1 9 9 4 , P re n tic e H a ll. D .B ro o k s , M a in ta in in g C le a n P o w e r , U ltra C a d W e b s i t e w w w .u l t r a c a d .c o m , 1 9 9 5 . D .B r o o k s , B y p a s s C a p a c ito r s , P r in te d C ir c u it M a g a z i n e , U l t r a C a d W e b s i t e w w w .u l t r a c a d .c o m , M a r c h 1 9 9 8 . I PC -2 1 5 2 : Standard f o r D eterm i ni ng C u rrent C arryi ng C apaci ty i n Pri nted B o ard D esi g n N ew C o rrel ati o ns betw een E l ectri cal C u rrent and T em peratu re R i se i n PC B T races by J o hannes A dam ( F l o m eri cs L td.)
P resenta tion_ ID 2006 Cisco Systems, Inc. All rights reserved. Cisco Conf identia l
R e fe r e n c e s
89
L .D . S m i t h , P o w e r D i s t r i b u t i o n S y s t e m D e s i g n M e t h o d o l o g y a n d C a p a c ito r S e le c tio n fo r M o d e rn C M O S T e c h n o lo g y , IE E E T r a n s a c tio n s o n A d v a n c e d P a c k a g in g , V o l.2 2 , N o .3 , A u g 1 9 9 9 . L .D . S m i t h , P o w e r D i s t r i b u t i o n N e t w o r k s f o r N e x t G e n e r a t i o n S y s te m s , E P E P C o n fe re n c e S h o rt C o u rs e , O c t.2 0 0 0 . L .D . S m i t h , P o w e r P l a n e S p i c e M o d e l s f o r F r e q u e n c y a n d T im e D o m a in s , E P E P C o n f e r e n c e O c t.2 0 0 0 . Is tv a n N o v a k , R e d u c in g S im u lta n e o u s S w itc h in g N o is e a n d E M I o n G ro u n d /P o w e r P la n e s b y D is s ip a tiv e E d g e T e rm in a tio n S U N M i c r o s y s t e m s , I n c ., E P E P C o n f e r e n c e O c t . 1 9 9 8 . P A R A S I T I C I N D U C T A N C E O F M U L T I L A Y E R C E R A M I C C A P A C I T O R S , b y J e ffr e y C a in , P h .D . A V X C o r p o r a tio n C u r r e n t C a r r y i n g C a p a c i t y o f V i a s b y Doug Brooks and Dav e G rav e s
R e fe r e n c e s
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