Mc68hc908jl3/jk3e/jk1e Mc68hrc908jl3/jk3e/jk1e Mc68hlc908jl3/jk3e/jk1e Mc68hc903kl3e/kk3e Mc68hc08jl3e/jk3e Mc68hrc08jl3e/jk3e

MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC903KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E
Data Sheet
M68HC08 Microcontrollers
MC68HC908JL3E Rev. 4 10/2006
freescale.com
MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC908KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E

Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash technology licensed from SST. Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 3
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision Level Description Table 4-1. Instruction Set Summary Updated table to include the WAIT instruction. 5.7.1 Break Status Register (BSR) Updated for clarity. 5.7.2 Reset Status Register (RSR) Updated description for clarity. 7.4 Security Updated to reflect the correct RAM location ($80) to determine if the security code has been entered correctly. October 2006 4 8.9.1 TIM Status and Control Register (TSC) Added note to definition of TSTOP bit. 10.1 Introduction Added note regarding 20-pin devices. 15.4.3 Break Status Register Updated for clarity. Chapter 17 Mechanical Specifications Updated package drawings to the latest available. Added appendix B for ROM parts. Nov 2004 3 Added appendix C for ADC-less parts. Added appendix A for low-volt devices. Dec 2002 2 Updated Monitor Mode Circuit (Figure 7-1) and Monitor Mode Entry Requirements and Options (Table 7-1) in Monitor ROM section. First general release. 167170 153224 76, 77 89 103 132 147 159166 Page Number(s) 42 63 64 80
May 2002
MC68HC908JL3E Family Data Sheet, Rev. 4 4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Configuration Registers (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 5 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 6 Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Chapter 9 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Chapter 10 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 11 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Chapter 12 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 13 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 14 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Chapter 15 Break Module (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Chapter 17 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chapter 18 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Appendix A MC68HLC908JL3E/JK3E/JK1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Appendix B MC68H(R)C08JL3E/JK3E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Appendix C MC68HC908KL3E/KK3E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 5
List of Chapters
Table of Contents
Chapter 1 General Description
1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 17 18 20
Chapter 2 Memory
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 27 28 28 29 30 30 31 31 33
Chapter 3 Configuration Registers (CONFIG)

3.1 3.2 3.3 3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 36
Chapter 4 Central Processor Unit (CPU)

4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37 37 37 38 38 39
Table of Contents
4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 40 41 41 41 41 41 42 47
Chapter 5 System Integration Module (SIM)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49 51 51 51 51 52 52 52 53 54 54 54 55 55 55 55 55 55 55 57 58 58 59 59 60 60 60 60 61 61 62 63 63 64 65
Chapter 6 Oscillator (OSC)

6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 6.5.1 6.5.2 6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-tal Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 67 69 69 69 69 69 69 69 69 70 70 70 70
Chapter 7 Monitor ROM (MON)

7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 73 75 76 76 76 77 79
Chapter 8 Timer Interface Module (TIM)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81 81 81 82 84 84 84 84 84 85 86 86 87
Table of Contents
8.5 8.6 8.6.1 8.6.2 8.7 8.8 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Status and Control Registers (TSC0:TSC1). . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88 88 88 88 88 89 89 89 91 91 92 95
Chapter 9 Analog-to-Digital Converter (ADC)

9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.4 9.5 9.5.1 9.5.2 9.6 9.6.1 9.7 9.7.1 9.7.2 9.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 10 Input/Output (I/O) Ports

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 105 105 106 107 108 108 108
10.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110 110 111 112
Chapter 11 External Interrupt (IRQ)

11.1 11.2 11.3 11.3.1 11.4 11.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 113 113 115 115 116
Chapter 12 Keyboard Interrupt Module (KBI)

12.1 12.2 12.3 12.4 12.4.1 12.5 12.5.1 12.5.2 12.6 12.6.1 12.6.2 12.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 117 118 119 119 120 121 121 121 121 121
Chapter 13 Computer Operating Properly (COP)

13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.4 13.5 13.6 13.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 123 124 124 124 124 124 124 124 125 125 125 125 125
Table of Contents
13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Chapter 14 Low Voltage Inhibit (LVI)

14.1 14.2 14.3 14.4 14.5 14.5.1 14.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 127 127 128 128 128 128
Chapter 15 Break Module (BREAK)

15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.5 15.5.1 15.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 129 129 130 130 130 130 131 131 132 132 133 133 133 133
Chapter 16 Electrical Specifications

16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135 135 136 136 137 138 139 140 141 142 143
16.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 16.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 17 Mechanical Specifications

17.1 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 18 Ordering Information

18.1 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Appendix A MC68HLC908JL3E/JK3E/JK1E
A.1 A.2 A.3 A.4 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.5.5 A.5.6 A.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 159 159 159 159 159 160 161 161 162 163 164
Appendix B MC68H(R)C08JL3E/JK3E
B.1 B.2 B.3 B.4 B.5 B.5.1 B.5.2 B.5.3 B.6 B.7 B.7.1 B.7.2 B.7.3 B.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 165 167 168 168 168 168 169 169 170 170 171 172 173
Table of Contents
Appendix C MC68HC908KL3E/KK3E
C.1 C.2 C.3 C.4 C.5 C.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 175 175 178 178 178
Chapter 1 General Description

1.1 Introduction
The MC68H(R)C908JL3E is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. A list of MC68H(R)C908JL3E device variations is shown in Table 1-1. Table 1-1. Summary of Device Variations
Device Type Operating Voltage LVI ADC Oscillator Option Memory Pin Count 28 4,096 bytes Flash XTAL 1,536 bytes Flash Flash 3V, 5V Yes Yes 28 4,096 bytes Flash RC 1,536 bytes Flash 4,096 bytes Flash 2.2 to 5.5V No Yes XTAL 1,536 bytes Flash XTAL 20 ROM(2) 3V, 5V Yes Yes RC 20 Flash, ADC-less(3) 28 3V, 5V Yes No XTAL 4,096 bytes Flash 20 MC68HC908KK3E MC68HRC08JK3E MC68HC908KL3E 4,096 bytes ROM 28 MC68HRC08JL3E MC68HC08JK3E 20 20 28 MC68HLC908JK3E MC68HLC908JK1E MC68HC08JL3E 20 20 28 Low Voltage Flash(1) MC68HRC908JK3E MC68HRC908JK1E MC68HLC908JL3E MC68HRC908JL3E 20 20 MC68HC908JK3E MC68HC908JK1E Device MC68HC908JL3E
1. Low-voltage Flash devices are documented in Appendix A MC68HLC908JL3E/JK3E/JK1E. 2. ROM devices are documented in Appendix B MC68H(R)C08JL3E/JK3E. 3. Flash, ADC-less devices are documented in Appendix C MC68HC908KL3E/KK3E.
All references to the MC68H(R)C908JL3E in this data book apply equally to the MC68H(R)C908JK3E and MC68H(R)C908JK1E, unless otherwise stated.
General Description
1.2 Features
Features of the MC68H(R)C908JL3E include the following: EMC enhanced version of MC68H(R)C908JL3/JK3/JK1 High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families Low-power design; fully static with stop and wait modes Maximum internal bus frequency: 8-MHz at 5V operating voltage 4-MHz at 3V operating voltage Oscillator options: Crystal oscillator for MC68HC908JL3E/JK3E/JK1E RC oscillator for MC68HRC908JL3E/JK3E/JK1E User program Flash memory with security(1) feature 4,096 bytes for MC68H(R)C908JL3E/JK3E 1,536 bytes for MC68H(R)C908JK1E 128 bytes of on-chip RAM 2-channel, 16-bit timer interface module (TIM) 12-channel, 8-bit analog-to-digital converter (ADC) 23 general purpose I/O ports for MC68H(R)C908JL3E: 7 keyboard interrupt with internal pull-up (6 keyboard interrupt for MC68HC908JL3E) 10 LED drivers (sink) 2 25mA open-drain I/O with pull-up 15 general purpose I/O ports for MC68H(R)C908JK3E/JK1E: 1 keyboard interrupt with internal pull-up (MC68HRC908JK3E/JK1E only) 4 LED drivers (sink) 2 25mA open-drain I/O with pull-up 10-channel ADC System protection features: Optional computer operating properly (COP) reset Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation Illegal opcode detection with reset Illegal address detection with reset Master reset pin with internal pull-up and power-on reset IRQ with schmitt-trigger input and programmable pull-up 28-pin PDIP, 28-pin SOIC, and 48-pin LQFP packages for MC68H(R)C908JL3E 20-pin PDIP and 20-pin SOIC packages for MC68H(R)C908JK3E/JK1E
1. No security feature is absolutely secure. However, Freescales strategy is to make reading or copying the Flash difficult for unauthorized users. MC68HC908JL3E Family Data Sheet, Rev. 4 16 Freescale Semiconductor
MCU Block Diagram
1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68H(R)C908JL3E.
INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU)
KEYBOARD INTERRUPT MODULE PORTA DDRA
CONTROL AND STATUS REGISTERS 64 BYTES USER FLASH: MC68H(R)C908JK3E/JL3E 4,096 BYTES MC68H(R)C908JK1E 1,536 BYTES USER RAM 128 BYTES MONITOR ROM 960 BYTES USER FLASH VECTOR SPACE 48 BYTES MC68HC908JL3E/JK3E/JK1E X-TAL OSCILLATOR MC68HRC908JL3E/JK3E/JK1E RC OSCILLATOR POWER-ON RESET MODULE * RST SYSTEM INTEGRATION MODULE LOW-VOLTAGE INHIBIT MODULE * IRQ EXTERNAL INTERRUPT MODULE COMPUTER OPERATING PROPERLY MODULE BREAK MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE
PTA6/KBI6** PTA5/KBI5** PTA4/KBI4** PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 PTD7** PTD6** PTD5/TCH1 PTD4/TCH0 PTD3/ADC8 PTD2/ADC9 PTD1/ADC10 PTD0/ADC11
2-CHANNEL TIMER INTERFACE MODULE PORTB PORTD
OSC1
OSC2
DDRD
DDRB
VDD POWER VSS ADC REFERENCE
* Pin contains integrated pull-up device. ** Pin contains programmable pull-up device. 25mA open-drain if output pin. LED direct sink pin. # Pins available on MC68H(R)C908JL3E only. Shared pin: MC68HC908JL3E/JK3E/JK1E OSC2 MC68HRC908JL3E/JK3E/JK1E RCCLK/PTA6/KBI6
Figure 1-1. MCU Block Diagram
General Description
1.4 Pin Assignments

IRQ PTA0/KBI0 VSS OSC1 OSC2/RCCLK/PTA6/KBI PTA1/KBI1 VDD PTA2/KBI2 PTA3/KBI3 PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTD7 PTD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RST PTA5/KBI5 PTD4/TCH0 PTD5/TCH1 PTD2/ADC9 PTA4/KBI4 PTD3/ADC8 PTB0/ADC0 PTB1/ADC1 PTD1/ADC10 PTB2/ADC2 PTB3/ADC3 PTD0/ADC11 PTB4/ADC4
MC68H(R)C908JL3E
Figure 1-2. 28-Pin PDIP/SOIC Pin Assignment
IRQ VSS OSC1 OSC2/RCCLK/PTA6/KBI VDD PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTD7 PTD6
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RST PTD4/TCH0 PTD5/TCH1 PTD2/ADC9 PTD3/ADC8 PTB0/ADC0 PTB1/ADC1 PTB2/ADC2 PTB3/ADC3 PTB4/ADC4
Pins not available on 20-pin packages PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 Internal pads are unconnected. PTD0/ADC11 PTD1/ADC10
MC68H(R)C908JK3E/JK1E
Figure 1-3. 20-Pin PDIP/SOIC Pin Assignment
Pin Assignments PTD4/TCH0 PTD5/TCH1
PTA0/KBI0
PTA5/KBI5
RST
IRQ
VSS
NC
NC
NC 38
47
46
45
44
43
42
41
40
39
37 NC 36 NC 35 34 33 32 31 NC NC PTD2/ADC9 PTA4/KBI4 PTD3/ADC8 NC PTB0/ADC0 PTB1/ADC1 PTD1/ADC10 NC 25 NC NC 24 30 29 28 27 26
NC 1 NC OSC1 OSC2/RCCLK/PTA6/KBI6 PTA1/KBI1 NC VDD PTA2/KBI2 PTA3KBI3 PTB7/ADC7 NC NC 12 NC 13 2 3 4 5 6 MC68H(R)C908JL3E 7 8 9 10 11 20 21 22 PTB2/ADC2 14 15 16 17 18 19 23 NC
48 NC
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
NC: No connection
Figure 1-4. 48-Pin LQFP Pin Assignment
PTD0/ADC11
PTB3/ADC3
PTD7
PTD6
NC
General Description
1.5 Pin Functions

Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions
PIN NAME VDDJL3JL3 VSS RST Power supply. Power supply ground RESET input, active low. With Internal pull-up and Schmitt trigger input. External IRQ pin. With software programmable internal pull-up and schmitt trigger input. This pin is also used for mode entry selection. X-tal or RC oscillator input. MC68HC908JL3E/JK3E/JK1E: X-tal oscillator output, this is the inverting OSC1 signal. OSC2 MC68HRC908JL3E/JK3E/JK1E: Default is RC oscillator clock output, RCCLK. Shared with PTA6/KBI6, with programmable pull-up. 7-bit general purpose I/O port. Shared with 7 keyboard interrupts KBI[0:6]. PTA[0:6] Each pin has programmable internal pull-up device. PTA[0:5] have LED direct sink capability 8-bit general purpose I/O port. PTB[0:7] Shared with 8 ADC inputs, ADC[0:7]. 8-bit general purpose I/O port. PTD[3:0] shared with 4 ADC inputs, ADC[8:11]. PTD[0:7] PTD[4:5] shared with TIM channels, TCH0 and TCH1. PTD[2:3], PTD[6:7] have LED direct sink capability PTD[6:7] can be configured as 25mA open-drain output with pull-up. In In/Out Input In/Out In In/Out Analog VDD Analog VDD VSS VDD In In In/Out VDD VSS VDD PIN DESCRIPTION IN/OUT In Out Input VOLTAGE LEVEL 5V or 3V 0V VDD to VTST
IRQ
Input
VDD to VTST
OSC1
In Out
Analog Analog
In/Out In/Out In
VDD VDD VDD
NOTE On the MC68H(R)C908JK3E/JK1E, the following pins are not available: PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1.
Chapter 2 Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: 4,096 bytes of user Flash MC68H(R)C908JL3E/JK3E 1,536 bytes of user Flash MC68H(R)C908JK1E 128 bytes of RAM 48 bytes of user-defined vectors 960 bytes of Monitor ROM
2.2 I/O Section

Addresses $0000$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: $FE00; Break Status Register, BSR $FE01; Reset Status Register, RSR $FE03; Break Flag Control Register, BFCR $FE04; Interrupt Status Register 1, INT1 $FE05; Interrupt Status Register 2, INT2 $FE06; Interrupt Status Register 3, INT3 $FE08; Flash Control Register, FLCR $FE09; Flash Block Protect Register, FLBPR $FE0C; Break Address Register High, BRKH $FE0D; Break Address Register Low, BRKL $FE0E; Break Status and Control Register, BRKSCR $FFFF; COP Control Register, COPCTL
2.3 Monitor ROM

The 960 bytes at addresses $FC00$FDFF and $FE10$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).)
Memory
$0000 $003F $0040 $007F $0080 $00FF $0100 $EBFF $EC00 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCF $FFD0 $FFFF
I/O REGISTERS 64 BYTES RESERVED 64 BYTES RAM 128 BYTES UNIMPLEMENTED 60,160 BYTES
UNIMPLEMENTED 62,720 BYTES
$0100 $F5FF $F600 $FBFF
FLASH MEMORY MC68H(R)C908JL3E/JK3E 4,096 BYTES
FLASH MEMORY MC68H(R)C908JK1E 1,536 BYTES
MONITOR ROM 512 BYTES BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (RSR) RESERVED (UBAR) BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FLASH CONTROL REGISTER (FLCR) FLASH BLOCK PROTECT REGISTER (FLBPR) RESERVED RESERVED BREAK ADDRESS HIGH REGISTER (BRKH) BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) RESERVED MONITOR ROM 448 BYTES USER VECTORS 48 BYTES
Figure 2-1. Memory Map
Monitor ROM Addr. $0000 Register Name Read: Port A Data Register Write: (PTA) Reset: Read: $0001 Port B Data Register Write: (PTB) Reset: Read: $0002 Unimplemented Write: Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read: $0005 Data Direction Register B Write: (DDRB) Reset: Read: $0006 Unimplemented Write: Read: Data Direction Register D Write: (DDRD) Reset: Read: Unimplemented Write: Read: Port D Control Register Write: (PDCR) Reset: Read: Unimplemented Write: Read: Port A Input Pull-up Enable Write: Register (PTAPUE) Reset: Read: Unimplemented Write: = Unimplemented R = Reserved 0 0 0 0 0 0 0 0 Bit 7 0 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Unaffected by reset
$0003
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset 0 0 DDRB7 0 DDRA6 0 DDRB6 0 DDRA5 0 DDRB5 0 DDRA4 0 DDRB4 0 DDRA3 0 DDRB3 0 DDRA2 0 DDRB2 0 DDRA1 0 DDRB1 0 DDRA0 0 DDRB0 0
$0004
$0007
DDRD7 0
DDRD6 0
DDRD5 0
DDRD4 0
DDRD3 0
DDRD2 0
DDRD1 0
DDRD0 0
$0008 $0009
$000A
SLOWD7 0
SLOWD6 0
PTDPU7 0
PTDPU6 0
$000B $000C
$000D $000E $0019
PTA6EN 0
PTAPUE6 0
PTAPUE5 0
PTAPUE4 0
PTAPUE3 0
PTAPUE2 0
PTAPUE1 0
PTAPUE0 0
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 4)
Memory Addr. $001A Register Name Read: Keyboard Status and Control Write: Register (KBSCR) Reset: Read: Keyboard Interrupt Enable Write: Register (KBIER) Reset: Read: $001C Unimplemented Write: IRQ Status and Control Read: Register Write: (INTSCR) Reset: Read: $001E Configuration Register 2 Write: (CONFIG2) Reset: Read: Configuration Register 1 Write: (CONFIG1) Reset: 0 0 IRQPUD 0 COPRS 0 0 0 R 0 R 0 0 0 R 0 R 0 0 0 LVIT1 0* LVID 0 IRQF 0 LVIT0 0* R 0 0 ACK 0 R 0 SSREC 0 Bit 7 0 0 0 0 6 0 0 KBIE6 0 5 0 0 KBIE5 0 4 0 0 KBIE4 0 3 KEYF 0 KBIE3 0 2 0 ACKK 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
$001B
$001D
IMASK 0 R 0 STOP 0
MODE 0 R 0 COPD 0
$001F
One-time writable register after each reset. * LVIT1 and LVIT0 reset to 0 by a power-on reset (POR) only. Read: TIM Status and Control Write: Register (TSC) Reset: Read: TIM Counter Register High Write: (TCNTH) Reset: Read: $0022 TIM Counter Register Write: Low (TCNTL) Reset: Read: TIM Counter Modulo Register Write: High (TMODH) Reset: Read: $0024 TIM Counter Modulo Register Write: Low (TMODL) Reset: Read: TIM Channel 0 Status and Write: Control Register (TSC0) Reset: Read: $0026 TIM Channel 0 Register High Write: (TCH0H) Reset: TOF 0 0 Bit15 0 Bit7 0 Bit15 1 Bit7 1 CH0F 0 0 Bit15 0 TRST 0 Bit12 0 Bit4 0 Bit12 1 Bit4 1 MS0A 0 Bit12 0 Bit11 0 Bit3 0 Bit11 1 Bit3 1 ELS0B 0 Bit11 0
$0020
TOIE 0 Bit14 0 Bit6 0 Bit14 1 Bit6 1 CH0IE 0 Bit14
TSTOP 1 Bit13 0 Bit5 0 Bit13 1 Bit5 1 MS0B 0 Bit13
PS2 0 Bit10 0 Bit2 0 Bit10 1 Bit2 1 ELS0A 0 Bit10
PS1 0 Bit9 0 Bit1 0 Bit9 1 Bit1 1 TOV0 0 Bit9
PS0 0 Bit8 0 Bit0 0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
$0021
$0023
$0025
Indeterminate after reset = Unimplemented R = Reserved
Monitor ROM Addr. $0027 Register Name Read: TIM Channel 0 Register Low Write: (TCH0L) Reset: Read: TIM Channel 1 Status and Write: Control Register (TSC1) Reset: Read: $0029 TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset: Read: Unimplemented Write: Read: ADC Status and Control Write: Register (ADSCR) Reset: Read: $003D ADC Data Register Write: (ADR) Reset: Read: ADC Input Clock Register Write: (ADICLK) Reset: Read: $003F Unimplemented Write: ADIV2 0 ADIV1 0 ADIV0 0 COCO 0 AD7 Bit 7 Bit7 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0
Indeterminate after reset CH1F 0 0 Bit15 CH1IE 0 Bit14 0 0 Bit13 MS1A 0 Bit12 ELS1B 0 Bit11 ELS1A 0 Bit10 TOV1 0 Bit9 CH1MAX 0 Bit8
$0028
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$002A $002B $003B
Indeterminate after reset
$003C
AIEN 0 AD6
ADCO 0 AD5
ADCH4 1 AD4
ADCH3 1 AD3
ADCH2 1 AD2
ADCH1 1 AD1
ADCH0 1 AD0
Indeterminate after reset 0 0 0 0 0 0 0 0 0 0
$003E
$FE00
Read: Break Status Register Write: (BSR) Reset: Read: Reset Status Register Write: (RSR) POR: Read: Reserved Write: Read: Break Flag Control Write: Register (BFCR) Reset:
SBSW See note 0
Note: Writing a 0 clears SBSW. POR 1 R PIN 0 R COP 0 R ILOP 0 R ILAD 0 R MODRST 0 R LVI 0 R 0 0 R $FE01
$FE02
$FE03
BCFE 0
= Unimplemented
= Reserved

Memory Addr. $FE04 Register Name Read: Interrupt Status Register 1 Write: (INT1) Reset: Read: Interrupt Status Register 2 Write: (INT2) Reset: Read: $FE06 Interrupt Status Register 3 Write: (INT3) Reset: Read: $FE07 Reserved Write: Read: Flash Control Register Write: (FLCR) Reset: Read: Flash Block Protect Write: Register (FLBPR) Reset: Read: Reserved Write: Read: Break Address High Write: Register (BRKH) Reset: Read: $FE0D Break Address Low Write: Register (BRKL) Reset: Read: Break Status and Control Write: Register (BRKSCR) Reset: Read: COP Control Register Write: (COPCTL) Reset: = Unimplemented Bit 7 0 R 0 IF14 R 0 0 R 0 R 6 IF5 R 0 0 R 0 0 R 0 R 5 IF4 R 0 0 R 0 0 R 0 R 4 IF3 R 0 0 R 0 0 R 0 R 3 0 R 0 0 R 0 0 R 0 R 2 IF1 R 0 0 R 0 0 R 0 R 1 0 R 0 0 R 0 0 R 0 R Bit 0 0 R 0 0 R 0 IF15 R 0 R
$FE05
0 0 BPR7 0 R
0 0 BPR6 0 R
0 0 BPR5 0 R
0 0 BPR4 0 R
$FE08
HVEN 0 BPR3 0 R
MASS 0 BPR2 0 R
ERASE 0 BPR1 0 R
PGM 0 BPR0 0 R
$FE09
$FE0A $FE0B
$FE0C
Bit15 0 Bit7 0 BRKE 0
Bit14 0 Bit6 0 BRKA 0
Bit13 0 Bit5 0 0 0
Bit12 0 Bit4 0 0 0
Bit11 0 Bit3 0 0 0
Bit10 0 Bit2 0 0 0
Bit9 0 Bit1 0 0 0
Bit8 0 Bit0 0 0 0
$FE0E
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset R = Reserved
$FFFF
Random-Access Memory (RAM)
Table 2-1. Vector Addresses

Vector Priority Lowest INT Flag Address $FFD0 $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Not Used ADC Conversion Complete Vector (High) ADC Conversion Complete Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) Not Used TIM Overflow Vector (High) TIM Overflow Vector (Low) TIM Channel 1 Vector (High) TIM Channel 1 Vector (Low) TIM Channel 0 Vector (High) TIM Channel 0 Vector (Low) Not Used IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) Vector
IF15
IF14 IF13 IF6 IF5
IF4
IF3 IF2 IF1
Highest
2.4 Random-Access Memory (RAM)

Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 compatibility, the H register is not stacked.
Memory
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
2.5 Flash Memory

This sub-section describes the operation of the embedded Flash memory. The Flash memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
Device MC68H(R)C908JL3E MC68H(R)C908JK3E MC68H(R)C908JK1E Flash Memory Size (Bytes) 4,096 4,096 1,536 Memory Address Range $EC00$FBFF $EC00$FBFF $F600$FBFF
Addr. $FE08
Register Name Flash Control Register (FLCR) Flash Block Protect Register (FLBPR) Read: Write: Reset: Read: Write: Reset:
Bit 7 0 0 BPR7 0
6 0 0 BPR6
5 0 0 BPR5
4 0 0 BPR4 0
3 HVEN 0 BPR3 0
2 MASS 0 BPR2 0
1 ERASE 0 BPR1 0
Bit 0 PGM 0 BPR0 0
$FE09
0 0 = Unimplemented
Figure 2-3. Flash I/O Register Summary
2.6 Functional Description

The Flash memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user vectors. The minimum size of Flash memory that can be erased is 64 bytes (a page); and the maximum size of Flash memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: $EC00$FBFF; user memory; 4,096 bytes; MC68H(R)C908JL3E/JK3E $F600$FBFF; user memory; 1,536 bytes; MC68H(R)C908JK1E $FFD0$FFFF; user interrupt vectors; 48 bytes NOTE An erased bit reads as 1 and a programmed bit reads as 0. A security feature prevents viewing of the Flash contents.(1)
1. No security feature is absolutely secure. However, Freescales strategy is to make reading or copying the Flash difficult for unauthorized users. MC68HC908JL3E Family Data Sheet, Rev. 4 28 Freescale Semiconductor
Flash Control Register
2.7 Flash Control Register

The Flash Control Register controls Flash program and erase operations.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $FE08 Bit 7 0 6 0 5 0 4 0 3 HVEN 0 2 MASS 0 1 ERASE 0 Bit 0 PGM 0
Figure 2-4. Flash Control Register (FLCR) HVEN High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM=1 or ERASE=1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE Erase Control Bit This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected
Memory
2.8 Flash Page Erase Operation

Use the following procedure to erase a page of Flash memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any page within the 4K bytes user memory area ($EC00$FBFF) can be erased alone. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the Flash Control Register. 2. Write any data to any Flash address within the page address range desired. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time tErase (1ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh (5s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again. NOTE Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
2.9 Flash Mass Erase Operation

Use the following procedure to erase the entire Flash memory: 1. Set both the ERASE bit and the MASS bit in the Flash Control Register. 2. Write any data to any Flash location within the Flash memory address range. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time tMErase (4ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh1 (100s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again. NOTE Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
Flash Program Operation
2.10 Flash Program Operation

Programming of the Flash memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of Flash memory (Figure 2-5 shows a flowchart of the programming algorithm): 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any Flash location within the address range of the row to be programmed. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time, tpgs (5s). 6. Write data to the byte being programmed. 7. Wait for time, tPROG (30s). 8. Repeat step 6 and 7 until all the bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (5s). 11. Clear the HVEN bit. 12. After time, trcv (1s), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each Flash address change (step 6 to step 6), or the time between the last Flash addressed programmed to clearing the PGM bit (step 6 to step 10), must not exceed the maximum programming time, tPROG max. NOTE Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
2.11 Flash Protection

Due to the ability of the on-board charge pump to erase and program the Flash memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a Flash Block Protect Register (FLBPR). The FLBPR determines the range of the Flash memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the Flash memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.
Memory
Set PGM bit
Algorithm for programming a row (32 bytes) of Flash memory

2
Write any data to any Flash address within the row address range desired
Wait for a time, tnvs
Set HVEN bit
Wait for a time, tpgs
Write data to the Flash address to be programmed
Wait for a time, tPROG
Completed programming this row? N

9
NOTE: The time between each Flash address change (step 6 to step 6), or the time between the last Flash address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased.
Clear PGM bit
10
Wait for a time, tnvh
11
Clear HVEN bit
12
Wait for a time, trcv
End of Programming
Figure 2-5. Flash Programming Flowchart
Flash Block Protect Register
2.12 Flash Block Protect Register

The Flash Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the Flash memory.
Address: Read: Write: Reset: $FE09 Bit 7 BPR7 0 6 BPR6 0 5 BPR5 0 4 BPR4 0 3 BPR3 0 2 BPR2 0 1 BPR1 0 Bit 0 BPR0 0
Figure 2-6. Flash Block Protect Register (FLBPR) BPR[7:0] Flash Block Protect Register Bit 7 to Bit 0 BPR[7:1] represent bits [12:6] of a 16-bit memory address. Bits [15:13] are 1s and bits [5:0] are 0s.
16-bit memory address Start address of Flash block protect 1 1 1 BPR[7:1] 0 0 0 0 0 0
BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the Flash memory for block protection. The Flash is protected from this start address to the end of Flash memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries 64 bytes) within the Flash memory. Examples of protect start address:
BPR[7:0] $00$60 $62 or $63 (0110 001x) $64 or $65 (0110 010x) $68 or $69 (0110 100x) and so on... $DE or $DF (1101 111x) $FE (1111 1110) $FF $FBC0 (1111 1011 1100 0000) $FFC0 (1111 1111 1100 0000) The entire Flash memory is not protected. Start of Address of Protect Range The entire Flash memory is protected. $EC40 (1110 1100 0100 0000) $EC80 (1110 1100 1000 0000) $ED00 (1110 1101 0000 0000)
Note: The end address of the protected range is always $FFFF.
Memory
Chapter 3 Configuration Registers (CONFIG)

3.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options: Stop mode recovery time (32 2OSCOUT cycles or 4096 2OSCOUT cycles) STOP instruction Computer operating properly module (COP) COP reset period (COPRS), 8176 2OSCOUT or 262,128 2OSCOUT Enable LVI circuit Select LVI trip voltage

The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU it is recommended that this register be written immediately after reset. The configuration register is located at $001E and $001F, and may be read at anytime. NOTE The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-1 and Figure 3-2.
3.3 Configuration Register 1 (CONFIG1)

Address: Read: Write: Reset: $001F Bit 7 COPRS 0 R 6 R 0 = Reserved 5 R 0 4 LVID 0 3 R 0 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
Figure 3-1. Configuration Register 1 (CONFIG1) COPRS COP reset period selection bit 1 = COP reset cycle is 8176 2OSCOUT 0 = COP reset cycle is 262,128 2OSCOUT
Configuration Registers (CONFIG)
LVID Low Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled SSREC Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 2OSCOUT cycles instead of a 4096 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 2OSCOUT cycles 0 = Stop mode recovery after 4096 2OSCOUT cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP STOP Instruction Enable STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD COP Disable Bit COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
3.4 Configuration Register 2 (CONFIG2)

Address: Read: Write: Reset: POR: $001E Bit 7 IRQPUD 0 0 R 6 R 0 0 = Reserved 5 R 0 0 4 LVIT1 Not affected 0 3 LVIT0 Not affected 0 2 R 0 0 1 R 0 0 Bit 0 R 0 0
Figure 3-2. Configuration Register 2 (CONFIG2) IRQPUD IRQ Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD LVIT1, LVIT0 Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI)
Chapter 4 Central Processor Unit (CPU)

4.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
4.2 Features
Features of the CPU include: Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes
4.3 CPU Registers

Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.
Central Processor Unit (CPU)

7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWOS COMPLEMENT OVERFLOW FLAG
Figure 4-1. CPU Registers
4.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 4-2. Accumulator (A)
4.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X X = Indeterminate 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 4-3. Index Register (H:X)
CPU Registers
4.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 4-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
4.3.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 4-5. Program Counter (PC)
4.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: Write: Reset: V X X = Indeterminate 6 1 1 5 1 1 4 H X 3 I 1 2 N X 1 Z X Bit 0 C X
Figure 4-6. Condition Code Register (CCR) V Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result
Arithmetic/Logic Unit (ALU)
Z Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions such as bit test and branch, shift, and rotate also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
4.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
4.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode

The WAIT instruction: Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
4.5.2 Stop Mode

The STOP instruction: Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
4.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by: Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary

Table 4-1 provides a summary of the M68HC08 instruction set. Table 4-1. Instruction Set Summary (Sheet 1 of 6)
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operation
Description
V H I N Z C
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM IMM IMM DIR EXT IX2 0 IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL REL REL
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff
Add without Carry
A (A) + (M)
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
Logical AND
A (A) & (M)
Arithmetic Shift Left (Same as LSL)
C b7 b0
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F 25 27 90 92 28 29 22 rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr
Arithmetic Shift Right

b7 b0
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
BCLR n, opr
Clear Bit n in M
Mn 0
BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0 REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 REL REL REL
3 3
Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3 3 3 3
Effect on CCR
Operand
Instruction Set Summary
Table 4-1. Instruction Set Summary (Sheet 2 of 6)

BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
V H I N Z C
REL REL REL IMM DIR EXT 0 IX2 IX1 IX SP1 SP2
24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A
rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr
Bit Test
(A) & (M)
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel REL REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR IMM IMM IX1+ IX+ SP1 0 INH 0 INH
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
BRN rel
Branch Never
PC (PC) + 2
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
BSET n,opr
Set Bit n in M
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) 1; push (PCH) SP (SP) 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) (M) = $00 PC (PC) + 3 + rel ? (A) (M) = $00 PC (PC) + 3 + rel ? (X) (M) = $00 PC (PC) + 3 + rel ? (A) (M) = $00 PC (PC) + 2 + rel ? (A) (M) = $00 PC (PC) + 4 + rel ? (A) (M) = $00 C0 I0
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI Clear Carry Bit Clear Interrupt Mask
Cycles
3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2
Effect on CCR
Operand

CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operation
Description
M $00 A $00 X $00 H $00 M $00 M $00 M $00
V H I N Z C
Clear
DIR INH INH 0 0 1 INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 0 1 IX1 IX SP1 IMM DIR
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) (M)
Complement (Ones Complement)
M (M) = $FF (M) A (A) = $FF (M) X (X) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) (H:X) (M:M + 1)
33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr ii ii+1 dd ii dd hh ll ee ff ff ff ee ff
Compare H:X with M
Compare X with M
(X) (M)
IMM DIR EXT IX2 IX1 IX SP1 SP2 U INH
Decimal Adjust A
(A)10
DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP
A (A) 1 or M (M) 1 or X (X) 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) 1 A (A) 1 X (X) 1 M (M) 1 M (M) 1 M (M) 1 A (H:A)/(X) H Remainder DIR INH INH IX1 IX SP1 INH IMM DIR EXT 0 IX2 IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1
Decrement
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
Exclusive OR M with A
A (A M)
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
3C dd 4C 5C 6C ff 7C 9E6C ff
Cycles
3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5
Effect on CCR
Operand
Instruction Set Summary

JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX
Operation
Description
V H I N Z C
PC Jump Address
Jump
DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 0 IX1 IX SP1 SP2 0 IMM DIR
BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE
dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) 1 Push (PCH); SP (SP) 1 PC Unconditional Address
Load A from M
A (M)
Load H:X from M
H:X (M:M + 1)
Load X from M
X (M)
IMM DIR EXT IX2 0 IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH 0 INH IX1 IX SP1 DD DIX+ 0 IMD IX+D 0 0 INH DIR INH INH IX1 IX SP1 INH INH IMM DIR EXT IX2 0 IX1 IX SP1 SP2 INH INH INH
Logical Shift Left (Same as ASL)
C b7 b0
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Logical Shift Right
0 b7 b0
Move Unsigned multiply
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) (A) M (M) = $00 (M) A (A) = $00 (A) X (X) = $00 (X) M (M) = $00 (M) M (M) = $00 (M) None A (A[3:0]:A[7:4])
Negate (Twos Complement)
No Operation Nibble Swap A
Inclusive OR A and M
A (A) | (M)
Push A onto Stack Push H onto Stack Push X onto Stack
Push (A); SP (SP) 1 Push (H); SP (SP) 1 Push (X); SP (SP) 1
Cycles
2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2
Effect on CCR
Operand

PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operation
Pull A from Stack Pull H from Stack Pull X from Stack
Description
SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
V H I N Z C
INH INH INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 INH INH
86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Left through Carry
C b7 b0
Rotate Right through Carry

b7 b0
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
RTI
Return from Interrupt
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
INH IMM DIR EXT IX2 IX1 IX SP1 SP2 1 INH 1 INH DIR EXT IX2 0 IX1 IX SP1 SP2 0 DIR 0 INH DIR EXT IX2 0 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
Subtract with Carry
A (A) (M) (C)
Set Carry Bit Set Interrupt Mask
C1 I1
Store A in M
M (A)
Store H:X in M Enable Interrupts, Stop Processing, Refer to MCU Documentation
(M:M + 1) (H:X) I 0; Stop Processing
Store X in M
M (X)
Subtract
A (A) (M)
Cycles
2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Effect on CCR
Operand
Opcode Map

Address Mode Opcode Source Form Operation Description
PC (PC) + 1; Push (PCL) SP (SP) 1; Push (PCH) SP (SP) 1; Push (X) SP (SP) 1; Push (A) SP (SP) 1; Push (CCR) SP (SP) 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
V H I N Z C
SWI
Software Interrupt
1 INH
83
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS WAIT A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH INH INH DIR INH INH 0 IX1 IX SP1 INH INH INH 0 INH
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 8F
Test for Negative or Zero
(A) $00 or (X) $00 or (M) $00
Transfer SP to H:X Transfer X to A Transfer H:X to SP Enable Interrupts; Wait for Interrupt
H:X (SP) + 1 A (X) (SP) (H:X) 1 I bit 0; Inhibit CPU clocking until interrupted n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() ( ) # ? :
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (twos complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
4.8 Opcode Map

See Table 4-2.
Cycles
9 2 1 1 3 1 1 3 2 4 2 1 2 1
Effect on CCR
Operand
48
Bit Manipulation DIR DIR
MSB LSB
Table 4-2. Opcode Map

Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL DIR 3 INH 4 Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 9E6 IX 7 Control INH INH 8 9 IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM DIR B EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT Register/Memory IX2 SP2 D 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 E SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 IX F 0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3
4 5 6 7 8 9 A B C D E
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor
INH Inherent REL Relative IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD Direct-Direct IMD Immediate-Direct IX+D Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Chapter 5 System Integration Module (SIM)

5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: Bus clock generation and control for CPU and peripherals Stop/wait/reset/break entry and recovery Internal clock control Master reset control, including power-on reset (POR) and COP timeout Interrupt control: Acknowledge timing Arbitration control timing Vector address generation CPU enable/disable timing Modular architecture expandable to 128 interrupt sources Table 5-1 shows the internal signal names used in this section. Table 5-1. Signal Name Conventions
Signal Name 2OSCOUT OSCOUT IAB IDB PORRST IRST R/W Description Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit. The 2OSCOUT frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT 4) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
System Integration Module (SIM)

MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK
2OSCOUT (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR) 2 VDD CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS
INTERNAL PULL-UP
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) USB RESET (FROM USB MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 5-1. SIM Block Diagram

Addr. Register Name Bit 7 R 0 POR 1 R 6 R 0 PIN 0 R 5 R 0 COP 0 R 4 R 0 ILOP 0 R 3 R 0 ILAD 0 R 2 R 0 MODRST 0 R 1 SBSW NOTE 0 LVI 0 R Bit 0 R 0 0 0 R
Read: Break Status Register $FE00 Write: (BSR) Reset: Note: Writing a 0 clears SBSW. Read: Reset Status Register Write: $FE01 (RSR) POR: Read: $FE02 Reserved Write: Reset: Read: Break Flag Control $FE03 Write: Register (BFCR) Reset:
BCFE 0
R R
R = Reserved
= Unimplemented
Figure 5-2. SIM I/O Register Summary

SIM Bus Clock Control and Generation Addr. $FE04 Register Name Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 0 R 0 IF14 R 0 0 R 0 6 5 IF5 IF4 R R 0 0 0 0 R R 0 0 0 0 R R 0 0 = Unimplemented 4 IF3 R 0 0 R 0 0 R 0 3 0 R 0 0 R 0 0 R 0 R 2 IF1 R 0 0 R 0 0 R 0 = Reserved 1 0 R 0 0 R 0 0 R 0 Bit 0 0 R 0 0 R 0 IF15 R 0
$FE05
$FE06
Figure 5-2. SIM I/O Register Summary
5.2 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 5-3.
FROM OSCILLATOR FROM OSCILLATOR
2OSCOUT OSCOUT
SIM COUNTER
BUS CLOCK GENERATORS
SIM
Figure 5-3. SIM Clock Signals
5.2.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four.
5.2.2 Clock Start-Up from POR

When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the time-out.
5.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 2OSCOUT cycles. (See 5.6.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
5.3 Reset and System Initialization

The MCU has these reset sources: Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address
All of these resets produce the vector $FFFE$FFFF ($FEFE$FEFF in Monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 5.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 5.7 SIM Registers.)
5.3.1 External Pin Reset

The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum of 67 2OSCOUT cycles, assuming that the POR was not the source of the reset. See Table 5-2 for details. Figure 5-4 shows the relative timing. Table 5-2. PIN Bit Set Timing
Reset Type POR All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
2OSCOUT RST IAB PC VECT H VECT L
Figure 5-4. External Reset Timing
5.3.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (Figure 5-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR. (See Figure 5-6.) Note that for POR resets, the SIM cycles through 4096 2OSCOUT cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 5-5.
Reset and System Initialization

IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
2OSCOUT
IAB
VECTOR HIGH
Figure 5-5. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET
Figure 5-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 5.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: A POR pulse is generated. The internal reset signal is asserted. The SIM enables the oscillator to drive 2OSCOUT. Internal clocks to the CPU and modules are held inactive for 4096 2OSCOUT cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES 2OSCOUT 32 CYCLES 32 CYCLES
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 5-7. POR Recovery

5.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 4080 2OSCOUT cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time-out. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 5.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 5.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
SIM Counter
5.3.2.5 LVI Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIP. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RSTB) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RSTB) pin for all internal reset sources.
5.4 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of 2OSCOUT.
5.4.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.
5.4.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a one, then the stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32 2OSCOUT cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
5.4.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See 5.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 5.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)
5.5 Exception Control

Normal, sequential program execution can be changed in three different ways: Interrupts Maskable hardware CPU interrupts Non-maskable software interrupt instruction (SWI) Reset Break interrupts
5.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 5-8 flow charts the handling of system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared).
FROM RESET
BREAK INTERRUPT? I BIT SET? NO
YES
YES
I BIT SET?
NO
IRQ INTERRUPT? NO
YES
TIMER INTERRUPT? NO (As many interrupts as exist on chip)
YES
STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO
YES
RTI INSTRUCTION? NO
YES
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
Figure 5-8. Interrupt Processing

Exception Control
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows interrupt entry timing. Figure 5-10 shows interrupt recovery timing.
MODULE INTERRUPT I BIT
IAB
DUMMY
SP
SP 1
SP 2
SP 3
SP 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC 1[7:0] PC 1[15:8]
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 5-9. Interrupt Entry

MODULE INTERRUPT I BIT
IAB
SP 4
SP 3
SP 2
SP 1
SP
PC
PC + 1
IDB
CCR
PC 1[15:8] PC 1[7:0]
OPCODE
OPERAND
R/W
Figure 5-10. Interrupt Recovery

5.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 5-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.

CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 5-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 5.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC 1, as a hardware interrupt does.
5.5.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 5-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.
Exception Control
Table 5-3. Interrupt Sources

Priority Highest Reset SWI Instruction IRQ Pin Timer Channel 0 Interrupt Timer Channel 1 Interrupt Timer Overflow Interrupt Keyboard Interrupt Lowest ADC Conversion Complete Interrupt Source Flag IRQF CH0F CH1F TOF KEYF COCO MASK(1) IMASK CH0IE CH1IE TOIE IMASKK AIEN INT Register Flag IF1 IF3 IF4 IF5 IF14 IF15 Vector Address $FFFE$FFFF $FFFC$FFFD $FFFA$FFFB $FFF6$FFF7 $FFF4$FFF5 $FFF2$FFF3 $FFE0$FFE1 $FFDE$FFDF
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
5.5.2.1 Interrupt Status Register 1

Address: Read: Write: Reset: $FE04 Bit 7 0 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 0 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 5-12. Interrupt Status Register 1 (INT1) IF1, IF3 to IF5 Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 5-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3 and 7 Always read 0 5.5.2.2 Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 IF14 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 0 R 0
Figure 5-13. Interrupt Status Register 2 (INT2)
IF14 Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 5-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 to 6 Always read 0 5.5.2.3 Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 IF15 R 0
Figure 5-14. Interrupt Status Register 3 (INT3) IF15 Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 5-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1 to 7 Always read 0
5.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
5.5.4 Break Interrupts

The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 15 Break Module (BREAK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
5.5.5 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism for example, a read of one register followed by the read or write of another are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
Low-Power Modes
5.6 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
5.6.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 5-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option register is zero, then the computer operating properly module (COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 5-15. Wait Mode Entry Timing Figure 5-16 and Figure 5-17 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 5-16. Wait Recovery from Interrupt or Break

32 Cycles IAB $6E0B 32 Cycles RSTVCTH RSTVCT L
IDB
$A6
$A6
$A6
RST
2OSCOUT
Figure 5-17. Wait Recovery from Internal Reset
5.6.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 5-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 5-18. Stop Mode Entry Timing
SIM Registers
STOP RECOVERY PERIOD 2OSCOUT
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP 1
SP 2
SP 3
Figure 5-19. Stop Mode Recovery from Interrupt or Break
5.7 SIM Registers

The SIM has three memory mapped registers. Table 5-4 shows the mapping of these registers. Table 5-4. SIM Registers
Address $FE00 $FE01 $FE03 Register BSR RSR BFCR Access Mode User User User
5.7.1 Break Status Register (BSR)

The break status register contains a flag to indicate a break caused by an exit from wait mode.
Address: Read: Write: Reset: R = Reserved 1. Writing a zero clears SBSW. $FE00 Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 Bit 0 R
Figure 5-20. Break Status Register (BSR) SBSW SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt
5.7.2 Reset Status Register (RSR)

The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the register. All other reset sources set the individual flag bits but do not clear the register. More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Address: Read: Write: POR: 1 0 = Unimplemented 0 0 0 0 0 0 $FE01 Bit 7 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
Figure 5-21. Reset Status Register (RSR) POR Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST Monitor Mode Entry Module Reset bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = VDD 0 = POR or read of SRSR LVI Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR
SIM Registers
5.7.3 Break Flag Control Register (BFCR)

The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 5-22. Break Flag Control Register (BFCR) BCFE Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
Chapter 6 Oscillator (OSC)

6.1 Introduction
The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator modules are available: MC68HC908JL3E/JK3E/JK1E built-in oscillator module (X-tal) that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1. MC68HRC908JL3E/JK3E/JK1E built-in oscillator module (RC) that requires an external RC connection only.
6.2 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E)

The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 6-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional) The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturers data for more information.
6.3 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E)

The RC oscillator circuit is designed for use with external R and C to provide a clock source with tolerance less than 10%. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: CEXT REXT The RC connection is shown in Figure 6-2.
Oscillator (OSC)
From SIM To SIM 2OSCOUT To SIM OSCOUT
XTALCLK SIMOSCEN
MCU
OSC1 RB OSC2
RS* X1 *RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturers data. See Chapter 16 Electrical Specifications for component value requirements. C1 C2
Figure 6-1. X-tal Oscillator External Connections
From SIM
To SIM 2OSCOUT
To SIM OSCOUT
SIMOSCEN
EN
Ext-RC Oscillator
RCCLK
0 PTA6 I/O
PTA6 PTA6EN
MCU
OSC1 PTA6/RCCLK (OSC2)
VDD
REXT
CEXT
See Chapter 16 Electrical Specifications for component value requirements.
Figure 6-2. RC Oscillator External Connections
I/O Signals
6.4 I/O Signals

The following paragraphs describe the oscillator I/O signals.
6.4.1 Crystal Amplifier Input Pin (OSC1)

OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.
6.4.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK)

For the X-tal oscillator device, OSC2 pin is the output of the crystal oscillator inverting amplifier. For the RC oscillator device, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of the internal RC oscillator clock, RCCLK.
Device MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Oscillator X-tal RC OSC2 pin function Inverting OSC1 Controlled by PTA6EN bit in PTAPUER ($0D) PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6 I/O
6.4.3 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the X-tal oscillator circuit or the RC-oscillator.
6.4.4 X-tal Oscillator Clock (XTALCLK)

XTALCLK is the X-tal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 6-1 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start-up.
6.4.5 RC Oscillator Clock (RCCLK)

RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. Figure 6-2 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry.
6.4.6 Oscillator Out 2 (2OSCOUT)

2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module and is used to determine the COP cycles.
6.4.7 Oscillator Out (OSCOUT)

The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency.
Oscillator (OSC)
6.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
6.5.1 Wait Mode

The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to the SIM module.
6.5.2 Stop Mode

The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT.
6.6 Oscillator During Break Mode

The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state.
Chapter 7 Monitor ROM (MON)

7.1 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of Flash memory in the MCU. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
7.2 Features
Features of the monitor ROM include the following: Normal user-mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Execution of code in RAM or Flash Flash memory security feature(1) Flash memory programming interface 960 bytes monitor ROM code size Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) Standard monitor mode entry if high voltage, VTST, is applied to IRQ

The monitor ROM receives and executes commands from a host computer. Figure 7-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor.
1. No security feature is absolutely secure. However, Freescales strategy is to make reading or copying the Flash difficult for unauthorized users. MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 71
Monitor ROM (MON)
RC CIRCUIT FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION B
VDD See Figure 16-1. RC vs. Frequency (5V @25 C) for component values vs. frequency. OSC1 OSC2
RST 0.1 F
H(R)C908JL3E H(R)C908JK3E H(R)C908JK1E

VDD VDD 0.1 F VSS
EXT OSC FOR MC68HC908JL3E/JK3E/JK1E SW1 AT POSITION A OR B FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION A
VDD
(50% DUTY) OSC1 OSC2
XTAL CIRCUIT FOR MC68HC908JL3E/JK3E/JK1E SW1 AT POSITION A OR B MAX232 1 1 F + 3 4 1 F + 5 C2 DB9 2 3 5 7 8 10 9 74HC125 3 2 1 V 6 + 1 F 74HC125 5 6 4 10 k C1+ VCC 16 + 15 + 2 VTST VDD 1 F 1 F VDD 20 pF
9.8304MHz 10M
OSC1
OSC2 20 pF
C1 C2+
GND V+
A 1k 8.5 V B
SW1
(SEE NOTE 1) IRQ VDD
10 k
PTB0 VDD 10 k C SW2 VDD 10 k PTB1 PTB3 PTB2 10 k
(SEE NOTE 2) NOTES: D 1. Monitor mode entry method: SW1: Position A High voltage entry (VTST) 10 k Clock source must be EXT OSC or XTAL CIRCUIT. Bus clock depends on SW2. SW1: Position B Reset vector must be blank ($FFFE = $FFFF = $FF) Bus clock = OSC1 4. 2. Affects high voltage entry to monitor mode only (SW1 at position A): SW2: Position C Bus clock = OSC1 4 SW2: Position D Bus clock = OSC1 2 5. See Table 16-4. DC Electrical Characteristics (5V) for VTST voltage level requirements.
Figure 7-1. Monitor Mode Circuit
Functional Description
7.3.1 Entering Monitor Mode

Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If IRQ = VTST: Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL) PTB3 = low 2. If IRQ = VTST: Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL) PTB3 = high 3. If $FFFE & $FFFF is blank (contains $FF): Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC) IRQ = VDD Table 7-1. Monitor Mode Entry Requirements and Options
PTB3(1) $FFFE and $FFFF PTB2 PTB1 PTB0 IRQ OSC1 Frequency Bus Frequency 2.4576MHz (OSC1 2) 2.4576MHz (OSC1 4) 2.4576MHz (OSC1 4) Comments
VTST(2) VTST
X X BLANK (contain $FF) NOT BLANK
0 1
0 0
1 1
1 1
4.9152MHz 9.8304MHz
High-voltage entry to monitor mode.(3) 9600 baud communication on PTB0. COP disabled. Low-voltage entry to monitor mode.(4) 9600 baud communication on PTB0. COP disabled. Enters User mode.
VDD
9.8304MHz
VDD
At desired frequency
OSC1 4
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using VTST for monitor mode entry. The OSC1 clock must be 50% duty cycle for this condition. 2. See Table 16-4. DC Electrical Characteristics (5V) for VTST voltage level requirements. 3. For IRQ = VTST: MC68HRC908JL3E/JK3E/JK1E clock must be EXT OSC. MC68HC908JL3E/JK3E/JK1E clock can be EXT OSC or XTAL. 4. For IRQ = VDD: MC68HRC908JL3E/JK3E/JK1E clock must be RC OSC. MC68HC908JL3E/JK3E/JK1E clock can be EXT OSC or XTAL.
If VTST is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with VTST applied to IRQ upon monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this event, the OSCOUT frequency is equal to the 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
Monitor ROM (MON)
Entering monitor mode with VTST on IRQ, the COP is disabled as long as VTST is applied to either the IRQ or the RST. (See Chapter 5 System Integration Module (SIM) for more information on modes of operation.) If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF) (Table 7-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions, including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ or the RST. Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ = VDD. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.
POR RESET
IS VECTOR BLANK? YES MONITOR MODE
NO
NORMAL USER MODE
EXECUTE MONITOR CODE
POR TRIGGERED? YES
NO
Figure 7-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate. In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code.
Table 7-2 is a summary of the vector differences between user mode and monitor mode. Table 7-2. Monitor Mode Vector Differences
Functions Modes COP Enabled Disabled(1) Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
User Monitor
1. If the high voltage (VTST) is removed from the IRQ pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register.
When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends control to the address on the stack pointer.
7.3.2 Baud Rate

The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ = VTST. When PTB3 is high, the divide by ratio is 1024. If the PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Table 7-3. Monitor Baud Rate Selection
Monitor Mode Entry By: Input Clock Frequency 4.9152 MHz IRQ = VTST 9.8304 MHz 4.9152 MHz Blank reset vector, IRQ = VDD 9.8304 MHz 4.9152 MHz PTB3 0 1 1 X X Baud Rate 9600 bps 9600 bps 4800 bps 9600 bps 4800 bps
Monitor ROM (MON)
7.3.3 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 7-3 and Figure 7-4.)
START BIT NEXT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
Figure 7-3. Monitor Data Format

START BIT START BIT NEXT START BIT NEXT START BIT
$A5 BREAK
BIT 0 BIT 0
BIT 1 BIT 1
BIT 2 BIT 2
BIT 3 BIT 3
BIT 4 BIT 4
BIT 5 BIT 5
BIT 6 BIT 6
BIT 7 BIT 7
STOP BIT STOP BIT
Figure 7-4. Sample Monitor Waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive baud rates must be identical.
7.3.4 Echoing
As shown in Figure 7-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin for error checking.
SENT TO MONITOR READ ECHO READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
RESULT
Figure 7-5. Read Transaction Any result of a command appears after the echo of the last byte of the command.
7.3.5 Break Signal

A start bit followed by nine low bits is a break signal. (See Figure 7-6.) When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO
Figure 7-6. Break Transaction
7.3.6 Commands
The monitor ROM uses the following commands: READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program) Table 7-4. READ (Read Memory) Command
Description Operand Data Returned Opcode Command Sequence
SENT TO MONITOR
Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Table 7-5. WRITE (Write Memory) Command

SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA
Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte None $49
ECHO
Monitor ROM (MON)
Table 7-6. IREAD (Indexed Read) Command

SENT TO MONITOR IREAD IREAD DATA DATA
Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A
ECHO
RESULT
Table 7-7. IWRITE (Indexed Write) Command

SENT TO MONITOR IWRITE IWRITE DATA DATA
Write to last address accessed + 1 Specifies single data byte None $19
ECHO
NOTE A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map.
Security
Table 7-8. READSP (Read Stack Pointer) Command

SENT TO MONITOR READSP READSP SP HIGH SP LOW
Reads stack pointer None Returns stack pointer in high byte:low byte order $0C
ECHO
RESULT
Table 7-9. RUN (Run User Program) Command

SENT TO MONITOR RUN RUN
Executes RTI instruction None None $28
ECHO
7.4 Security
A security feature discourages unauthorized reading of Flash locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6$FFFD. Locations $FFF6$FFFD contain user-defined data. NOTE Do not leave locations $FFF6$FFFD blank. For security reasons, program locations $FFF6$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTB0. If the received bytes match those at locations $FFF6$FFFD, the host bypasses the security feature and can read all Flash locations and execute code from Flash. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 7-7.)
Monitor ROM (MON)
VDD 4096 + 32 OSCXCLK CYCLES RST COMMAND 1 BYTE 8 ECHO BYTE 2 ECHO 2 4 1 COMMAND ECHO BREAK 24 BUS CYCLES BYTE 1 BYTE 2 BYTE 8 1
FROM HOST
PTB0 1 BYTE 1 ECHO FROM MCU 4
NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte.
Figure 7-7. Monitor Mode Entry Timing Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a Flash location returns an invalid value and trying to execute code from Flash causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bytes. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is set. If it is, then the correct security code has been entered and Flash can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the Flash module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).
Chapter 8 Timer Interface Module (TIM)

8.1 Introduction
This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 8-1 is a block diagram of the TIM.
8.2 Features
Features of the TIM include the following: Two input capture/output compare channels Rising-edge, falling-edge, or any-edge input capture trigger Set, clear, or toggle output compare action Buffered and unbuffered pulse width modulation (PWM) signal generation Programmable TIM clock input with 7-frequency internal bus clock prescaler selection Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
8.3 Pin Name Conventions

The TIM share two I/O pins with two port D I/O pins. The full name of the TIM I/O pins are listed in Table 8-1. The generic pin name appear in the text that follows. Table 8-1. Pin Name Conventions
TIM Generic Pin Names: Full TIM Pin Names: TCH0 PTD4/TCH0 TCH1 PTD5/TCH1
Timer Interface Module (TIM)

Figure 8-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels.
PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 8-1. TIM Block Diagram
Addr. $0020
Register Name Read: TIM Status and Control Register (TSC) Write: Reset: Read:
Bit 7 TOF 0 0 Bit15 0 Bit7 0 Bit15 1 Bit7 1 CH0F 0 0 Bit15
6 TOIE 0 Bit14 0 Bit6 0 Bit14 1 Bit6 1 CH0IE 0 Bit14
5 TSTOP 1 Bit13 0 Bit5 0 Bit13 1 Bit5 1 MS0B 0 Bit13
4 0 TRST 0 Bit12 0 Bit4 0 Bit12 1 Bit4 1 MS0A 0 Bit12
3 0 0 Bit11 0 Bit3 0 Bit11 1 Bit3 1 ELS0B 0 Bit11
2 PS2 0 Bit10 0 Bit2 0 Bit10 1 Bit2 1 ELS0A 0 Bit10
1 PS1 0 Bit9 0 Bit1 0 Bit9 1 Bit1 1 TOV0 0 Bit9
Bit 0 PS0 0 Bit8 0 Bit0 0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
$0021
TIM Counter Register High (TCNTH)
Write: Reset: Read:
$0022
TIM Counter Register Low (TCNTL)
Write: Reset: Read:
$0023
TIM Counter Modulo Register High (TMODH)
Write: Reset: Read:
$0024
TIM Counter Modulo Register Low (TMODL)
Write: Reset: Read:
$0025
TIM Channel 0 Status and Control Register (TSC0)
Write: Reset: Read:
$0026
TIM Channel 0 Register High (TCH0H)
Write: Reset: Read:
$0027
TIM Channel 0 Register Low (TCH0L)
Write: Reset: Read:
Indeterminate after reset CH1F 0 0 Bit15 CH1IE 0 Bit14 0 0 Bit13 MS1A 0 Bit12 ELS1B 0 Bit11 ELS1A 0 Bit10 TOV1 0 Bit9 CH1MAX 0 Bit8
$0028
TIM Channel 1 Status and Control Register (TSC1)
Write: Reset: Read:
$0029
TIM Channel 1 Register High (TCH1H)
Write: Reset: Read:
$002A
TIM Channel 1 Register Low (TCH1L)
Write: Reset:
Indeterminate after reset = Unimplemented
Figure 8-2. TIM I/O Register Summary
8.4.1 TIM Counter Prescaler

The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.
8.4.2 Input Capture

With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
8.4.3 Output Compare

With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 8.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 8.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 8.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
8.4.4 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 8-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIM to set the pin if the state of the PWM pulse is logic zero.
OVERFLOW PERIOD OVERFLOW OVERFLOW
PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 8-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 8.9.1 TIM Status and Control Register (TSC)). The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%.
8.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 8.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 8.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
8.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 8-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 8-3.) NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1).)
8.5 Interrupts
The following TIM sources can generate interrupt requests: TIM overflow flag (TOF) The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1. CHxF and CHxIE are in the TIM channel x status and control register.
8.6 Low-Power Modes

8.6.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
8.6.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
8.7 TIM During Break Interrupts

A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR).) To allow software to clear status bits during a break interrupt, write a one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a zero to the BCFE bit. With BCFE at zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at zero. After the break, doing the second step clears the status bit.
I/O Signals
8.8 I/O Signals

Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin.
8.9 I/O Registers

The following I/O registers control and monitor operation of the TIM: TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
8.9.1 TIM Status and Control Register (TSC)

The TIM status and control register does the following: Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
Address: Read: Write: Reset: $0020 Bit 7 TOF 0 0 6 TOIE 0 = Unimplemented 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0
Figure 8-4. TIM Status and Control Register (TSC) TOF TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a zero to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled
TSTOP TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. When the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared. When using TSTOP to stop the timer counter, see if any timer flags are set. If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the flag, then setting TSTOP again. TRST TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as zero. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 8-2 shows. Reset clears the PS[2:0] bits. Table 8-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal Bus Clock 1 Internal Bus Clock 2 Internal Bus Clock 4 Internal Bus Clock 8 Internal Bus Clock 16 Internal Bus Clock 32 Internal Bus Clock 64 Not available
I/O Registers
8.9.2 TIM Counter Registers (TCNTH:TCNTL)

The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: Read: Write: Reset: Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 0 $0022 Bit 7 Bit7 0 TCNTL 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0 0 0 0 0 0 0 $0021 Bit 7 Bit15 TCNTH 6 Bit14 5 Bit13 4 Bit12 3 Bit11 2 Bit10 1 Bit9 Bit 0 Bit8
Figure 8-5. TIM Counter Registers (TCNTH:TCNTL)
8.9.3 TIM Counter Modulo Registers (TMODH:TMODL)

The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: Read: Write: Reset: Address: Read: Write: Reset: $0023 Bit 7 Bit15 1 $0024 Bit 7 Bit7 1 TMODH 6 Bit14 1 TMODL 6 Bit6 1 5 Bit5 1 4 Bit4 1 3 Bit3 1 2 Bit2 1 1 Bit1 1 Bit 0 Bit0 1 5 Bit13 1 4 Bit12 1 3 Bit11 1 2 Bit10 1 1 Bit9 1 Bit 0 Bit8 1
Figure 8-6. TIM Counter Modulo Registers (TMODH:TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers.
8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)

Each of the TIM channel status and control registers does the following: Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
Address: Read: Write: Reset: Address: Read: Write: Reset: $0025 Bit 7 CH0F 0 0 $0028 Bit 7 CH1F 0 0 TSC0 6 CH0IE 0 TSC1 6 CH1IE 0 = Unimplemented 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1) CHxF Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a one to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled
I/O Registers
MSxB Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 8-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See Table 8-3.) Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 8-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 8-3. Mode, Edge, and Level Selection
MSxB X X 0 0 0 0 0 0 1 1 1 MSxA 0 1 0 0 0 1 1 1 X X X ELSxB 0 0 0 1 1 0 1 1 0 1 1 ELSxA 0 Output Preset 0 1 0 1 1 0 1 1 0 1 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare Mode Configuration Pin under Port Control; Initial Output Level High
NOTE Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks.
TOVx Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX Channel x Maximum Duty Cycle Bit When the TOVx bit is at one, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 8-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW PERIOD OVERFLOW OVERFLOW OVERFLOW OVERFLOW
TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 8-8. CHxMAX Latency
I/O Registers
8.9.5 TIM Channel Registers (TCH0H/L:TCH1H/L)

These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: $02A Bit 7 Bit7 TCH1L 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0 $0029 Bit 7 Bit15 TCH1H 6 Bit14 5 Bit13 4 Bit12 3 Bit11 2 Bit10 1 Bit9 Bit 0 Bit8 $0027 Bit 7 Bit7 TCH0L 6 Bit6 5 Bit5 4 Bit4 3 Bit3 2 Bit2 1 Bit1 Bit 0 Bit0 $0026 Bit 7 Bit15 TCH0H 6 Bit14 5 Bit13 4 Bit12 3 Bit11 2 Bit10 1 Bit9 Bit 0 Bit8
Figure 8-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
Chapter 9 Analog-to-Digital Converter (ADC)

9.1 Introduction
This section describes the 12-channel, 8-bit linear successive approximation analog-to-digital converter (ADC).
9.2 Features
Features of the ADC module include: 12 channels with multiplexed input Linear successive approximation with monotonicity 8-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock
Addr. $003C Register Name Read: ADC Status and Control Write: Register (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset: Read: $003E ADC Input Clock Register Write: (ADICLK) Reset: Bit 7 COCO 0 AD7 6 AIEN 0 AD6 5 ADCO 0 AD5 4 ADCH4 1 AD4 3 ADCH3 1 AD3 2 ADCH2 1 AD2 1 ADCH1 1 AD1 Bit 0 ADCH0 1 AD0
$003D
Indeterminate after reset ADIV2 0 ADIV1 0 = Unimplemented ADIV0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-1. ADC I/O Register Summary

Twelve ADC channels are available for sampling external sources at pins PTB0PTB7 and PTD0PTD3. An analog multiplexer allows the single ADC converter to select one of the 12 ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 9-2 shows a block diagram of the ADC.
Analog-to-Digital Converter (ADC)

INTERNAL DATA BUS READ DDRB/DDRD DISABLE RESET WRITE PTB/PTD PTBx/PTDx ADCx DDRBx/DDRDx
WRITE DDRB/DDRD
READ PTB/PTD
DISABLE ADC CHANNEL x ADC DATA REGISTER
INTERRUPT LOGIC
CONVERSION COMPLETE
ADC
ADC VOLTAGE IN ADCVIN
CHANNEL SELECT (1 OF 12 CHANNELS)
ADCH[4:0]
AIEN
COCO
ADC CLOCK
BUS CLOCK
CLOCK GENERATOR
ADIV[2:0]
ADICLK
Figure 9-2. ADC Block Diagram
9.3.1 ADC Port I/O Pins

PTB0PTB7 and PTD0PTD3 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register, $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is at 0. If the DDR bit is at 1, the value in the port data latch is read.
Interrupts
9.3.2 Voltage Conversion

When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS. NOTE Input voltage should not exceed the analog supply voltages.
9.3.3 Conversion Time

Fourteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1MHz, then one conversion will take 14s to complete. With a 1MHz ADC internal clock the maximum sample rate is 71.43kHz. 14 ADC Clock Cycles ADC Clock Frequency
Conversion Time =
Number of Bus Cycles = Conversion Time Bus Frequency
9.3.4 Continuous Conversion

In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC data register with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADC status and control register, $003C) is set after each conversion and can be cleared by writing the ADC status and control register or reading of the ADC data register.
9.3.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes.
9.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
9.5 Low-Power Modes

The following subsections describe the ADC in low-power modes.
9.5.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to 1s before executing the WAIT instruction.
9.5.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode.
9.6 I/O Signals

The ADC module has 12 channels that are shared with I/O port B and port D.
9.6.1 ADC Voltage In (ADCVIN)

ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module.
9.7 I/O Registers

These I/O registers control and monitor ADC operation: ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADICLK)
9.7.1 ADC Status and Control Register

The following paragraphs describe the function of the ADC status and control register.
Address: Read: Write: Reset: 0 $003C Bit 7 COCO 6 AIEN 0 5 ADCO 0 4 ADCH4 1 3 ADCH3 1 2 ADCH2 1 1 ADCH1 1 Bit 0 ADCH0 1
= Unimplemented
Figure 9-3. ADC Status and Control Register (ADSCR) COCO Conversions Complete Bit When the AIEN bit is a 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read. Reset clears this bit. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) When the AIEN bit is a 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be 0 when read. AIEN ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled
I/O Registers
ADCO ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] ADC Channel Select Bits ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select bits are detailed in the following table. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a 1. NOTE Recovery from the disabled state requires one conversion cycle to stabilize. Table 9-1. MUX Channel Select
ADCH4 0 0 0 0 0 0 0 0 0 0 0 0 0 : 1 1 1 1 1 1 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 : 1 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 : 0 0 1 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 : 1 1 0 0 1 1 ADCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 : 0 1 0 1 0 1 Reserved Unused VDDA (see Note 2) VSSA (see Note 2) ADC power off Unused (see Note 1) ADC Channel ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 Input Select PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTD3 PTD2 PTD1 PTD0
1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications.
9.7.2 ADC Data Register

One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: Read: Write: Reset: = Unimplemented Indeterminate after reset $003D Bit 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
Figure 9-4. ADC Data Register (ADR)
9.7.3 ADC Input Clock Register

This register selects the clock frequency for the ADC
Address: Read: Write: Reset: $003E Bit 7 ADIV2 0 6 ADIV1 0 5 ADIV0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 9-5. ADC Input Clock Register (ADICLK) ADIV[2:0] ADC Clock Prescaler Bits ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 9-2 shows the available clock configurations. The ADC clock should be set to approximately 1MHz. Table 9-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 X = dont care ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC Input Clock 1 ADC Input Clock 2 ADC Input Clock 4 ADC Input Clock 8 ADC Input Clock 16
Chapter 10 Input/Output (I/O) Ports

10.1 Introduction
Twenty three (23) bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 20-pin devices have non-bonded pins. These pins should be configured either as outputs driving low or high, or as inputs with internal pullups enabled. Configuring these non-bonded pins in this manner will prrevent any excess current compsumption caused by floating inputs.
Addr. $0000 Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read: $0005 Data Direction Register B Write: (DDRB) Reset: Read: Data Direction Register D Write: (DDRD) Reset: PTB7 Bit 7 0 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset 0 0 DDRB7 0 DDRD7 0 DDRA6 0 DDRB6 0 DDRD6 0 DDRA5 0 DDRB5 0 DDRD5 0 DDRA4 0 DDRB4 0 DDRD4 0 DDRA3 0 DDRB3 0 DDRD3 0 DDRA2 0 DDRB2 0 DDRD2 0 DDRA1 0 DDRB1 0 DDRD1 0 DDRA0 0 DDRB0 0 DDRD0 0
$0004
$0007
Figure 10-1. I/O Port Register Summary
Input/Output (I/O) Ports Addr. $000A Register Name Read: Port D Control Register Write: (PDCR) Reset: Port A Input Pull-up Enable Read: Register Write: (PTAPUE) Reset: Bit 7 0 0 PTA6EN 0 6 0 0 PTAPUE6 0 = Unimplemented 5 0 0 PTAPUE5 0 4 0 0 PTAPUE4 0 3 SLOWD7 0 PTAPUE3 0 2 SLOWD6 0 PTAPUE2 0 1 PTDPU7 0 PTAPUE1 0 Bit 0 PTDPU6 0 PTAPUE0 0
$000D
Figure 10-1. I/O Port Register Summary
Table 10-1. Port Control Register Bits Summary

Port Bit 0 1 2 A 3 4 5 6 0 1 2 B 3 4 5 6 7 0 1 2 D 3 4 5 6 7 DDR DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DDRD0 DDRD1 DDRD2 DDRD3 DDRD4 DDRD5 DDRD6 DDRD7 TIM TSC0 ($0025) TSC1 ($0028) ELS0B:ELS0A ELS1B:ELS1A ADC ADSCR ($003C) ADCH[4:0] ADC ADSCR ($003C) ADCH[4:0] KBI KBIER ($001B) Module Control Module Register Pin PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 RCCLK/PTA6/KBI6(1) PTB0/ADC0 PTB1/ADC1 PTB2/ADC2 PTB3/ADC3 PTB4/ADC4 PTB5/ADC5 PTB6/ADC6 PTB7/ADC7 PTD0/ADC11 PTD1/ADC10 PTD2/ADC9 PTD3/ADC8 PTD4/TCH0 PTD5/TCH1 PTD6 PTD7
Control Bit
KBIE0 KBIE1 KBIE2 KBIE3 KBIE4 KBIE5
OSC KBI
PTAPUE ($000D) KBIER ($001B)
PTA6EN KBIE6
1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option); PTAPUE register has priority control over the port pin. RCCLK/PTA6/KBI6 is the OSC2 pin on MC68HC908JL3E/JK3E/JK1E devices (X-TAL option).
Port A
10.2 Port A
Port A is an 7-bit special function port that shares all seven of its pins with the keyboard interrupt (KBI) module (see Chapter 12 Keyboard Interrupt Module (KBI)). Each port A pin also has software configurable pull-up device if the corresponding port pin is configured as input port. PTA0 to PTA5 has direct LED drive capability. NOTE PTA0PTA5 pins are available on MC68H(R)C908JL3E only. PTA6 pin is available on MC68HRC908JL3E/JK3E/JK1E only.
10.2.1 Port A Data Register (PTA)

The port A data register (PTA) contains a data latch for each of the seven port A pins.
Address: Read: Write: Reset: Additional Functions: LED (Sink) Keyboard Interrupt Keyboard Interrupt $0000 Bit 7 0 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by Reset LED (Sink) Keyboard Interrupt LED (Sink) Keyboard Interrupt LED (Sink) Keyboard Interrupt LED (Sink) Keyboard Interrupt LED (Sink) Keyboard Interrupt
30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up
= Unimplemented
Figure 10-2. Port A Data Register (PTA) PTA[6:0] Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI[6:0] Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE[6:0], in the keyboard interrupt control register (KBIER) enable the port A pins as external interrupt pins, (see Chapter 12 Keyboard Interrupt Module (KBI)).
Input/Output (I/O) Ports
10.2.2 Data Direction Register A (DDRA)

Data direction register A determines whether each port A pin is an input or an output. Writing a one to a DDRA bit enables the output buffer for the corresponding port A pin; a zero disables the output buffer.
Address: Read: Write: Reset: 0 $0004 Bit 7 0 6 DDRA6 0 = Unimplemented 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0
Figure 10-3. Data Direction Register A (DDRA) DDRA[6:0] Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[6:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 10-4 shows the port A I/O logic.
READ DDRA ($0004) PTAPUEx WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx 30k
READ PTA ($0000)
To Keyboard Interrupt Circuit
Figure 10-4. Port A I/O Circuit When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
Port A
10.2.3 Port A Input Pull-up Enable Register (PTAPUE)

The port A input pull-up enable register (PTAPUE) contains a software configurable pull-up device for each of the seven port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx be configured as input. Each pull-up device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output.
Address: Read: Write: Reset: $000D Bit 7 PTA6EN 0 6 PTAPUE6 0 5 PTAPUE5 0 4 PTAPUE4 0 3 PTAPUE3 0 2 PTAPUE2 0 1 PTAPUE1 0 Bit 0 PTAPUE0 0
Figure 10-5. Port A Input Pull-up Enable Register (PTAPUE) PTA6EN Enable PTA6 on OSC2 This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has no effect for X-tal oscillator option. 1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions 0 = OSC2 pin outputs the RC oscillator clock (RCCLK) PTAPUE[6:0] Port A Input Pull-up Enable Bits These read/write bits are software programmable to enable pull-up devices on port A pins 1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0 0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Table 10-2 summarizes the operation of the port A pins. Table 10-2. Port A Pin Functions
PTAPUE Bit 1 0 X DDRA Bit 0 0 1 Accesses to DDRA PTA Bit X
(1)
Accesses to PTA Read Pin Pin PTA[6:0] Write PTA[6:0](3) PTA[6:0](3) PTA[6:0]
I/O Pin Mode Read/Write Input, VDD(2) DDRA[6:0] DDRA[6:0] DDRA[6:0]
X X
Input, Hi-Z(4) Output
1. X = Dont care. 2. I/O pin pulled to VDD by internal pull-up. 3. Writing affects data register, but does not affect input. 4. Hi-Z = High Impedance.
10.3 Port B
Port B is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital converter (ADC) module, see Chapter 9 Analog-to-Digital Converter (ADC).
10.3.1 Port B Data Register (PTB)

The port B data register contains a data latch for each of the eight port B pins.
Address: Read: Write: Reset: Alternative Function: ADC7 ADC6 AD4C5 $0001 Bit 7 PTB7 6 PTB6 5 PTB5 4 PTB4 3 PTB3 2 PTB2 1 PTB1 Bit 0 PTB0
Unaffected by reset ADC4 ADC3 ADC2 ADC2 ADC0
Figure 10-6. Port B Data Register (PTB) PTB[7:0] Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. ADC[7:0] ADC channels 7 to 0 ADC[7:0] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Chapter 9 Analog-to-Digital Converter (ADC).
10.3.2 Data Direction Register B (DDRB)

Data direction register B determines whether each port B pin is an input or an output. Writing a one to a DDRB bit enables the output buffer for the corresponding port B pin; a zero disables the output buffer.
Address: Read: Write: Reset: $0005 Bit 7 DDRB7 0 6 DDRB6 0 5 DDRB5 0 4 DDRB4 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0
Figure 10-7. Data Direction Register B (DDRB) DDRB[7:0] Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1.
Port B
READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001) To Analog-To-Digital Converter
Figure 10-8. Port B I/O Circuit When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-3 summarizes the operation of the port B pins. Table 10-3. Port B Pin Functions
Accesses to DDRB DDRB Bit 0 1 PTB Bit X(1) X I/O Pin Mode Read/Write Input, Hi-Z(2) Output DDRB[7:0] DDRB[7:0] Read Pin Pin Write PTB[7:0](3) PTB[7:0] Accesses to PTB
1. X = dont care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
10.4 Port D
Port D is an 8-bit special function port that shares two of its pins with timer interface module, (see Chapter 8 Timer Interface Module (TIM)) and shares four of its pins with analog-to-digital converter module (see Chapter 9 Analog-to-Digital Converter (ADC)). PTD6 and PTD7 each has high current drive (25mA sink) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED driving (sink) capability. NOTE PTD0PTD1 are available on MC68H(R)C908JL3E only.
10.4.1 Port D Data Register (PTD)

The port D data register contains a data latch for each of the eight port D pins.
Address: Read: Write: Reset: Additional Functions: LED (Sink) LED (Sink) TCH1
25mA sink 25mA sink (Slow Edge) (Slow Edge)
$0003 Bit 7 PTD7 6 PTD6 5 PTD5 4 PTD4 3 PTD3 2 PTD2 1 PTD1 Bit 0 PTD0
Unaffected by reset LED (Sink) ADC8 TCH0 LED (Sink) ADC9 ADC10 ADC11
5k pull-up
5k pull-up = Unimplemented
Figure 10-9. Port D Data Register (PTD) PTD[7:0] Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. ADC[11:8] ADC channels 11 to 8 ADC[11:8] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an ADC input and overrides any control from the port I/O logic. See Chapter 9 Analog-to-Digital Converter (ADC). TCH[1:0] Timer Channel I/O The TCH1 and TCH0 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTD4/TCH0 and PTD5/TCH1 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 8 Timer Interface Module (TIM).
Port D
10.4.2 Data Direction Register D (DDRD)

Data direction register D determines whether each port D pin is an input or an output. Writing a one to a DDRD bit enables the output buffer for the corresponding port D pin; a zero disables the output buffer.
Address: Read: Write: Reset: $0007 Bit 7 DDRD7 0 6 DDRD6 0 5 DDRD5 0 4 DDRD4 0 3 DDRD3 0 2 DDRD2 0 1 DDRD1 0 Bit 0 DDRD0 0
Figure 10-10. Data Direction Register D (DDRD) DDRD[7:0] Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 10-11 shows the port D I/O logic.
READ DDRD ($0007) PTDPU[6:7] WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx 5k
READ PTD ($0003)
PTD[0:3] To Analog-To-Digital Converter PTD[4:5] To Timer
Figure 10-11. Port D I/O Circuit When DDRDx is a 1, reading address $0003 reads the PTDx data latch. When DDRDx is a 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 10-4 summarizes the operation of the port D pins.
Table 10-4. Port D Pin Functions

DDRD Bit 0 1 PTD Bit X
(1)
I/O Pin Mode Input, Hi-Z Output

(2)
Accesses to DDRD Read/Write DDRD[7:0] DDRD[7:0]
Accesses to PTD Read Pin Pin Write PTD[7:0](3) PTD[7:0]
1. X = dont care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
10.4.3 Port D Control Register (PDCR)

The port D control register enables/disables the pull-up resistor and slow-edge high current capability of pins PTD6 and PTD7.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $000A Bit 7 0 6 0 5 0 4 0 3 SLOWD7 0 2 SLOWD6 0 1 PTDPU7 0 Bit 0 PTDPU6 0
Figure 10-12. Port D Control Register (PDCR) SLOWDx Slow Edge Enable The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink) of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx. 1 = Slow edge enabled; pin is open-drain output 0 = Slow edge disabled; pin is push-pull PTDPUx Pull-up Enable The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and PTD7 respectively, regardless the status of DDRDx bit. 1 = Enable 5k pull-up 0 = Disable 5k pull-up
Chapter 11 External Interrupt (IRQ)

11.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
11.2 Features
Features of the IRQ module include the following: A dedicated external interrupt pin, IRQ IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Selectable internal pullup resistor

A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 11-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: Vector fetch A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a one to the ACK bit clears the IRQ latch. Reset A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: Vector fetch or software clear Return of the interrupt pin to logic one
External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to one. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. See 5.5 Exception Control.
ACK RESET INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD IRQPUD INTERNAL PULLUP DEVICE IRQ VDD D CLR Q SYNCHRONIZER IRQF TO CPU FOR BIL/BIH INSTRUCTIONS
CK IRQ FF IMASK
IRQ INTERRUPT REQUEST
MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 11-1. IRQ Module Block Diagram

Addr. $001D Register Name Read: IRQ Status and Control Write: Register (INTSCR) Reset: Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 IRQF 0 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Figure 11-2. IRQ I/O Register Summary
IRQ Module During Break Interrupts
11.3.1 IRQ Pin

A zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to logic one As long as the IRQ pin is at logic zero, IRQ remains active. The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE An internal pull-up resistor to VDD is connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
11.4 IRQ Module During Break Interrupts

The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Chapter 5 System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a one to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a zero to the BCFE bit. With BCFE at zero (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
External Interrupt (IRQ)
11.5 IRQ Status and Control Register (INTSCR)

The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR has the following functions: Shows the state of the IRQ flag Clears the IRQ latch Masks IRQ and interrupt request Controls triggering sensitivity of the IRQ interrupt pin
Address: Read: Write: Reset: 0 0 0 0 0 = Unimplemented $001D Bit 7 0 6 0 5 0 4 0 3 IRQF ACK 0 2 1 IMASK 0 Bit 0 MODE 0
Figure 11-3. IRQ Status and Control Register (INTSCR) IRQF IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK IRQ Interrupt Request Acknowledge Bit Writing a one to this write-only bit clears the IRQ latch. ACK always reads as zero. Reset clears ACK. IMASK IRQ Interrupt Mask Bit Writing a one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
Address: Read: Write: Reset: POR: $001E Bit 7 IRQPUD 0 0 R 6 R 0 0 = Reserved 5 R 0 0 4 LVIT1
Not affected
3 LVIT0
Not affected
2 R 0 0
1 R 0 0
Bit 0 R 0 0
Figure 11-4. Configuration Register 2 (CONFIG2) IRQPUD IRQ Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD
Chapter 12 Keyboard Interrupt Module (KBI)

12.1 Introduction
The keyboard interrupt module (KBI) provides seven independently maskable external interrupts which are accessible via PTA0PTA6 pins.
12.2 Features
Features of the keyboard interrupt module include the following: Seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Software configurable pull-up device if input pin is configured as input port bit Programmable edge-only or edge- and level- interrupt sensitivity Exit from low-power modes
Addr. Register Name Bit 7 0 0 0 0 6 0 0 KBIE6 0 = Unimplemented 5 0 0 KBIE5 0 4 0 0 KBIE4 0 3 KEYF 0 KBIE3 0 2 0 ACKK 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
Read: Keyboard Status and Control $001A Write: Register (KBSCR) Reset: Read: $001B Keyboard Interrupt Enable Write: Register (KBIER) Reset:
Figure 12-1. KBI I/O Register Summary
12.3 I/O Pins

The seven keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 12-1. The generic pin name appear in the text that follows. Table 12-1. Pin Name Conventions
KBI Generic Pin Name KBI0KBI5 KBI6 Full MCU Pin Name PTA0/KBI0PTA5/KBI5 RCCLK/PTA6/KBI6(1) Pin Selected for KBI Function by KBIEx Bit in KBIER KBIE0KBIE5 KBIE6
1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option).
Keyboard Interrupt Module (KBI)

INTERNAL BUS
KBI0 VDD . KBIE0 TO PULLUP ENABLE . KBI6 . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST
CK
KEYBOARD INTERRUPT FF
IMASKK
MODEK KBIE6 TO PULLUP ENABLE
Figure 12-2. Keyboard Interrupt Block Diagram Writing to the KBIE6KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pull-up device irrespective of PTAPUEx bits in the port A input pull-up enable register (see 10.2.3 Port A Input Pull-up Enable Register (PTAPUE)). A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. Return of all enabled keyboard interrupt pins to logic 1 As long as any enabled keyboard interrupt pin is at 0, the keyboard interrupt remains set.
Keyboard Interrupt Registers
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction register to configure the pin as an input and then read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a 0 for software to read the pin.
12.4.1 Keyboard Initialization

When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
12.5 Keyboard Interrupt Registers

Two registers control the operation of the keyboard interrupt module: Keyboard status and control register Keyboard interrupt enable register
12.5.1 Keyboard Status and Control Register

Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
Address: Read: Write: Reset: 0 0 0 0 0 = Unimplemented $001A Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 1 IMASKK 0 Bit 0 MODEK 0
Figure 12-3. Keyboard Status and Control Register (KBSCR) KEYF Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port-A. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard interrupt request on port-A. ACKK always reads as 0. Reset clears ACKK. IMASKK Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port-A. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port-A. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
Low-Power Modes
12.5.2 Keyboard Interrupt Enable Register

The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin.
Address: Read: Write: Reset: 0 $001B Bit 7 0 6 KBIE6 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
= Unimplemented
Figure 12-4. Keyboard Interrupt Enable Register (KBIER) KBIE6KBIE0 Port-A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin
12.6 Low-Power Modes

12.6.1 Wait Mode

The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
12.6.2 Stop Mode

The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
12.7 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect.
Chapter 13 Computer Operating Properly (COP)

13.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register.

Figure 13-1 shows the structure of the COP module.
SIM 2OSCOUT 12-BIT SIM COUNTER CLEAR STAGES 512 SIM RESET CIRCUIT RESET STATUS REGISTER
CLEAR ALL STAGES
INTERNAL RESET SOURCES(1) RESET VECTOR FETCH COPCTL WRITE
COP CLOCK
COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) CLEAR COP COUNTER
NOTE: See Chapter 5 System Integration Module (SIM) for more details.
Figure 13-1. COP Block Diagram
COP TIMEOUT
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 2OSCOUT cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout period of 32.766 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 2OSCOUT cycles and sets the COP bit in the reset status register (RSR). (See 5.7.2 Reset Status Register (RSR).). NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
13.3 I/O Signals

The following paragraphs describe the signals shown in Figure 13-1.
13.3.1 2OSCOUT
2OSCOUT is the oscillator output signal. 2OSCOUT frequency is equal to the crystal frequency or the RC-oscillator frequency.
13.3.2 COPCTL Write

Writing any value to the COP control register (COPCTL) (see 13.4 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector.
13.3.3 Power-On Reset

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 2OSCOUT cycles after power-up.
13.3.4 Internal Reset

An internal reset clears the SIM counter and the COP counter.
13.3.5 Reset Vector Fetch

A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter.
13.3.6 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). (See Chapter 3 Configuration Registers (CONFIG).)
COP Control Register
13.3.7 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
Figure 13-2. Configuration Register 1 (CONFIG1) COPRS COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is 8176 2OSCOUT cycles 0 = COP timeout period is 262,128 2OSCOUT cycles COPD COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
13.4 COP Control Register

The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: Read: Write: Reset: $FFFF Bit 7 6 5 4 3 2 1 Bit 0 Low byte of reset vector Clear COP counter Unaffected by reset
Figure 13-3. COP Control Register (COPCTL)
13.5 Interrupts
The COP does not generate CPU interrupt requests.
13.6 Monitor Mode

The COP is disabled in monitor mode when VTST is present on the IRQ pin or on the RST pin.

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
Computer Operating Properly (COP)
13.7.1 Wait Mode

The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
13.7.2 Stop Mode

Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
13.8 COP Module During Break Mode

The COP is disabled during a break interrupt when VTST is present on the RST pin.
Chapter 14 Low Voltage Inhibit (LVI)

14.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage.
14.2 Features
Features of the LVI module include the following: Selectable LVI trip voltage Selectable LVI circuit disable

Figure 14-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which VDD level the LVI module should take actions. The LVI module generates one output signal: LVI Reset an reset signal will be generated to reset the CPU when VDD drops to below the set trip point.
VDD
LVID
VDD > LVITRIP = 0 LOW VDD DETECTOR VDD < LVITRIP = 1
LVI RESET
LVIT1
LVIT0
Figure 14-1. LVI Module Block Diagram
Low Voltage Inhibit (LVI)
14.4 LVI Control Register (CONFIG2/CONFIG1)

The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2.
Address: Read: Write: Reset: POR: $001E Bit 7 IRQPUD 0 0 R 6 R 0 0 = Reserved 5 R 0 0 4 LVIT1
Not affected
3 LVIT0
Not affected
2 R 0 0
1 R 0 0
Bit 0 R 0 0
Figure 14-2. Configuration Register 2 (CONFIG2)

Figure 14-3. Configuration Register 1 (CONFIG1) LVID Low Voltage Inhibit Disable Bit 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled LVIT1, LVIT0 LVI Trip Voltage Selection These two bits determine at which level of VDD the LVI module will come into action. LVIT1 and LVIT0 are cleared by a Power-On Reset only.
LVIT1 0 0 1 1 LVIT0 0 1 0 1 Trip Voltage(1) VLVR3 (2.4V) VLVR3 (2.4V) VLVR5 (4.0V) Reserved Comments For VDD =3V operation For VDD =3V operation For VDD =5V operation
1. See Chapter 16 Electrical Specifications for full parameters.

The STOP and WAIT instructions put the MCU in low-power-consumption standby modes.
14.5.1 Wait Mode

The LVI module, when enabled, will continue to operate in WAIT Mode.
14.5.2 Stop Mode

The LVI module, when enabled, will continue to operate in STOP Mode.
Chapter 15 Break Module (BREAK)

15.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
15.2 Features
Features of the break module include the following: Accessible I/O registers during the break Interrupt CPU-generated break interrupts Software-generated break interrupts COP disabling during break interrupts

When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a one to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 15-1 shows the structure of the break module.
IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] BKPT (TO SIM)
Figure 15-1. Break Module Block Diagram

Break Module (BREAK)
Addr. $FE00
Register Name Read: Break Status Register Write: (BSR) Reset: Break Flag Control Read: Register Write: (BFCR) Reset: Break Address High Read: Register Write: (BRKH) Reset: Break Address low Read: Register Write: (BRKL) Reset: Break Status and Control Read: Register Write: (BRKSCR) Reset:
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW See note 0
Bit 0 R
$FE03
BCFE 0 Bit15 0 Bit7 0 BRKE 0
$FE0C
Bit14 0 Bit6 0 BRKA 0
Bit13 0 Bit5 0 0 0
Bit12 0 Bit4 0 0 0 R
Bit11 0 Bit3 0 0 0 = Reserved
Bit10 0 Bit2 0 0 0
Bit9 0 Bit1 0 0 0
Bit8 0 Bit0 0 0 0
$FE0D
$FE0E
Note: Writing a 0 clears SBSW.
= Unimplemented
Figure 15-2. Break I/O Register Summary
15.3.1 Flag Protection During Break Interrupts

The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR) and see the Break Interrupts subsection for each module.)
15.3.2 CPU During Break Interrupts

The CPU starts a break interrupt by: Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
15.3.3 TIM During Break Interrupts

A break interrupt stops the timer counter.
15.3.4 COP During Break Interrupts

The COP is disabled during a break interrupt when VTST is present on the RST pin.
Break Module Registers
15.4 Break Module Registers

These registers control and monitor operation of the break module: Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) Break status register (BSR) Break flag control register (BFCR)
15.4.1 Break Status and Control Register (BRKSCR)

The break status and control register contains break module enable and status bits.
Address: Read: Write: Reset: $FE0E Bit 7 BRKE 0 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 15-3. Break Status and Control Register (BRKSCR) BRKE Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a zero to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a one to BRKA generates a break interrupt. Clear BRKA by writing a zero to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
15.4.2 Break Address Registers

The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: Read: Write: Reset: $FE0C Bit 7 Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0
Figure 15-4. Break Address Register High (BRKH)

Address: Read: Write: Reset: $FE0D Bit 7 Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
Figure 15-5. Break Address Register Low (BRKL)
15.4.3 Break Status Register

The break status register contains a flag to indicate that a break caused an exit from wait mode.
Address: Read: Write: Reset: R = Reserved 1. Writing a zero clears SBSW. $FE00 Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 Bit 0 R
Figure 15-6. Break Status Register (BSR) SBSW SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt
Low-Power Modes
15.4.4 Break Flag Control Register (BFCR)

The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 15-7. Break Flag Control Register (BFCR) BCFE Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break

The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
15.5.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see 5.6 Low-Power Modes). Clear the SBSW bit by writing zero to it.
15.5.2 Stop Mode

A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 5.7 SIM Registers.
Chapter 16 Electrical Specifications

16.1 Introduction
This section contains electrical and timing specifications.
16.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 5V DC Electrical Characteristics and 16.8 3V DC Electrical Characteristics for guaranteed operating conditions. Table 16-1. Absolute Maximum Ratings
Characteristic(1) Supply voltage Input voltage Mode entry voltage, IRQ pin Maximum current per pin excluding VDD and VSS Storage temperature Maximum current out of VSS Maximum current into VDD 1. Voltages referenced to VSS. Symbol VDD VIN VTST I TSTG IMVSS IMVDD Value 0.3 to +6.0 VSS 0.3 to VDD +0.3 VSS 0.3 to +8.5 25 55 to +150 100 100 Unit V V V mA C mA mA
NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.)
Electrical Specifications
16.3 Functional Operating Range

Table 16-2. Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD 40 to +125 5 10% Value 40 to +85 3 10% Unit C V
16.4 Thermal Characteristics

Table 16-3. Thermal Characteristics
Characteristic Thermal resistance 20-pin PDIP 20-pin SOIC 28-pin PDIP 28-pin SOIC 48-pin LQFP I/O pin power dissipation Power dissipation(1) Constant(2) Average junction temperature Symbol Value 70 70 70 70 80 User determined PD = (IDD VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 JA TA + (PD JA) Unit C/W C/W C/W C/W C/W W W W/C C
JA
PI/O PD K TJ
1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
5V DC Electrical Characteristics
16.5 5V DC Electrical Characteristics

Table 16-4. DC Electrical Characteristics (5V)
Characteristic(1) Output high voltage (ILOAD = 2.0mA) PTA0PTA6, PTB0PTB7, PTD0PTD7 Output low voltage (ILOAD = 1.6mA) PTA6, PTB0PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (ILOAD = 25mA) PTD6, PTD7 LED drives (VOL = 3V) PTA0PTA5, PTD2, PTD3, PTD6, PTD7 Input high voltage PTA0PTA6, PTB0PTB7, PTD0PTD7, RST, IRQ, OSC1 Input low voltage PTA0PTA6, PTB0PTB7, PTD0PTD7, RST, IRQ, OSC1 VDD supply current, fOP = 4MHz Run(3) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Wait(4) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Stop(5) (40C to 85C) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E (40C to 125C) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate(7) Monitor mode entry voltage Pullup resistors(8) PTD6, PTD7 RST, IRQ, PTA0PTA6 Symbol VOH VOL VOL IOL Min VDD 0.8 10 Typ(2) 16 Max 0.4 0.5 22 Unit V V V mA
VIH
0.7 VDD
VDD
VIL
VSS
0.3 VDD
10 4.5 6 1
11 5 6.5 1.5
mA mA mA mA A A A A A A pF mV V/ms V k k
IDD
IIL IIN COUT CIN VPOR RPOR VTST RPU1 RPU2 0 0.035 1.5 VDD 1.8 16
2 2 2 2 3.3 26
5 5 10 10 10 1 12 8 100 8.5 4.8 36
Table continued on next page
Table 16-4. DC Electrical Characteristics (5V) (Continued)

Characteristic(1) LVI reset voltage Symbol VLVR5 Min 3.6 Typ(2) 4.0 Max 4.4 Unit V
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V.
16.6 5V Control Timing

Table 16-5. Control Timing (5V)
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min 750 Max 8 Unit MHz ns
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
5V Oscillator Characteristics
16.7 5V Oscillator Characteristics

Table 16-6. Oscillator Component Specifications (5V)
Characteristic Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1) Crystal load capacitance(2) Crystal fixed capacitance(2) Crystal tuning capacitance(2) Feedback bias resistor Series resistor(2), (3) RC oscillator external R RC oscillator external C 1. No more than 10% duty cycle deviation from 50%. 2. Consult crystal vendor data sheet. 3. Not required for high frequency crystals. Symbol fOSCXCLK fRCCLK fOSCXCLK CL C1 C2 RB RS REXT CEXT Min 2 dc Typ 10 10 2 CL 2 CL 10 M See Figure 16-1 10 pF Max 32 12 32 Unit MHz MHz MHz
14 12 RC FREQUENCY, fRCCLK (MHz) CEXT = 10 pF 10 8 6 VDD 4 2 0 0 10 20 30 40 50 RESISTOR, REXT (k) REXT CEXT 5V @ 25 C OSC1 MCU
Figure 16-1. RC vs. Frequency (5V @25 C)
16.8 3V DC Electrical Characteristics

Table 16-7. DC Electrical Characteristics (3V)
Characteristic(1) Output high voltage (ILOAD = 1.0mA) PTA0PTA6, PTB0PTB7, PTD0PTD7 Output low voltage (ILOAD = 0.8mA) PTA6, PTB0PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (ILOAD = 20mA) PTD6, PTD7 LED drives (VOL = 1.8V) PTA0PTA5, PTD2, PTD3, PTD6, PTD7 Input high voltage PTA0PTA6, PTB0PTB7, PTD0PTD7, RST, IRQ, OSC1 Input low voltage PTA0PTA6, PTB0PTB7, PTD0PTD7, RST, IRQ, OSC1 VDD supply current, fOP = 2MHz Run(3) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Wait(4) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Stop(5) (40C to 85C) MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate(7) Monitor mode entry voltage Pullup resistors(8) PTD6, PTD7 RST, IRQ, PTA0PTA6 Symbol VOH VOL VOL IOL Min VDD 0.4 Typ(2) Max Unit V
0.4
0.5
10
mA
VIH
0.7 VDD
VDD
VIL
VSS
0.3 VDD
IDD
3 1.5 1.5 0.2
3.5 2 2 0.3
mA mA mA mA A A A A pF mV V/ms V k k
IIL IIN COUT CIN VPOR RPOR VTST RPU1 RPU2 0 0.035 1.5 VDD
1 1
5 5 10 1 12 8 100 8.5
1.8 16
3.3 26
4.8 36
Table continued on next page
3V Control Timing
Table 16-7. DC Electrical Characteristics (3V) (Continued)

Characteristic(1) LVI reset voltage Symbol VLVR3 Min 2.0 Typ(2) 2.4 Max 2.69 Unit V
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V.
16.9 3V Control Timing

Table 16-8. Control Timing (3V)
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min 1.5 Max 4 Unit MHz s
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
16.10 3V Oscillator Characteristics

Table 16-9. Oscillator Component Specifications (3V)
Characteristic Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1) Crystal load capacitance(2) Crystal fixed capacitance(2) Crystal tuning capacitance(2) Feedback bias resistor Series resistor(2), (3) RC oscillator external R RC oscillator external C 1. No more than 10% duty cycle deviation from 50%. 2. Consult crystal vendor data sheet. 3. Not required for high frequency crystals. Symbol fOSCXCLK fRCCLK fOSCXCLK CL C1 C2 RB RS REXT CEXT Min 2 dc Typ 8 8 2 CL 2 CL 10 M See Figure 16-2 10 pF Max 16 12 16 Unit MHz MHz MHz
14 12 RC FREQUENCY, fRCCLK (MHz) 10 8 6 VDD 4 2 0 0 10 20 30 40 50 RESISTOR, REXT (k) REXT CEXT CEXT = 10 pF 3V @ 25 C OSC1 MCU
Figure 16-2. RC vs. Frequency (3V @25 C)
Typical Supply Currents
16.11 Typical Supply Currents

14 12 10 IDD (mA) 8 6 4 2 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 9 MC68HC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 16-3. Typical Operating IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned On (25C)
10 8 IDD (mA) 6 4 2 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 9 MC68HRC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 16-4. Typical Operating IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned On (25C)
10 8 IDD (mA) 6 4 2 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 9 MC68HC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 16-5. Typical Wait Mode IDD (MC68HC908JL3E/JK3E/JK1E), with All Modules Turned Off (25C)
2 1.75 1.50 1.25 IDD (mA) 1 0.75 0.5 0.25 0 0 1 2 3 4 fOP or fBUS (MHz) 5 6 7 8 MC68HRC908JL3E/JK3E/JK1E 5.5 V 3.3 V
Figure 16-6. Typical Wait Mode IDD (MC68HRC908JL3E/JK3E/JK1E), with All Modules Turned Off (25 C)
16.12 ADC Characteristics

Table 16-10. ADC Characteristics
Characteristic Supply voltage Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(1)
(2)
Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI
Min 2.7 (VDD min) VSS 8 0.5 0.5 VSS 16 14 5 00 FE
Max 5.5 (VDD max) VDD 8 1.5 1.048 VDD
Unit V V Bits LSB MHz V tAIC cycles
Comments
Includes quantization tAIC = 1/fADIC, tested only at 1 MHz
15 01 FF (20) 8 1
tAIC cycles tAIC cycles Hex Hex pF A VIN = VSS VIN = VDD Not tested
Zero input reading Full-scale
reading(3)
Input capacitance Input Port B/port D leakage(3)
1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
Memory Characteristics
16.13 Memory Characteristics

Table 16-11. Memory Characteristics
Characteristic RAM data retention voltage Flash program bus clock frequency Flash read bus clock frequency Flash page erase time Flash mass erase time Flash PGM/ERASE to HVEN set up time Flash high-voltage hold time Flash high-voltage hold time (mass erase) Flash program hold time Flash program time Flash return to read time Flash cumulative program hv period Flash row erase endurance(6) Flash row program endurance Flash data retention time(8)
(7)
Symbol VRDR fRead(1) tErase(2) tMErase(3) tnvs tnvh tnvh1 tpgs tPROG trcv(4) tHV(5)
Min 1.3 1 32k 1 4 10 5 100 5 30 1 10k 10k 10
Max 8M 40 4
Unit V MHz Hz ms ms s s s s s s ms cycles cycles years
1. fRead is defined as the frequency range for which the Flash memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the Flash memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the Flash memory. 4. trcv is defined as the time it needs before the Flash can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG 32) tHV max. 6. The minimum row endurance value specifies each row of the Flash memory is guaranteed to work for at least this many erase / program cycles. 7. The minimum row endurance value specifies each row of the Flash memory is guaranteed to work for at least this many erase / program cycles. 8. The Flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
Chapter 17 Mechanical Specifications

17.1 Introduction
This section gives the dimensions for: 20-pin plastic dual in-line package (case #738) 20-pin small outline integrated circuit package (case #751D) 28-pin plastic dual in-line package (case #710) 28-pin small outline integrated circuit package (case #751F) 48-pin low-profile quad flat pack (case #932) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Sales Office.
17.2 Package Dimensions

Refer to the following pages for detailed package dimensions.
A
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
T
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) T A
M
T B
DIM A B C D E F G J K L M N
20-Pin PDIP (Case #738)
Mechanical Specifications
Chapter 18 Ordering Information

18.1 Introduction
This section contains ordering numbers for the MC68H(R)C908JL3E, MC68H(R)C908JK3E, and MC68H(R)C908JK1E.
18.2 MC Order Numbers

Table 18-1. MC Order Numbers
MC Order Number MC68HC908JL3ECFA MC68HC908JL3EMFA MC68HRC98JL3ECFA MC68HRC98JL3EMFA MC68HC908JL3ECP MC68HC908JL3EMP MC68HC908JL3ECDW MC68HC908JL3EMDW MC68HRC98JL3ECP MC68HRC98JL3EMP MC68HRC98JL3ECDW MC68HRC98JL3EMDW MC68HC908JK3ECP MC68HC908JK3EMP MC68HC908JK3ECDW MC68HC908JK3EMDW MC68HRC98JK3ECP MC68HRC98JK3EMP MC68HRC98JK3ECDW MC68HRC98JK3EMDW MC68HC908JK1ECP MC68HC908JK1EMP MC68HC908JK1ECDW MC68HC908JK1EMDW MC68HRC98JK1ECP MC68HRC98JK1EMP MC68HRC98JK1ECDW MC68HRC98JK1EMDW Oscillator Type Crystal oscillator 4096 Bytes RC oscillator 48-pin LQFP Flash Memory Package
Crystal oscillator 4096 Bytes RC oscillator 28-pin package
Crystal oscillator 4096 Bytes RC oscillator 20-pin package Crystal oscillator 1536 Bytes RC oscillator
Temperature: C = 40C to +85C M = 40C to +125C (available for VDD = 5V only) Package: P = PDIP DW = SOIC FA = LQFP
Ordering Information
Appendix A MC68HLC908JL3E/JK3E/JK1E
A.1 Introduction
This appendix introduces three devices, that are low-voltage versions of MC68HC908JL3E/JK3E/JK1E: MC68HLC908JL3E MC68HLC908JK3E MC68HLC908JK1E The entire data book apply to these low-voltage devices, with exceptions outlined in this appendix.
A.2 Flash Memory

The Flash memory can be read at minimum VDD of 2.2V. Program or erase operations require a minimum VDD of 2.7V.
A.3 Low-Voltage Inhibit

There is no low-voltage inhibit circuit. Therefore, no low-voltage reset. The associated register bits are reserved bits.
A.4 Oscillator Options

Only crystal oscillator or direct clock input is supported.
A.5 Electrical Specifications

Electrical specifications for low-voltage devices are given in the following tables.
A.5.1 Functional Operating Range

Table A-1. Operating Range
Characteristic Operating temperature range Operating voltage range Operating voltage for Flash memory program and erase operations Symbol TA VDD VDD Value 0 to +85 2.2 to 5.5 2.7 to 5.5 Unit C V V
A.5.2 DC Electrical Characteristics

Table A-2. DC Electrical Characteristics
Characteristic(1) Output high voltage (ILOAD = 1.0mA) PTA0PTA6, PTB0PTB7, PTD0PTD7 Output low voltage (ILOAD = 0.8mA) PTA6, PTB0PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (ILOAD = 15mA) PTD6, PTD7 Input high voltage PTA0PTA6, PTB0PTB7, PTD0PTD7, RST, IRQ, OSC1 Input low voltage PTA0PTA6, PTB0PTB7, PTD0PTD7, RST, IRQ, OSC1 VDD supply current (VDD = 2.4V, fOP = 2MHz) Run(3) Wait(4) Stop(5) 0C to 85C Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate(7) Pullup resistors(8) PTD6, PTD7 RST, IRQ, PTA0PTA6 Symbol VOH VOL VOL VIH Min VDD 0.4 0.7 VDD Typ(2) Max 0.4 0.5 Unit V V V
VDD
VIL
VSS
0.2 VDD
IDD
0 0.02 1.8 16
2 1 1 3.3 26
3.5 1.5 3 10 1 12 8 100 4.8 36
mA mA A A A pF mV V/ms k k
IIL IIN COUT CIN VPOR RPOR RPU1 RPU2
1. VDD = 2.4 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD. 5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V
A.5.3 Control Timing

Table A-3. Control Timing
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min 1.5 Max 2 Unit MHz s
1. VDD = 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
A.5.4 Oscillator Characteristics

Table A-4. Oscillator Component Specifications
Characteristic Crystal frequency, XTALCLK External clock reference frequency(1) Crystal load capacitance(2) Crystal fixed capacitance
(2)
Symbol fOSCXCLK fOSCXCLK CL C1 C2 RB RS
Min dc
Typ 2 CL 2 CL 10 M
Max 8 8
Unit MHz MHz
Crystal tuning capacitance(2) Feedback bias resistor Series resistor(2), (3) 1. No more than 10% duty cycle deviation from 50% 2. Consult crystal vendor data sheet 3. Not Required for high frequency crystals
A.5.5 ADC Characteristics

Table A-5. ADC Characteristics
Characteristic Supply voltage Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(1)
(2)
Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI
Min 2.2 (VDD min) VSS 8 0.5 0.5 VSS 14 14 5 00 FE
Max 5.5 (VDD max) VDD 8 2 1.048 VDD 15 01 FF (20) 8 1
Unit V V Bits LSB MHz V tAIC cycles tAIC cycles tAIC cycles Hex Hex pF A
Comments
Includes quantization tAIC = 1/fADIC, tested only at 1 MHz
Zero input reading
VIN = VSS VIN = VDD Not tested
Full-scale reading(3) Input capacitance Input Port B/port D leakage(3)
1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
A.5.6 Memory Characteristics

The Flash memory can only be read at an operating voltage of 2.2 to 5.5V. Program and erase are achieved at an operating voltage of 2.7 to 5.5V. The program and erase parameters in Table A-6 are for VDD = 2.7 to 5.5V only. Table A-6. Memory Characteristics
Characteristic RAM data retention voltage Flash program bus clock frequency Flash read bus clock frequency Flash page erase time Flash mass erase time Flash PGM/ERASE to HVEN set up time Flash high-voltage hold time Flash high-voltage hold time (mass erase) Flash program hold time Flash program time Flash return to read time Flash cumulative program hv period Flash row erase endurance(6)
(7)
Symbol VRDR fRead

(1)
Min 1.3 1 32k 1 4 10 5 100 5 30 1 10k 10k 10
Max 8M 40 4
Unit V MHz Hz ms ms s s s s s s ms cycles cycles years
tErase(2) tMErase(3) tnvs tnvh tnvhl tpgs tPROG trcv(4) tHV(5)
Flash row program endurance Flash data retention time(8)
1. fRead is defined as the frequency range for which the Flash memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the Flash memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the Flash memory. 4. trcv is defined as the time it needs before the Flash can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG 32) tHV max. 6. The minimum row endurance value specifies each row of the Flash memory is guaranteed to work for at least this many erase / program cycles. 7. The minimum row endurance value specifies each row of the Flash memory is guaranteed to work for at least this many erase / program cycles. 8. The Flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
A.6 MC Order Numbers

Table A-7 shows the ordering numbers for the low-voltage devices. Table A-7. MC68HLC908JL3E/JK3E/JK1E Order Numbers
MC Order Number MC68HLC98JL3EIFA MC68HLC98JL3EIP MC68HLC98JL3EIDW MC68HLC98JK3EIP MC68HLC98JK3EIDW MC68HLC98JK1EIP MC68HLC98JK1EIDW Oscillator Type Crystal oscillator Crystal oscillator Crystal oscillator Crystal oscillator Flash Memory 4096 Bytes 4096 Bytes 4096 Bytes 20-pin package 1536 Bytes Package 48-pin LQFP 28-pin package
Notes: I = 0 C to +85 C P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) FA = Low-Profile Quad Flat Pack (LQFP)
Appendix B MC68H(R)C08JL3E/JK3E
B.1 Introduction
This appendix introduces four devices, that are ROM versions of MC68H(R)C908JL3E/JK3E: MC68HC08JL3E MC68HC08JK3E MC68HRC08JL3E MC68HRC08JK3E The entire data book apply to these ROM devices, with exceptions outlined in this appendix. Table B-1. Summary of Device Differences
MC68H(R)C08JL3E/JK3E Memory ($EC00$FBFF) User vectors ($FFD0$FFFF) Registers at $FE08 and $FE09 4,096 bytes ROM 48 bytes ROM Not used; locations are reserved. $FC00$FDFF: Not used. $FE10$FFCF: Used for testing purposes only. MC68H(R)C908JL3E/JK3E 4,096 bytes Flash 48 bytes Flash Flash related registers. $FE08 FLCR $FF09 FLBPR Used for testing and Flash programming/erasing.
Monitor ROM ($FC00$FDFF and $FE10$FFCF)
B.2 MCU Block Diagram

Figure B-1 shows the block diagram of the MC68H(R)C08JL3E/JK3E.
KEYBOARD INTERRUPT MODULE PORTA DDRA
CONTROL AND STATUS REGISTERS 64 BYTES USER ROM: MC68H(R)C08JK3E/JL3E 4,096 BYTES 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE
PTA6/KBI6** PTA5/KBI5** PTA4/KBI4** PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 PTD7** PTD6** PTD5/TCH1 PTD4/TCH0 PTD3/ADC8 PTD2/ADC9 PTD1/ADC10 PTD0/ADC11
USER RAM 128 BYTES MONITOR ROM 960 BYTES USER ROM VECTOR SPACE 48 BYTES MC68HC908JL3E/JK3E X-TAL OSCILLATOR MC68HRC908JL3E/JK3E RC OSCILLATOR
BREAK MODULE
OSC1
OSC2
COMPUTER OPERATING PROPERLY MODULE
* RST
SYSTEM INTEGRATION MODULE LOW-VOLTAGE INHIBIT MODULE EXTERNAL INTERRUPT MODULE * Pin contains integrated pull-up device. ** Pin contains programmable pull-up device. 25mA open-drain if output pin. LED direct sink pin. # Pins available on MC68H(R)C08JL3E only. Shared pin: MC68HC08JL3E/JK3E OSC2 MC68HRC08JL3E/JK3E RCCLK/PTA6/KBI6
DDRD
POWER-ON RESET MODULE
DDRB
* IRQ
VDD POWER VSS ADC REFERENCE
Figure B-1. MC68H(R)C08JL3E/JK3E Block Diagram
B.3 Memory Map

The MC68H(R)C08JL3E/JK3E has 4,096 bytes of user ROM from $EC00 to $FBFF, and 48 bytes of user ROM vectors from $FFD0 to $FFFF. On the MC68H(R)C908JL3E/JK3E, these memory locations are Flash memory. Figure B-2 shows the memory map of the MC68H(R)C08JL3E/JK3E.
$0000 $003F $0040 $007F $0080 $00FF $0100 $EBFF $EC00 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCF $FFD0 $FFFF I/O REGISTERS 64 BYTES RESERVED 64 BYTES RAM 128 BYTES UNIMPLEMENTED 60,160 BYTES ROM MC68H(R)C08JL3E/JK3E 4,096 BYTES MONITOR ROM 512 BYTES BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (RSR) RESERVED (UBAR) BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED RESERVED RESERVED RESERVED RESERVED BREAK ADDRESS HIGH REGISTER (BRKH) BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) RESERVED MONITOR ROM 448 BYTES USER ROM VECTORS 48 BYTES
Figure B-2. MC68H(R)C08JL3E/JK3E Memory Map
B.4 Reserved Registers

The two registers at $FE08 and $FE09 are reserved locations on the MC68H(R)C08JL3E/JK3E. On the MC68H(R)C908JL3E/JK3E, these two locations are the Flash control register and the Flash block protect register respectively.
B.5 Mask Option Registers

This section describes the mask option registers (MOR1 and MOR2). The mask option registers enable or disable the following options: Stop mode recovery time (32 2OSCOUT cycles or 4096 2OSCOUT cycles) STOP instruction Computer operating properly module (COP) COP reset period (COPRS), 8176 2OSCOUT or 262,128 2OSCOUT Enable LVI circuit Select LVI trip voltage
B.5.1 Functional Description

The mask options are hard-wired connections, specified at the same time as the ROM code, which allow the user to customize the MCU.
B.5.2 Mask Option Register 1 (MOR1)

Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 $001F Bit 7 COPRS 6 0 5 0 4 LVID 3 0 2 SSREC 1 STOP Bit 0 COPD
= Unimplemented
Figure 18-1. Mask Option Register 1 (MOR1) COPRS COP reset period selection bit 1 = COP reset cycle is 8176 2OSCOUT 0 = COP reset cycle is 262,128 2OSCOUT LVID Low Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled
SSREC Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 2OSCOUT cycles instead of a 4096 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 2OSCOUT cycles 0 = Stop mode recovery after 4096 2OSCOUT cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP STOP Instruction Enable STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD COP Disable Bit COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
B.5.3 Mask Option Register 2 (MOR2)

Address: Read: Write: Reset: POR: 0 0 0 0 0 0 Not affected 0 Not affected 0 0 0 0 0 0 0 $001E Bit 7 IRQPUD 6 0 5 0 4 LVIT1 3 LVIT0 2 0 1 0 Bit 0 0
= Unimplemented
Figure 18-2. Mask Option Register 2 (MOR2) IRQPUD IRQ Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD LVIT1, LVIT0 Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI)
B.6 Monitor ROM

The monitor program (monitor ROM: $FE10$FFCF) on the MC68H(R)C08JL3E/JK3E is for device testing only. $FC00$FDFF are unused.
B.7 Electrical Specifications

Electrical specifications for the MC68H(R)C908JL3E/JK3E apply to the MC68H(R)C08JL3E/JK3E, except for the parameters indicated below.
B.7.1 DC Electrical Characteristics

Table B-2. DC Electrical Characteristics (5V)
Characteristic(1) VDD supply current, fOP = 4MHz Run(3) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Wait(4) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Stop(5) (40C to 85C) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E (40C to 125C) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Pullup resistors(6) PTD6, PTD7 RST, IRQ, PTA0PTA6 Symbol Min Typ(2) Max Unit
9 4.3 5.5 0.8
11 5 6.5 1.5
mA mA mA mA A A A A k k
IDD
RPU1 RPU2 1.8 16
1.8 1.8 5 5 4.3 31
5 5 10 10 4.8 36
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled. 6. RPU1 and RPU2 are measured at VDD = 5.0V.
Table B-3. DC Electrical Characteristics (3V)

Characteristic(1) VDD supply current, fOP = 2MHz Run(3) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Wait(4) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Stop(5) (40C to 85C) MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Pullup resistors(6) PTD6, PTD7 RST, IRQ, PTA0PTA6 Symbol Min Typ(2) Max Unit
IDD
2.8 1.4 1.5 0.19
3.5 2 2 0.3
mA mA mA mA A A k k
RPU1 RPU2 1.8 16
1.4 1.4 4.3 31
5 5 4.8 36
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 2MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled. 6. RPU1 and RPU2 are measured at VDD = 5.0V.
B.7.2 5V Oscillator Characteristics

Table B-4. Oscillator Component Specifications (5V)
Characteristic RC oscillator external R RC oscillator external C Symbol REXT CEXT Min Typ Max Unit
See Figure B-3 and Figure B-4 10 pF
14 12 RC FREQUENCY, fRCCLK (MHz) 10 8 6 VDD 4 2 0 0 10 20 30 RESISTOR, REXT (k) 40 50 REXT CEXT CEXT = 10 pF 5V @ 25 C OSC1 MCU
Figure B-3. RC vs. Frequency (5V @25 C)

14 12 RC FREQUENCY, fRCCLK (MHz) 10 8 6 VDD 4 2 0 0 10 20 30 RESISTOR, REXT (k) 40 50 REXT CEXT CEXT = 10 pF 3V @ 25 C OSC1 MCU
Figure B-4. RC vs. Frequency (3V @25 C)
B.7.3 Memory Characteristics

Table B-5. Memory Characteristics
Characteristic RAM data retention voltage Symbol VRDR Min 1.3 Max Unit V
NOTES: Since MC68H(R)C08JL3E/JK3E is a ROM device, Flash memory electrical characteristics do not apply.
B.8 MC Order Numbers

These part numbers are generic numbers only. To place an order, ROM code must be submitted to the ROM Processing Center (RPC). Table B-6. MC Order Numbers
MC Order Number MC68HC08JL3ECP MC68HC08JL3EMP MC68HC08JL3ECDW MC68HC08JL3EMDW MC68HRC08JL3ECP MC68HRC08JL3EMP MC68HRC08JL3ECDW MC68HRC08JL3EMDW MC68HC08JK3ECP MC68HC08JK3EMP MC68HC08JK3ECDW MC68HC08JK3EMDW MC68HRC08JK3ECP MC68HRC08JK3EMP MC68HRC08JK3ECDW MC68HRC08JK3EMDW Oscillator Type Package
Crystal 28-pin package RC
Crystal 20-pin package RC
NOTES: C = 40 C to +85 C M = 40 C to +125 C (available for VDD = 5V only) P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC)
Appendix C MC68HC908KL3E/KK3E
C.1 Introduction
This appendix introduces two devices, that are ADC-less versions of MC68HC908JL3E/JK3E: MC68HC908KL3E MC68HC908KK3E The entire data book applies to these devices, with exceptions outlined in this appendix. Table C-1. Summary of MC68HC908KL3E/KK3E and MC68HC908JL3E Differences
MC68HC908KL3E/KK3E Analog-to-Digital Converter (ADC) Registers at: $003C, $003E, and $003E Interrupt Vector at: $FFDE and $FFDF Not used; locations are reserved. Not used. 20-pin PDIP (MC68HC908KK3E) 20-pin SOIC (MC68HC908KK3E) 28-pin PDIP 28-pin SOIC MC68HC908JL3E 12-channel, 8-bit. ADC registers. ADC interrupt vector. 20-pin PDIP (MC68HC908JK3E) 20-pin SOIC (MC68HC908JK3E) 28-pin PDIP 28-pin SOIC 48-pin LQFP
Available Packages
C.2 MCU Block Diagram

Figure C-1 shows the block diagram of the MC68HC908KL3E/KK3E.
C.3 Pin Assignments

Figure C-2 and Figure C-3 show the pin assignments for the MC68HC908KL3E/KK3E.
KEYBOARD INTERRUPT MODULE PTA5/KBI5** PTA4/KBI4** PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PTD7** PTD6** PTD5/TCH1 PTD4/TCH0 PTD3 PTD2 PTD1 PTD0 PORTA DDRA
CONTROL AND STATUS REGISTERS 64 BYTES
USER FLASH 4,096 BYTES
USER RAM 128 BYTES MONITOR ROM 960 BYTES USER FLASH VECTOR SPACE 48 BYTES
BREAK MODULE
OSC1 X-TAL OSCILLATOR OSC2 COMPUTER OPERATING PROPERLY MODULE
* RST
SYSTEM INTEGRATION MODULE LOW-VOLTAGE INHIBIT MODULE EXTERNAL INTERRUPT MODULE * Pin contains integrated pull-up device. ** Pin contains programmable pull-up device. 25mA open-drain if output pin. LED direct sink pin. # Pins available on MC68HC908KL3E only.
DDRD
POWER-ON RESET MODULE
DDRB
* IRQ
VDD POWER VSS
Figure C-1. MC68HC908KL3E/KK3E Block Diagram
IRQ PTA0/KBI0 VSS OSC1 OSC2 PTA1/KBI1 VDD PTA2/KBI2 PTA3/KBI3 PTB7 PTB6 PTB5 PTD7 PTD6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RST PTA5/KBI5 PTD4/TCH0 PTD5/TCH1 PTD2 PTA4 PTD3 PTB0 PTB1 PTD1 PTB2 PTB3 PTD0 PTB4
MC68HC908KL3E
Figure C-2. 28-Pin PDIP/SOIC Pin Assignment
IRQ VSS OSC1 OSC2 VDD PTB7 PTB6 PTB5 PTD7 PTD6
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RST PTD4/TCH0 PTD5/TCH1 PTD2 PTD3 PTB0 PTB1 PTB2 PTB3 PTB4
Pins not available on 20-pin packages PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 Internal pads are unconnected. PTD0 PTD1
MC68HC908KK3E
Figure C-3. 20-Pin PDIP/SOIC Pin Assignment
C.4 Reserved Registers

The following registers are reserved location on the MC68HC908KL3E/KK3E.
Addr. $003C Register Name Read: Reserved Write: Reset: Read: $003D Reserved Write: Reset: Read: $003E Reserved Write: Reset: R R R R R R R R R R R R R R R R Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure C-4. Reserved Registers
C.5 Reserved Vectors

The following vectors are reserved interrupt vectors on the MC68HC908KL3E/KK3E. Table C-2. Reserved Vectors
Vector Priority INT Flag IF15 $FFDF Reserved Address $FFDE Reserved Vector
C.6 Order Numbers

Table C-3. MC68HC908KL3E/KK3E Order Numbers
MC order number MC68HC908KL3ECP MC68HC908KL3ECDW MC68HC908KK3ECP MC68HC908KK3ECDW Package 28-pin PDIP 28-pin SOIC 20-pin PDIP 20-pin SOIC 40 to +85 C 3V, 5V XTAL 4096 Bytes Operating Temperature Operating VDD OSC Flash Memory
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MC68HC908JL3E Rev. 4, 10/2006

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MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC903KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E

MC68HC908JL3E Rev. 4 10/2006

MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC908KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E

MC68HC908JL3E Family Data Sheet, Rev. 4 4 Freescale Semiconductor

MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 5

MC68HC908JL3E Family Data Sheet, Rev. 4 6 Freescale Semiconductor

Chapter 3 Configuration Registers (CONFIG)

Chapter 4 Central Processor Unit (CPU)

4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8

Chapter 5 System Integration Module (SIM)

Chapter 6 Oscillator (OSC)

Chapter 7 Monitor ROM (MON)

Chapter 8 Timer Interface Module (TIM)

Chapter 9 Analog-to-Digital Converter (ADC)

Chapter 10 Input/Output (I/O) Ports

MC68HC908JL3E Family Data Sheet, Rev. 4 10 Freescale Semiconductor

110 110 111 112

Chapter 11 External Interrupt (IRQ)

Chapter 12 Keyboard Interrupt Module (KBI)

Chapter 13 Computer Operating Properly (COP)

MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 11

Chapter 14 Low Voltage Inhibit (LVI)

Chapter 15 Break Module (BREAK)

Chapter 16 Electrical Specifications

16.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 16.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Chapter 17 Mechanical Specifications

Chapter 18 Ordering Information

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Chapter 1 General Description

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MCU Block Diagram

1.3 MCU Block Diagram

KEYBOARD INTERRUPT MODULE PORTA DDRA

2-CHANNEL TIMER INTERFACE MODULE PORTB PORTD

VDD POWER VSS ADC REFERENCE

Figure 1-1. MCU Block Diagram

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1.4 Pin Assignments

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Pin Assignments PTD4/TCH0 PTD5/TCH1

37 NC 36 NC 35 34 33 32 31 NC NC PTD2/ADC9 PTA4/KBI4 PTD3/ADC8 NC PTB0/ADC0 PTB1/ADC1 PTD1/ADC10 NC 25 NC NC 24 30 29 28 27 26

NC 1 NC OSC1 OSC2/RCCLK/PTA6/KBI6 PTA1/KBI1 NC VDD PTA2/KBI2 PTA3KBI3 PTB7/ADC7 NC NC 12 NC 13 2 3 4 5 6 MC68H(R)C908JL3E 7 8 9 10 11 20 21 22 PTB2/ADC2 14 15 16 17 18 19 23 NC

Figure 1-4. 48-Pin LQFP Pin Assignment

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1.5 Pin Functions

VDD VDD VDD

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2.2 I/O Section

2.3 Monitor ROM

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UNIMPLEMENTED 62,720 BYTES

$0100 $F5FF $F600 $FBFF

FLASH MEMORY MC68H(R)C908JL3E/JK3E 4,096 BYTES

FLASH MEMORY MC68H(R)C908JK1E 1,536 BYTES