CHAPTER 1: INTRODUCTION 1.

1 Introduction
A combination lock is a type of lock in which a sequence of numbers or symbols is used to open the lock. In the real world, combinational locks are used frequently to lock up personal belongings, lock doors, and to provide password protection for operation of devices and machinery. Conventionally, combinational locks have been made mechanically using physical rotating discs or cams, which are specially crafted to interact with some type of locking mechanism. The first mechanical combinational locks were designed as early as 1200 AD. However, these locks require a lot of precise moving parts to function correctly and have several flaws. With a mechanical lock, if the combination is forgotten it is most probable that the lock will have to be physically cut to remove the lock since the combination is unknown and cannot be reset. Also, many mechanical locks only have one set combination so if the password is compromised the entire lock must be replaced. The programmable combination lock is an interesting digital design problem because entering and checking combinations are processes that can be divided into sequential states which can be modelled using a finite state machine. The engineers are forced to solve a clearly defined set problem. If the design was 100% creative with no set design parameters then the engineers could stay away from any design hurdles. The intelligent combinational lock is a good idea for digital logic design because the digital combination lock has a good mix of mandatory design parameters that must be adhered to, but also a good amount of leeway for the designer to add personal ideas and intuition to improve the design of the system. This project enforces set design parameters while still allowing room for creativity.

CHAPTER 2 2.1 Review of literature

We implemented a digital lock using two different procedures at first but the failure of one led to the adoption of the other. The first design turned down due to faults in synchronization of the signal though we used FSM but wasnt helpful. So the second design was completely dependent on the FSM model wherein we learnt about Finite State Machines importance as well as its need and application in the process of designing a system. So either way we learnt about FSM as well as successfully implemented it through this lock. Next the BIST, it is built in self test was rather using complex algorithm construction but also was very difficult to work on so we decided that we shall provide the code or sequence that is randomly generated by a random code generator so that the system shall generate the output so we are sure enough that the lock is well in condition.

2.2 Scope of the study (Problem Statement)

To implement a digital combinational lock with built in self-test capabilities using Verilog HDL on Isim.

CHAPTER 3 3.1 Objectives of the study

The necessity of implementation of Verilog in designing high end as well as cheap cost ICs was our area of interest. So we came up with the idea of implementing a digital lock with FSM as well as BIST. We had to first learn about the details of the Verilog HDL to adopt its programming ways and types through which we could implement our system. Next it was necessary for us to learn about FSM for implementing the system or digital lock. Also we used the random code generator and successfully implemented testing using a random sequence of bits.

3.2 Expected outcome of the study

We designed a digital combinational lock wherein we the user enables the lock first. As soon as the lock is enabled the system enters into the self test mode. If the output of the lock is correct then the lock status goes high and user can use the lock. Else it can be determined that there might be a problem in the IC so the system keeps self testing itself.Then he enters the code or to say the combination into the lock, the lock checks for the combination and returns the output whether the entered code is correct or not. Now the user gets a choice either check for combination or change the combination. Now if the user chooses to check the combination the lock shows the correct output or wrong output for given period of time only. Else if the user changes the combination the lock is again set for self testing. Also a hex output is connected to the lock to predetermine which state the lock is in.

4.3Preliminary research work done

The necessary components we should know to implement the project with least number of flaws, for our project, are Finite State Machine (FSM) Built In Self Test (BIST) These components are have been described briefly further in the chapter. These components were necessary to design the project because any other approach would have made the design

either complex or lead us to unknown outputs. As our project involved a lot of synchronization of the input as well as outputs and implementation through Moore machine so we used the FSM. Also built in self capabilities are to be realized it is necessary to have a clear perception about it.

4.3.1 Finite State Machine

Basically a FSM consists of combinational, sequential and output logic. Combinational logic is used to decide the next state of the FSM, sequential logic is used to store the current state of the FSM. The output logic is a mixture of both combo and seq. logic as shown in the figure below.

FIG: 2.1 Output of combinational and sequential logic Moore machines are very useful because their output signals are synchronized with the clock. No matter when input signals reach the Moore Machine, its output signals will not change until the rising edge of the next clock cycle. This is very important to avoid setup timing violations. For example, if a Mealy machines input signal(s) changes sometime in the middle of a clock cycle, one or more of its outputs and next state signals may change some time later. Some time later might come after the setup time threshold for the next rising edge. If this happens, the registers that will hold the FSMs next state may receive garbage, or just incorrect inputs. Obviously, this amounts to a bug(s) in your FSM. The trade-off in using the Moore machine is that sometimes the Moore machine will require more states to specify its function than the Mealy machine. This is because in a Moore machine, output signals are only dependent on the current state. In a Mealy machine, outputs are dependent on both the current state and the inputs.

4.3.2 Built In Self Test

Built-in Self Test, or BIST, is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self-testing, i.e., testing of their own operation (functionally, parametrically, or both) using their own circuits, thereby reducing dependence on an external automated test equipment (ATE). BIST is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient, and less costly. The concept of BIST is applicable to just about any kind of circuit, so its implementation can vary as widely as the product diversity that it caters to. It can be represented in the following diagram.

Sequence Generator

Present Circuitary to be tested

FIG.2.2: Block Diagram of BIST

Output comparasion

The sequence generator generates a sequence which is fed to the original circuitry. According to the input the output is tested to define whether the given circuitry is having errors or not.

4.3.3 Verilog and Xilinx Verilog:

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis. The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard for Verilog was published in 1995. A revised version was published in 2001; this is the version used by most Verilog users. The IEEE Verilog standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

A further revision of the Verilog standard was published in 2005, though it has little extra compared to the 2001 standard. SystemVerilog is a huge set of extensions to Verilog, and was first published as an IEEE standard in 2005. IEEE Std. 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C). Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

Xilinx: The Xilinx Integrated Software Environment (ISE) is a powerful and complex set of tools. Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer tosynthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

CHAPTER 3: METHODOLOGY 3.1 Introduction

Present digital locking system have the capability to reset the password in case the present password gets compromised but most of these locks can malfunction without the knowledge of the user so we introduced the built in self testing capability into the system. Thus it was necessary for us to design the system with the built in self test capabilities so that the user knows whether the lock is functioning properly or not. So we used a random sequence generator of 4 bits that generated the output that was used for testing of the lock with the help of finite state machine used to control the timing and the signals. There were two fundamental ways to design a programmable combinational lock using digital logic to create a digital system. The first strategy was to create a digital combination lock by creating a finite state machine that is an enormous if-tree, which moves from designated state to designated state based on timing and user inputs. The second strategy was to use a set of registers to store data from users and make comparisons with the predefined key registers that are reprogrammable. Since the design should be more straightforward and easier to tweak or make modifications and additions to the system, we used the second strategy.

3.2 Algorithm
An intelligent combinational lock design for the specifications of this class should be reprogrammable, have a timeout feature, a lockout feature, and a self-check or test feature [5]. It is important to note that whenever the key is changed the self testing is performed and as well as when the system is started. The user will be allowed to enter the code only if the lock status is high. The performing of the task to obtain the correct output can be direct but a number of risks have to be looked into while designing a system so we took care of a number of points and designed the following system as shown in the flowchart that has been implemented by the following algorithm : As soon as the system is started the lock is tested for correct performance. If it fails a retest is performed until the system passes the test.

The user enters a combination that is of four numbers. Until the key is entered, that is the combination of four keys is entered, the lock does not process further. On entering the correct combination we have two choices either to open the lock or to change the code. (Only if we enter the correct code we get to make the changes in the combination.)

On changing the password the lock is self-tested again else the lock is opened if the other option is opted. Now if the combination is entered, correct or wrong, the status goes high at given pins for a predefined period of time and then resets itself.

3.3 System flowchart

START

Built In Self Test Mode

FAULT IN LOCK

NO

Lock Status

YES
LOCK CONDITION OK

Enter Lock Code

Lock Code Match YES

NO

Check Value Change

NO

YES Change Lock Code

Display Input Code Matched or Not

3.4 Logical diagram

Inputs

BIST

Encoder

Mux Key Register

Register

Comp 2 bit

Comp 4x4 bit

Output Control

Lock Status Lock open

Counter

The following block diagram defines the module of the combinational lock that we have implemented using Verilog HDL. The user has 10 buttons that are used to enter the code that is 0-9, a reset pin to reset the system, a c pin used for changing the combination and the clock signal clk that is used for controlling the sequential circuitry and also used for synchronizing.

Self Test Mode:The following mode is selected as soon is the system is started or whenever the combination is changed. In the following mode user inputs are not considered. Until the lock generates an ok status the system does not enter the user mode.

User Mode:The following mode is selected whenever the lock status is ok. In the following mode the random code generator is disabled. The user gets two choices that is one where it performs in normal mode wherein the entered combination is correct or not. The next choice is to change the combination which is only allowed after the entered combination is correct. The block diagram details: Encoder: - The encoder used in the circuit is simply for the purpose of converting each number
pressed on the keyboard into its BCD format for easier storage and calculation. Its output is in BCD format that is used either to store the input lock key or for the change in key.

Multiplexer: - It is used for selecting either encoder input or random code generator input to be
stored into the register. The selection lines input is decided based on the state of the finite state machine

Comparators: - Two types of comparator are used out of which one is for simply comparing the
input combination and the correct combination. The other is for comparing the lock module output and the BIST module output for faults in lock.

Counter: - It is used to count the clock cycles for timing, to control the output. Register: - The use of 4x4 bit register in our system is to store the user entered code in BCD
format for comparing purposes. As BCD formatted numbers are of four bits and our lock has a combination of four numbers so 4x4 bit register is required. It is also used to store the real key combination and the code generated by the BIST.

 Output Control: - It is used to control the output timing as the lock shouldnt be open for more than given period of time. So this module is used to implement the timeout feature into our system.

BIST: - It was necessary to have this module implemented so that our idea of self testing system could be incorporated into this system. But a simple random sequence was not enough to complete the system. We also needed to store the generated code so we combined the module with the register module to store the generated output. But the real purpose was to test the system so we stored the generated code into the users register. The value generated is stored in register of the BIST as well as the user input register and compared to the stored combination. Figure below shows the block diagram of the BIST module.

Original Key Random Sequence Generator

3.5 CODING
3.5.1 FSM

Comp 4x4 bit

Output

Register

For carrying out FSM we will need a way to express the following in Verilog: 1. A state encoding for each state. 2. A mechanism for keeping track of the current state. 3. Transitions from state to state. 4. Output values based on the current state.

We will construct the FSM one step at a time. 3.5.1.1 Creating a State Encoding We will create our state encoding with Verilog parameters. Parameters are symbolic constants with either global (given by the Verilog keyword parameter) or module (localparam) scope. Because we only want our state encoding to be visible to the other modules other than the

module in which we will write the FSM, we will use parameter. With this in mind, we can specify the comp module. In the comp module, the 3b notation indicates that the number specified is in the binary radix. If we were to use 3d, the encoding would look like simple as we shall declare states with decimal values. Both implementations are equivalent. Base 10, is typically easier to work on so we use it. Because this FSM has 6 total states, we must allocate 3 bits to specify the encoding (hence 3b as opposed to 2b or 4b. This is extremely important. If we specify too few bits for our state encoding, Verilog shall not warn us. In fact, when synthesized, each state will only get as many bits as you provide. For example, if STATE_4 was specified like this: STATE_4 = 2b00, STATE_4 would be specified as 00, the bottom 2 bits of what was intended, namely 100. 3.5.1.2 Keeping Track of the Current State We have several options in how to store the current state of our FSM. Though we thought that the module itself shall decide the present and the next state shall be stored in it at the same time in the code as we have used defining another always block to assign the present state the next state as shown.
always @ (posedge clk) begin state1<=state; end

3.5.1.3 Transitioning from State to State After we have established our state encoding and a means of storing the current state value (which will henceforth be referred to as Current State), our next task is to create a way for the FSM to actually change state, and for it to choose how to change state. This requires that we have a state diagram to implement the code for present state and next state

S0 e=0 rst=0,r=0

e=1 S1 rst=1,r=0 re=0

re=1 rin=1 S2 re=0 rst=1,r=0

re=1 S3 rst=1,r=0 re=0

re=1 S4 rst=1,r=1 re=0

re=1 S5 rst=x,r=0 rin=0

3.5.1.4 Outputting Values Based on the Current State The final step in specifying a Moore FSM is assigning output values based on Current State.
assign hex_display = {1'b0,state1};

Here we use assign to assign output. Also we provide the hex code state output to see it on display or connect external peripheral device.

Functionality

A sophisticated design strategy is utilized in this project that is to store the combination in registers and then compare the register containing the user input combination with the register containing the programmed combination to determine whether the lock should be unlocked. Finite state machines are implemented to control the timing and order of processes in the digital system. As soon as the lock starts it is in self test mode where the combinations are generated by the 4-bit random sequence generator. The code is compared to the stored code generating the correct or erroneous output. If the lock module also generates the same output then the lock status is set high making it available for the users. Else the module will keep self testing itself. Now when the user enters the combination it is verified. If the entered combination is correct then the system monitors the C signal for changing the key combination. If the value on signal C is asserted then the user enters the new combination that is stored and the system is self tested again. Else the system performs normally to generate an output showing the combination entered is correct or not. The output is available only for a number of clock cycles so as to have a timeout feature.

CHAPTER 4: RESULT ANALYSIS 4.1 Introduction

To implement a design in Verilog HDL we need to design using blocks or modules. So we did the implementation using modules and finally combined all the basic module to form one module at the end called module lock.

4.2 Preliminary experimental work done

4.2.1 MODULE HDD The following module has been used for storage purpose as it contains 4 x 4 registers that is 16 registers used to store the combination of 4 numbers in BCD format. This register had been instantiated twice, once for the user combination and the other for the BIST combination.

S0 e=0 rst=0,r=0 e=1 S1 re=0 rst=1,r=0 re=1 rin=1 S2 re=0 rst=1,r=0 re=1 S3 re=0 rst=1,r=0 re=1 S4 re=0 rst=1,r=1 re=1 S5 rin=0 rst=x,r=0

We have used the re signal and rst signal for synchronizing purposes. Also the r signal has been used for denoting that the combination has been successfully stored into the registers. The following represents the state diagram of the module hdd wherein the states have transition based on input and the outputs generated depending on the states.

This state diagram could be explained as follows: If the system is enabled then move to next state (S1) else remain in same state (S0). If there is an input then the re pin needs to go high moving to next state (S2) else it remains in same state (S1). The rst signal goes high denoting that data has been received. If there is an input then the re pin needs to go high moving to next state (S3) else it remains in same state (S2). The rst signal goes high denoting that data has been received. If there is an input then the re pin needs to go high moving to next state (S4) else it remains in same state (S3). The rst signal goes high denoting that data has been received. If there is an input then the re pin needs to go high moving to next state (S5) else it remains in same state (S4). The rst signal goes high denoting that data has been received. Also the r signal goes high representing that the combination has been successfully received. Now in the system resets the r signal in this state and remains in this state (S5) until it receives a reset signal rin. On receiving a rin signal the system goes back to first state (S0). The output generated is as follows:-

MODULE STREG This module is used for storing the key combination. It has two modes of operation. First is normal where it provides the key combination on Q1,Q2,Q3,Q4 pins. Next is key combination change mode which is activated as soon as a pulse signal is applied at c pin.

Now if we see the state machine diagram as shown, we may see that there are two states As soon as the system is started the default combination 9999 is provided at the output that is each Q1, Q2, Q3, Q4 will have a value 9 at the output. Now if the c signal is sent then we move to next state (S2).which internally has a number of states to change the stored combination replacing it with a new combination. As soon we enter the state S2 a new state is started within. If the system is enabled then move to next state (S11).

S1

c=0

c=1

S2 S11 e=0 rst=1,r=0 re=1 S12 re=0 rst=1,r=0 re=1 S13 re=0 rst=1,r=0 re=1 S14 re=0 rst=1,r=0 re=1 S15 rst=0,r=0

If there is an input then the re pin needs to go high moving to next state (S12) else it remains in same state (S11). The rst signal goes high denoting that data has been received.

If there is an input then the re pin needs to go high moving to next state (S13) else it remains in same state (S12). The rst signal goes high denoting that data has been received.

If there is an input then the re pin needs to go high moving to next state (S14) else it remains in same state (S13). The rst signal goes high denoting that data has been received.

If there is an input then the re pin needs to go high moving to next state (S15) else it remains in same state (S14). The rst signal goes high denoting that data has been received. Also the r signal goes high representing that the combination has been successfully received.

As soon we enter state S15 the signal r goes low and the next state is S11. But the outer state moves to state S1 so again the newly stored combination is given at the output.

The following can be seen as the output of the module

MODULE BISTHD This module is a combination of 2 modules 1. Random Sequence Generator 2. HDD We have already seen the module HDD and its working and now we shall be looking at the LFSR. An LFSR is a shift register that, when clocked, advances the signal through the register from one bit to the next most-significant bit. Some of the outputs are combined in exclusive-OR configuration to form a feedback mechanism. A linear feedback shift register can be formed by performing exclusive-OR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip-flops. So in our project we have feedback outputs LSB and second last MSB.

Now we have interfaced the LFSR with HDD so as to store the generated code into registers for performing the test. Also the generated code is sent to user combination storage register

The following output was obtained on implementation of the bisthd module

MODULE ENCODER This module is used to convert the single bit input to binary representation of the number. For eg. if the input signal at a pin connected to button 9 goes high then the encoder generates the output 1001 that is the binary representation of the 9.

MODULE COMP This module is

used for comparing the combinations and generating either high signal co if the output is correct or high signal at eo if the combinations dont match.

MODULE COMP2B This module is used to compare the outputs generated by BIST comparator and the other comparator.

MODULE MUX This module is used for interfacing the user combination storage register with the encoder input as well as BIST input depending on the state of the lock.

MODULE LOCK This is the module where all the above modules have been combined as well as synchronized by signals to generate the required output.