Scribd
Upload
61 views6 pages

Experiment No: - 1: Aim: - To Design Various Logical Gates Using VHDL.

The document describes an experiment to design various logical gates using VHDL. The aim was to create VHDL code for AND, OR, NAND, NOR, XOR, XNOR, and NOT gates. VHDL code was written and tested in Active HDL 7.2 software to generate the logic functions of each gate based on the input values. Output waveforms confirmed the gates were functioning correctly as designed.

Uploaded by

Prem Prakash
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
61 views6 pages

Experiment No: - 1: Aim: - To Design Various Logical Gates Using VHDL.

The document describes an experiment to design various logical gates using VHDL. The aim was to create VHDL code for AND, OR, NAND, NOR, XOR, XNOR, and NOT gates. VHDL code was written and tested in Active HDL 7.2 software to generate the logic functions of each gate based on the input values. Output waveforms confirmed the gates were functioning correctly as designed.

Uploaded by

Prem Prakash
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 6

Experiment No: - 1

Aim: - To design various logical gates using VHDL.


Software Used: - Active HDL 7.2 VHDL Source Code: (i) For AND gate:library IEEE; use IEEE.std_logic_1164.all; entity and_g is port(a,b:in std_logic; z:out std_logic); end and_g; architecture beh of and_g is begin process(a,b) begin if a='0' and b='0' then z<='0'; elsif a='0' and b='1' then z<='0'; elsif a='1' and b='0' then z<='0'; else z<='1'; end if; end process; end beh;

(ii) For OR gate:


library IEEE; use IEEE.std_logic_1164.all; entity or_g is port(a,b:in std_logic; z:out std_logic); end or_g; architecture beh1 of or_g is begin process(a,b) begin

Name:-Prem Prakash

Roll No.:-241/09

C.S.E(6th Sem.)

if a='0' and b='0' then z<='0'; elsif a='0' and b='1' then z<='1'; elsif a='1' and b='0' then z<='1'; else z<='1'; end if; end process; end beh1;

(iii) For NAND gate:


library IEEE; use IEEE.std_logic_1164.all; entity nand_g is port(a,b:in std_logic; z:out std_logic); end nand_g; architecture beh2 of nand_g is begin process(a,b) begin if a='0' and b='0' then z<='1'; elsif a='0' and b='1' then z<='1'; elsif a='1' and b='0' then z<='1'; else z<='0'; end if; end process; end beh2;

(iv) For NOR gate:


library IEEE; use IEEE.std_logic_1164.all; entity nor_g is port(a,b:in std_logic; z:out std_logic); end nor_g; architecture beh2 of nor_g is

Name:-Prem Prakash

Roll No.:-241/09

C.S.E(6th Sem.)

begin process(a,b) begin if a='0' and b='0' then z<='1'; elsif a='0' and b='1' then z<='0'; elsif a='1' and b='0' then z<='0'; else z<='0'; end if; end process; end beh2;

(v) For XOR gate:


library IEEE; use IEEE.std_logic_1164.all; entity xor_g is port(a,b:in std_logic; z:out std_logic); end xor_g; architecture beh4 of xor_g is begin process(a,b) begin if a= b then z<='0'; else z<='1'; end if; end process; end beh4;

(vi) For XNOR gate:


library IEEE; use IEEE.std_logic_1164.all; entity xnor_g is port(a,b:in std_logic; z:out std_logic); end xnor_g; architecture beh5 of xnor_g is begin

Name:-Prem Prakash

Roll No.:-241/09

C.S.E(6th Sem.)

process(a,b) begin if a= b then z<='1'; else z<='0'; end if; end process; end beh5;

(vii) For NOT gate:


library IEEE; use IEEE.std_logic_1164.all; entity not_g is port(a:in std_logic;z:out std_logic); end not_g; architecture beh6 of not_g is begin process(a) begin if a='0' then z<='1'; else z<='0'; end if; end process; end beh6;

Name:-Prem Prakash

Roll No.:-241/09

C.S.E(6th Sem.)

Output waveform of programs:


For AND gate:

For OR gate:

For NAND gate:

For NOR gate:

Name:-Prem Prakash

Roll No.:-241/09

C.S.E(6th Sem.)

For XOR gate:

For XNOR gate:

For NOT gate:

Name:-Prem Prakash

Roll No.:-241/09

C.S.E(6th Sem.)

You might also like