A z -Domain Model and Analysis of Phase-Domain All-Digital Phase-Locked Loops

Stefan Mendel
Christian Doppler Laboratory for Nonlinear Signal Processing Graz University of Technology, Austria Email: [email protected]

Christian Vogel
Signal Processing and Speech Communication Laboratory Graz University of Technology, Austria Email: [email protected]

Abstract In this paper a comprehensive z -domain model of alldigital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus reects both, frequency and phase behavior. The system model is investigated in detail. Each component is described in form of its transfer function to obtain an overall input/output behavior for the frequency and the phase domain. Furthermore, the physical characteristics of the noise sources within the structure are studied and their effects on the phase noise of the PLL are determined. The system level model is independent of the actual implementation, however, the relation to an existing frequency synthesizer for wireless communications is discussed. Simulation results conrm the accurateness of the presented model with respect to the time and frequency behavior of the system.

behavior which reects the above mentioned characteristics of a digital implementation. II. P HASE D OMAIN A LL -D IGITAL P HASE -L OCKED L OOP Figure 1 shows the z -domain model of a phase-domain ADPLL. The model includes frequency and phase signals and thus reects both, frequency and phase behavior of the PLL. The sampling frequency of the discrete-time system is the slow reference frequency fref . The sample index n corresponds to the reference cycles n Tref with Tref = 1/fref . The feedback mechanism of the PLL controls the variable frequency fv [n] produced by the digitally controlled oscillator (DCO) so that in steady-state it is in frequency and phase lock with the desired ss . Note that fv [n] represents the variable frequency over frequency fv time Tref and is updated with each reference cycle n. A frequency-tophase converter (FPC) converts the variable frequency signal fv [n] into a phase-domain signal v [n]. Since the conversion needs one reference clock cycle, a delay element z 1 is added in the feedback path. ss is given as a multiple Nr of a reference The desired frequency fv frequency fref produced by a crystal oscillator, i.e.,
ss = Nr fref . fv

I. I NTRODUCTION All-digital phase-locked loops (ADPLLs) are an attractive alternative to their analog counterparts, beneting from the advantages of digital design regarding area, power consumption, and exibility. Furthermore, analog design becomes increasingly difcult with a higher integration density. While an analog PLL needs a complete redesign for a new process, a digital implementation can be ported with less effort. Beside the mentioned advantages in the design procedure, ADPLLs are also attractive from a system level point of view. The noise immunity of digital circuits, the capability of digital signal processing, the avoidance of analog tuning, and the linear phase detector allow for high performance PLLs. Recently, several high performance ADPLLs for various applications have been proposed in [1] and [2]. In [2] the authors propose a phase-domain ADPLL architecture as a frequency synthesizer for multigigahertz wireless communications such as GSM and Bluetooth. Since several decades we have had experience concerning design and analysis of analog PLLs, but until today little research has been done on ADPLLs. An analysis of the frequency synthesizer introduced in [2] is presented in [3]. Although a z -domain model is the proper and more accurate description of a digital system, the analysis focuses on a linear s-domain approximation. Moreover, the design procedure of ADPLLs in [4] is based on the analogy to the extensively analyzed analog charge-pump PLL, e.g., [5]. ADPLLs are generally modeled with event-driven simulators in the time-domain [6], [7], and [8]. A high level model is often sufcient to evaluate typical effects of ADPLLs, such as, lock time, loop bandwith, and noise behavior. In this paper we present a comprehensive z -domain model of phase-domain ADPLLs and derive the input/output transfer function as well as the noise transfer functions. Relations to the implementation of [2] and its analysis in [3] are discussed. We show that the model allows an easy and accurate modelling of the ADPLL

(1)

ss into a reference Another FPC converts the desired frequency fv phase signal r [n], similar to the feedback path. An advantage of a phase-domain PLL is the simple phase detector, which realizes a subtraction and introduces no harmonics [9]. The resulting phase error e [n] is ltered by the digital loop lter and normalized to the . The reference frequency fref and an estimate of the DCO gain K calculated oscillator tuning word d[n] is the input to the DCO. The feedback mechanism of the phase-locked loop controls the oscillator tuning word d[n] dss , so that the output of the DCO becomes ss . The symbol denotes the behavior of the steadyfv [n] fv state, i.e., when lock is achieved. In the following we investigate the key components of the phasedomain ADPLL in order to obtain their input-output behavior in form of their transfer function.

A. Digitally Controlled Oscillator A digitally controlled oscillator, i.e., a digital-to-frequency converter (DFC), converts a digital input word d[n] into a signal with frequency fv [n]. The frequency change corresponding to the change of the least signicant bit (LSB) of d[n] is the DCO gain K with the unit Hz/LSB. Thus, the idealized digital-to-frequency conversion is fv (z ) = K. d(z ) (2)

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Reference Normalization
fref

Frequency-to-Phase Converter
Tref

Reference Delay

Phase Detector

Loop Filter

Loop Normalization
fref

Normalized DCO
1 K

DCO
K

DCO

Nr

ss fv

Nr

1 1z 1

r [n]

z 1

r [n 1]

e [n] N v [n]
z 1 1z 1

f v [n]

d[n]

fv [ n]

v [n 1] T DC

z 1

v [n]

1 1z 1

Nv [n] Tref

Feedback Delay

Frequency-to-Phase Converter

Fig. 1.

A z -domain model of a phase domain All-digital phase-locked loop.

` Within the paper (z ) denotes the z -transform of the time signal ` [n], e.g., fv (z ) is the z -transform of fv [n]. The DCO is the only analog component and, in practice, its behavior suffers from process, supply voltage VDD [n], and temperature [n] (PVT) effects. A more general description of (2) incorporates the combined PVT impairments in a time-varying, nonlinear function K (d(z ), VDD (z ), (z )), fv (z ) = K (d(z ), VDD (z ), (z )) . d(z ) B. Frequency-to-Phase Converter A frequency-to-phase converter (FPC) converts frequency information into phase information evaluated at discrete time stamps n Tref . The input to the FPC is a sinusoidal signal with frequency f (t) and phase 20 , i.e., sin(2f (t)t + 20 ). The phase signal normalized by 2 is (t) = f (t) t + 0 . Assuming a constant frequency f (t) over a reference period Tref and that the FPC updates with each reference cycle n, the corresponding phase at time t = n Tref is given by [n] = f [n] nTref + 0 = f [n] Tref + f [n] (n 1)Tref + 0 . | {z }
[n1]

arithmetic within the loop is purely digital. A major advantage of an ADPLL is the linear phase detector e [n] = r [n 1] v [n 1] (6)

which produces no spurs, so that a proportional factor can be used as a loop lter, i.e., a type-I PLL N v (z ) = . e (z ) (7)

(3)

While a type-I PLL is superior in lock time it has inferior noise attenuation compared to higher order PLLs. In a type-II PLL an integral term is added, N v (z ) z 1 . =+ e (z ) 1 z 1 (8)

(4)

The output of the loop lter f v [n] is multiplied with fref , since an LSB integer change of Nr corresponds to a frequency change of fref . to make the In a further normalization step, f v is normalized by K is an estimate loop ideally independent of PVT effects. The factor K of the actual DCO gain K (d(z ), VDD (z ), (z )). If the estimate K equals the actual gain K (d(z ), VDD (z ), (z )) the normalized DCO with input f v and output fv has a transfer function of unity. III. A NALYSIS A. Steady-State It is crucial to understand the locking process of phase-domain ADPLLs. For the following analysis we assume a linear DCO as = K . Consequently, the locking process can be in (2) and K described as
ss f v [n] = fv [n] fv ,

Thus, the FPC can be implemented as an accumulator with [0] = 0 . The transfer function of the FPC in the z -domain is (z ) 1 . = Tref f (z ) 1 z 1 (5)

Since the transfer function has a pole at z = 1 it is unstable and the phase which is obtained by accumulating f [n] Tref , is unbounded. In practice the value of the phase is limited since a certain number of bits is used to represent [n]. If the maximum value of the representation is exceeded, the phase representation is affected by an overow. However, this strong nonlinear behavior does not inuence the ADPLL characteristic [9] and is therefore neglected in the model. Note, that the FTP conversion requires one reference cycle, so that at the output only [n 1] is available. Therefore an additional delay element z 1 is added in the reference and in the feedback path in Fig.1. C. Digital Loop Arithmetic The DCO is an analog component and the FPC in the feedback path converts an analog signal with frequency fv into a digital phase signal v , i.e., the ADPLL is a mixed signal system. However, the

(9) (10)

N v [n] = Nv [n] Nr .

Substituting (4) for the reference and the variable phase into the phase detector equation (6) yields
ss fv [n]) + e [n 1]. e [n] = Tref (fv

(11)

In steady-state the rst term of the right side vanishes, since (9) and the phase error converges to a constant value ss e . In a type-I PLL the phase error is ss e = Nr / since (7) and (10) must be fulllled. In a type-II PLL the ss e will converge to zero since the integral term will converge to Nr .

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B. z -Domain Transfer Function The open-loop transfer function of the discrete-time z -domain model of the type-II ADPLL in Fig. 1 with respect to the phasedomain signals is ol (z ) = v (z )z 1 (z 1) + = e (z ) (z 1)2 (12)

S ( )
3 30 dB/dec 2 20 dB/dec 0 0 dB/dec

S ( )
1 10 dB/dec 0 0 dB/dec

2 20 dB/dec

(a) Phase Noise (b) Frequency Noise

= K . Otherwise the coefcients and where we assumed again K would be scaled by K/K . The closed-loop transfer function is cl (z ) = v (z )z 1 (z 1) + = r (z ) (z 1)2 + (z 1) + (13)

Fig. 3.

Phase and Frequency Noise of an oscillator.

D. Noise Analysis Typically the phase noise is expressed as the power in a 1 Hz bandwidth in a single sideband at frequency offset normalized to the carrier power, i.e., in dBc/Hz. This is the single sided spectral noise density L{ } and is related to the double sided noise spectrum S ( ) by S ( ) . (19) 2 In general the relation between the spectral density of the input Lx { } and the output Ly { } is given by L{ } = Ly { } = Lx { } |H ( )|2 (20)

with r (z ) and v (z ) being the z -transforms of v [n] and r [n], respectively. Substituting = 0 into (12) and (13) leads to a type-I PLL. It is interesting to note, that the input/output transfer functions are scaled versions of the phase transfer functions ol (z ) (12) and cl (z ) (13), fv (z ) = fref ol (z ), e (z ) fv (z ) Hcl (z ) = = fref cl (z ). Nr (z ) Hol (z ) = (14) (15)

Considering the reference frequency fref as input signal to the system results in similar transfer functions, where the scaling changes from fref to Nr in (14) and (15). The relationship between the frequency and phase transfer-function is not surprising, since frequency information is converted into phase information so that both frequency and phase lock is achieved simultaneously. C. s-Domain Transfer Function Although the z -transform is the natural description of a discretetime system it is common to approximate it with a linear continuoustime system in the s-domain. The accuracy of the linearization depends on the PLL bandwidth. The rule of thumb used in practice, states that the sampling rate fref must be at least 10 times larger than the PLL bandwidth [5], so that the approximation z = esTref 1 + sTref holds. Substituting (16) into (12) gives ol (s) =
2 fref s + fref v (s) = e (s) s2

(16)

where H ( ) is the transfer function from x to y . Figure 1 shows two noise sources DCO and T DC . In the following we will investigate the physical properties and their transfer function to be able to evaluate (20). 1) DCO noise: An ideal oscillator would produce a single frequency 0 and its power would be concentrated on two single spurs in the power density spectrum. However, in practice the oscillator suffers from several effects and spreads the power over nearby frequencies. Figure 3 shows the phase noise characteristics in the double-sided phase noise spectrum S ( ), where the phase noise in dBc/Hz is plotted against the frequency deviation from the carrier. The phase noise traverses through 3 regions: 3 icker noise with a slope of 30 dB/dec, 2 noise wander with a slope of 20 dB/dec, and 1 noise jitter with 0 dB/dec [6]. The phase noise can be converted into frequency noise by integration (20 dB/dec), or vice versa, by differentiation (+20 dB/dec), i.e., S ( ) . w2 The DCO noise transfer function is given by S ( ) = HDCO (z ) = fv (z ) (z 1)2 = . 2 DCO (z ) (z 1) + (z 1) + (21)

(17)

the open-loop transfer function and into (13) results in cl (s) =

(18)

(22)

the closed-loop transfer function. Figure 2 shows the s-domain approximation of the z -domain model in Fig. 1.
Norm
fref

FPC

PD

Loop Filter

Norm
fref

Normalized DCO
1 K

DCO
K

DCO

To evaluate the phase noise L{ } due to the DCO noise we can calculate S ( ), convert it to S ( ) by using (21) and then halve it according to (19). However, since the signal v [n] is also available in the model we can obtain L{ } directly. Substituting the transfer function DCO (z ) = (z 1) v (z )z 1 = Tref . (23) DCO (z ) (z 1)2 + (z 1) +

Nr

1 s

fv

fref s v

FPC
1 s

T DC

Fig. 2. A s-domain model of a phase domain All-digital phase-locked loop.

into (20) results in the single-sided power spectrum L{ } due to the DCO noise. 2) TDC noise: The second noise source T DC in the feedback path is due to the FPC. Section. IV describes an actual implementation of an ADPLL, where the fractional part of the variable phase v [n] is measured by a time-to-digital converter (TDC). Unfortunately, the TDC suffers from quantization effects and, thus,

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Nr

r [n]

e [n]

LF

N v [ n]

fref K

d[n]

CKV
DCO

[n]

v [n]

REF
v [i] TDC
1 Tv

CKR [n] r [n]

F REF @ fref

CKR @ fref

31 4

73 4

CKV @ fv

Fig. 4. An ADPLL implementation for wireless communication systems [10].

v [i] e [n]

1 0
n0

2 0
n0 + 1

3 0
n0 + 2

5 0
n0 + 3

6 0
n0 + 4

8 0
n0 + 5

introduces noise. Since a variable period Tv is much larger than the resolution of the TDC, the quantization noise can be modeled as white noise. The TDC noise transfer function with respect to variable frequency and variable phase is HT DC (z ) = and T DC (z ) = v (z ) (z 1) + = . T DC (z ) (z 1)2 + (z 1) + (25) (z 1)2 + (z 1) fv (z ) = fref T DC (z ) (z 1)2 + (z 1) + (24)

Fig. 5.

Retiming mechanism with Nr = 1.5.

reference signal fref , while in (13) the phase r (z ) is related to N fref . However, (20) in [3] equals the frequency transfer function Hcl (z ) in (15). Furthermore, the z -domain model, Fig.7 in [3], does not reect the actual implementation, since the loop normalization with fref is missing. V. S IMULATIONS The simulated ADPLL is designed for frequencies in the range from 2.4 to 2.5 GHz with a fref = 13 MHz reference clock. The DCO is operated with respect to the free running frequency f0 = 2.4 GHz which is the output frequency for d = 0. The desired ss is 2.413 GHz. We assume that the DCO gain K is frequency fv = K and neglect quantization effects. perfectly compensated K Figure 6 compares the step response of the z -domain model, the s-domain model, and the simulation output of the implementation in Fig. 4. While, the z -domain model and the simulation output cannot be distinguished from each other, the s-domain model differs increasingly with the bandwidth of the ADPLL. Figure 7 depicts the difference between the s-domain model and the actual simulation output. The accuracy depends on the PLL bandwidth and the outputs diverge up to 600 kHz. The z -domain model is much more accurate, the error is in the range of 2 kHz in Fig. 8. The main difference between the z -domain model and the implementation is the sampling process. The implementation updates the PLL on the rising edge of the CKR signal, while the model uses REF . While REF has exactly the frequency fref , CKR is only on average on rate fref due to the retiming mechanism. However, since the period of Tv is much smaller than the period of the reference Tref the model error is very small, c.f. Fig. 8. Figure 9 shows the magnitude response of the phase-domain type-II ADPLL for three different loop lters in the z -domain and its s-domain approximation. Increasing the bandwidth of the PLL increases the lock time. The gain of about 142 dB corresponds to the 13 MHz of the reference frequency, since an integer change of Nr changes the output frequency fv by fref . The corresponding DCO noise magnitude response and TDC noise magnitude response are shown in Fig. 10 and Fig. 11, respectively. Note that the bandwidth of the transfer function in Fig. 9 corresponds to the bandwidth of the DCO noise transfer function in Fig. 10. While the bandwidth is independent of the loop lter coefcients, the nal gain of the TDC transfer function depends on them. Note, that a loop lter with good DCO noise suppression has worse TDC noise suppression.

The digital nature of the loop arithmetic, i.e., loop lter and normalization is immune to noise. IV. R ELATIONS TO [3] The ADPLL described in this paper was rst proposed in [9], where the actual implementation was digital apart from of the voltage controlled oscillator (VCO). The digital loop arithmetic is converted to an analog tuning voltage by a digital-to-analog converter. Such a mixed signal implementation is called digital PLL (DPLL) [11]. An ADPLL for wireless communication implementing the same concept was presented in [2] and analyzed in [3]. Figure 4 shows the block diagram of the ADPLL. The additional circuitry compared to Fig. 1 is due to a retiming mechanism, that synchronizes the two clock signals CKV and F REF which correspond to the frequencies, fv and fref . The idea is to delay the rising edge of the reference clock F REF to the rising edge of the variable clock signal CKV [12]. The clock signal for the entire PLL CKR, n corresponds now to positive CKR transitions, is obtained by oversampling the slow F REF clock by the faster CKV clock using a Flip-Flop. Due to the retiming the number of variable cycles within one reference cycle is always an integer number. Thus, the variable phase v [i] is calculated by accumulating 1 at a rate of CKV , where i corresponds to the clock CKV . Resampling the output v [i] at rate CKR yields the variable phase at the reference rate v [n]. Accumulating N at rate CKR gives the reference phase r [n], which is identical to the model in Fig. 1, since the reference normalization with fref and the multiplication with Tref in the FPC cancel each other. However, due to the retiming of the reference clock an error [n] is introduced. A time-to-digital converter (TDC) measures the time between the positive edge of F REF and the positive edge of CKV and normalizes it by a variable period Tv . The retiming concept is illustrated in Fig. 5. The analysis in [3] is restricted to the transfer function of the phase signals. While the open-loop transfer function (18) in [3] corresponds with ol (z ) (12) the closed-loop transfer function (20) in [3] differs by the factor Nr from cl (z ) in (13). This disagreement is due to slightly different models. In [3] the input phase is the phase of the

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x 10 2.42

150

Magnitude Response [dB]

Frequency [Hz]

2.415

130

110

2.41

2.405

=2 =2 step H(z) step H(s) =27 =212 step H(z) step H(s) 8 15 =2 =2 step H(z) step H(s)

|H(z)| with =26 = 29 |H(s)| with =26 = 29 |H(z)| with =2 |H(z)| with =2
4 5

90

=2 =2

12

|H(s)| with =27 = 212

70 7 10

|H(s)| with =28 = 215 10 10

2.4

6 x 10

10

Time [s]

Frequency [Hz]

Fig. 6.
x 10 6 4
5

Comparison of the step responses.

Fig. 9.
20

Magnitude response of a phase-domain ADPLL.

=2 =2

=27 =212
8 15

Magnitude Response [dB]

Model Error [Hz]

2 0 2 4 6 0 1 2 3 4 5 6 x 10 7
5

20

|H |H

(z)| with =26 = 29 (s)| with =26 = 29 (z)| with =2

DCO

DCO

40

|H |H

=2

12

DCO

(s)| with =27 = 212 (z)| with =28 = 215 (s)| with =2
6
8

DCO

60

|H |H

DCO

=2

15

DCO

80 3 10

10

10

10

10

Time [s]

Frequency [Hz]

Fig. 7.

Difference between simulated output and s-domain model.

Fig. 10.

Magnitude response of the phase-noise transfer-function.

Magnitude Response [dB]

=27 =212

110

Model Error [Hz]

1000 500 0 500 1000 1500 2000 0 1 2 3 4 5 6 x 10 7

90

|H |H

(z)| with =26 = 29 (s)| with =26 = 29 (z)| with =27 = 212 (s)| with =27 = 212 (z)| with =28 = 215 (s)| with =28 = 215
6 7

TDC

TDC

70

|H |H

TDC

TDC

50

|H |H

TDC

TDC

30 3 10

10

10

10

10

Time [s]

Frequency [Hz]

Fig. 8.

Difference between simulated output and z -domain model.

Fig. 11.

Magnitude response of the TDC-noise transfer-function.

To evaluate the phase noise transfer functions in (23) and (25) we compare the theory with results from an event-driven simulation, where DCO effects are modeled in the time domain [6]. The noise wander is a random Gaussian process with s L{ } ss (26) Tv = Tv ss 2 fv which results with L{ } = 10 at = 2 500 kHz in Tv = 11 fs. Since the presented model is on to the low frequency fref rather than on the much higher frequency fv , the standard deviation fref has to be computed from Tv . In a rst step we convert the noise at the short period Tv to a noise at the long period Tref by averaging the deviation over one reference cycle. If we modeled also the noise in that way the period deviation of each period Tv within Tref would be constant. The phase noise spectrum would exhibit additional 20 dB/dec, since that effect is similar to
112dB/10

low-pass ltering the phase noise with a moving average lter with cut-off frequency fref . However, the standard deviation for noise wander on period Tref is T Tref = v . Nr (27)

Furthermore, the noise is added as frequency noise rather than on the periods, i.e., 1 ss ss . (28) fref = fv Tv + Tref For Tv = 11 fs we get fref = 4.7 kHz. Since the phase noise power is uniformly spread between DC and the frequency ` Nyquist2 the single-sideband spectral density LDCO = 2fref /fref = 38.3 dBc/Hz. Figure 12 compares the theoretical output (20) L{ } = LDCO |DCO ( )|2 (29)

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40 60

80 100 120 140 160 180 4 10

=2 : simulation

=26 =29: theory =27 =212: simulation =27 =212: theory =2

operates on the low reference frequency and accounts for both, frequency and phase signals. That allows to investigate effects on the output phase and the output frequency as needed. In particular, TDC quantization and oscillator phase noise were investigated. It was shown how the physical characteristics of both noise sources can be incooperated in the model and how the noise propagates through the PLL. The abstract system level model is independent of the actual implementation. Nevertheless relations to an actual implementation were discussed and the theoretical results were compared to the simulation output of that structure. Both, the derived transfer functions and the step response agree with the simulation output. ACKNOWLEDGEMENT
10
6

Phase Noise [dBc/Hz]

=2

15

: simulation

=28 =215: theory

10

10

Frequency [Hz]
Fig. 12. Effect of DCO noise on the output phase noise.

Support of our research by Inneon Technologies Austria AG is gratefully acknowledged. Furthermore, the authors would like to thank N. Da Dalt for fruitful discussions and suggestions for this paper R EFERENCES

80

Phase Noise [dBc/Hz]

100 120 140 160 180 200

=26 =29: simulation =2

=2 : theory

=27 =212: simulation =27 =212: theory =28 =215: simulation =28 =215: theory

10

10

10

10

Frequency [Hz]
Fig. 13. Effects of TDC noise on the output phase noise.

to the phase noise output of event-driven simulations with good agreement. The quantization noise of the TDC can be modeled as white Gaussian noise with tres (30) T DC = ss 12 Tv where tres is the time resolution of the TDC and LT DC = (2T DC )2 /fref [13]. For a TDC resolution of tres = 20 ps, T DC = 0.0875 and LT DC = 92.3 dBc/Hz. The effects on the phase noise is given by (20) L{ } = LT DC |T DC ( )|2 . (31)

Figure 13 shows good agreement between event-driven simulation and theory. Comparing Fig.12 and Fig. 13 shows again the trade-off between TDC noise suppression and DCO noise suppression. The transfer function regarding the output phase noise of the ADPLL due to DCO noise (23) shown in Fig. 12 and due to TDC noise (25) shown in Fig. 13 differ from the output frequency noise in (22) and (24) shown in Fig. 10 and Fig. 11 by additional 20 dB/dec due to the integration. VI. C ONCLUSION In this paper we have presented a comprehensive z -domain model for phase domain all-digital phase locked loops. The discrete model

[1] N. Da Dalt, E. Thaller, P. Gregorius, and L. Gazsi, A compact tripleband low-jitter digital LC PLL with programmable coil in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1482 1490, July 2005. [2] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process, IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 815828, November 2003. [3] R. B. Staszewski and P. T. Balsara, Phase-domain all-digital phaselocked loop, IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing, vol. 52, no. 3, pp. 159163, March 2005. [4] V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, A design procedure for aldigital phase-locked loops based on a chargepump phase locked loop analogy, IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing, vol. 54, no. 3, pp. 247251, March 2007. [5] F. M. Gardner, Charge pump phase-lock loops, IEEE Transactions on Communications, vol. 28, pp. 18491858, November 1980. [6] R. B. Staszewski, C. Fernando, and P. T. Balsara, Event-driven simulation and modeling of phase noise of an RF oscillator, IEEE Transactions on Circuits and SystemsPart I: Fundamental Theory and Applications. [7] C. Joubert, J. F. Bercher, G. Baudoin, T. Divel, S. Ramet, and P. Level, Time behavioral model for phase-domain ADPLL based frequency synthesizer, in Proceedings of the IEEE International Conference on Circuits and Systems (ICECS), 2006, 2006, pp. 167170, a preliminary version of this work is presented at RWS, San Diego, January 2006. [8] S. Dondi, R. Strandberg, M. Nilsson, A. Boni, and P. Anderani, Highlevel design ow for all-digital PLLs, in Proceedings of the IEEE Norchip Conference, 2006, November 2006, pp. 247250. [9] A. Kajiwara and M. Nakagawa, A new PLL frequency synthesizer with high switching speed, IEEE Transactions on Vehicular Technology, vol. 41, no. 4, pp. 407413, November 1992. [10] R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de Obaldia, and P. T. Balsara, All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 22782291, December 2004. [11] R. E. Best, Phase-Locked Loops: Design, simulation, and applications. McGraw-Hill, 2003. [12] F. M. Gardner, Interpolation in digital modems. I. fundamentals, IEEE Transactions on Communications, vol. 41, no. 3, pp. 501507, March 1993. [13] R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, TDCbased frequency synthesizer for wireless applications, in Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE, June 2004, pp. 215 218.

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