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    EE42 100 Wb-Lecture17 080213-F

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    This lecture covered MOSFET transistors and their regions of operation. It discussed the cutoff, triode, and saturation regions for NMOS and PMOS transistors. Equations were provided relating the gate-source voltage (vGS), drain-source voltage (vDS), and drain current (iD) in each region. Load-line analysis was introduced as a way to analyze the behavior of MOSFET circuits by plotting the transistor's I-V characteristics on a graph with the load line. An example NMOS amplifier circuit was used to demonstrate how load-line analysis can determine the voltage transfer characteristics.

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    EE42 100 Wb-Lecture17 080213-F

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    ozanistz
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    This lecture covered MOSFET transistors and their regions of operation. It discussed the cutoff, triode, and saturation regions for NMOS and PMOS transistors. Equations were provided relating the gate-source voltage (vGS), drain-source voltage (vDS), and drain current (iD) in each region. Load-line analysis was introduced as a way to analyze the behavior of MOSFET circuits by plotting the transistor's I-V characteristics on a graph with the load line. An example NMOS amplifier circuit was used to demonstrate how load-line analysis can determine the voltage transfer characteristics.

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    EE42_100_wb-Lecture17_080213-F

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    This lecture covered MOSFET transistors and their regions of operation. It discussed the cutoff, triode, and saturation regions for NMOS and PMOS transistors. Equations were provided relating the gate-source voltage (vGS), drain-source voltage (vDS), and drain current (iD) in each region. Load-line analysis was introduced as a way to analyze the behavior of MOSFET circuits by plotting the transistor's I-V characteristics on a graph with the load line. An example NMOS amplifier circuit was used to demonstrate how load-line analysis can determine the voltage transfer characteristics.

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    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    40 views35 pages

    EE42 100 Wb-Lecture17 080213-F

    Uploaded by

    ozanistz
    This lecture covered MOSFET transistors and their regions of operation. It discussed the cutoff, triode, and saturation regions for NMOS and PMOS transistors. Equations were provided relating the gate-source voltage (vGS), drain-source voltage (vDS), and drain current (iD) in each region. Load-line analysis was introduced as a way to analyze the behavior of MOSFET circuits by plotting the transistor's I-V characteristics on a graph with the load line. An example NMOS amplifier circuit was used to demonstrate how load-line analysis can determine the voltage transfer characteristics.

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    EE 42/43/100 Introduction to Digital Electronics

    Lecture 17 8/2/13 Instructors: Prof. Connie Chang-Hasnain Dr. Wenbin Hsu

    Lecture 17
    Review of Diode Structure and Circuits MOSFET Transistors and Regions of Operation Load-Line Analysis of MOSFET Circuits

    Formation of pn Junction

    Built-in Electric Potential


    Depletion Region

    Immobile Negatively Charged Ions

    Immobile Positively Charged Ions

    Potential Barrier

    potential barrier seen by holes

    potential barrier seen by electrons

    Forward Bias & Reverse Bias


    VF VR

    -VF

    +VR

    I-V Characteristics of Diodes

    I-V Characteristics of Combined Diodes

    Quiz 1
    If all 3 diodes on the left are identical and all have infinite reverse breakdown voltage, which one below would be the best description of the i-v characteristic of the combination?

    E Answer: C

    Quiz 2

    Assume voltages of 0.7 V for all diodes including the Zener diodes when current flows in the forward direction. The i-v characteristic of the combined circuit is as shown. What is the value of Y? (A) -2.6V (B) -4.0V (C) -4.4V (D) -5.8V (E) Unknown Answer: D

    Quiz 3

    Answer: C A diode having the i -v characteristic (light blue curve) shown on the right is powered by a voltage source shown on the left, which one is the correct load-line for this circuit?

    Photovoltaic (Solar) Cell

    potential barrier seen by holes

    ID (A)

    potential barrier seen by electrons

    in the dark VD (V) with incident light

    Ideal Diode Model


    In the ideal diode model, we ignore the small forward-bias voltage drop across the diode. Its I-V characteristic is given below: I
    Reverse bias I 0, any V < 0 Forward bias V 0, any I > 0 V

    An ideal diode passes current only in one direction.

    Large-Signal Diode Model


    If we choose not to ignore the small forward-bias voltage drop across the diode, it is a very good approximation to regard the voltage drop in forward bias as a constant, about 0.7V. We then have the improved "large signal model".
    I

    - 0.7+

    Reverse bias I 0, any V < 0

    V+

    Forward bias V 0.7, any I > 0 V


    0.7

    Example: Ideal Diode Model

    When the sinusiodal source is positive, D2 is on and D1 is off. When the source is negative, D1 is on and D2 is off.

    Example (continued)

    = vo (t ) 2.5sin(2 t ) v0 (t ) = 2.5sin(2 t )

    for 0 t 0.5 for 0.5 t 1

    Quiz 4
    Assume ideal diodes (0V forward bias). Which one below is the best description of transfer characteristic (vo versus vin)? Answer: C
    vo

    vin

    Example: Clipper Circuit

    When the voltage source is positive but between 0 and 10V, D1 and D3 are both off. vo (t ) = 15sin(200 t ) When the voltage source is positive and greater than 10V, D3 is off , D1 is on, and D2 is in breakdown vo (t ) = 10 When the voltage source is negative, D3 is on and D1 is off. vo (t ) = 0

    Quiz 5

    The above voltage-regulator circuit is to provide a constant voltage of 5 V to a load from a variable supply voltage. Assume ideal Zener diode for this circuit. The load current varies from 0 to 100 mA and the source voltage varies from 10 to 15 V. What is the maximum resistance allowed for R? (A) 50 (B) 100 (C) 150 (D) 200 (E) 250 Answer: A

    Metal-Oxide-Semiconductor-Field-EffectTransistor (MOSFET)

    NMOS vs. PMOS

    NMOS

    PMOS

    Powering NMOS Transistor

    body connected to source. pn junction between drain and body reverse-biased.

    Regions of Operation in NMOS


    Cutoff Region vGS Vto Triode Region vGS Vto and vDS vGS Vto or vGS Vto and vGD = vGS vDS Vto Saturation Region vGS Vto and vDS vGS Vto or vGS Vto and vGD = vGS vDS Vto
    Threshold voltage Vto, typically a fraction of a volt to one volt.

    Operation in the Cutoff Region

    No channel forms

    vGS Vto iD = 0

    Operation in the Triode Region


    Channel induced

    vGS Vto and vDS vGS Vto iD = K [2( vGS Vto )vDS vDS 2 ] where K = ( W KP KP typically 50 A/V 2 ) L 2 A channel of n-type material is induced under the gate. The channel becomes thicker with increasing vGS . The device behaves like a resistor whose value depends on vGS .

    Physical Meaning of the Equation

    In triode region: Gate voltage vGS on the source side. Gate voltage vGD =vGS vDS on the drain side. iD = K [2( vGS Vto )vDS vDS 2 ] 1 = K [2( vGS vDS Vto )vDS ] 2
    Average

    Operation in the Saturation Region


    Channel pinched-off

    vGS Vto and vDS vGS Vto W KP iD = K ( vGS Vto ) 2 where K = ( ) L 2 When vGD equals Vto , the channel thickness at the drain end becomes zero. Further increases in vDS will not increase iD (iD becomes saturated).

    Physical Meaning of the Equation

    In triode region: iD = K [2( vGS Vto )vDS vDS 2 ] Entering saturation region: v= vGS Vto DS = iD K [2( vGS Vto )( vGS Vto ) ( vGS Vto ) 2 ] = K ( vGS Vto ) 2 (iD becomes saturated and indpendent of vDS )

    I-V Characteristics (NMOS Transistor)


    v= vGS Vt 0 DS

    Powering PMOS Transistor

    polarities of all voltages and currents are reversed (or with negative values as shown). body connected to source. pn junction between drain and body reverse-biased.

    MOSFET Summary

    MOSFET Summary
    NMOS
    Cut-off Saturation Triode

    Vto

    vDS + Vto

    vGS

    PMOS
    Triode Saturation Cut-off

    vDS + Vto

    Vto

    vGS

    Simple NMOS Amplifier Circuit

    VDD = RD iD (t ) + vDS (t )

    Load-Line Analysis

    VDD = RD iD (t ) + vDS (t )

    vGS and vDS versus time

    Av = 12V/2V= 6

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