Q3. What is race around condition?

Q1. What are positive logic & negative logic? Ans. It is concerned with R.S. – flip flop . i.e. When is RS-FF, we have reset one F.F.
Ans. When any clock dependent digital ckt. Works on positive edge of clock pulse at same time, which is not possible, means at R=S=1 , output comes in high,
i.e. logic 1 (+5.v) is called positive logic . When works on negative edge of state or rapidly changes from 1 to 0 & viceversa at high speed & we are not able
clock pulse i.e. logic ‘o’(+ov) is called negative logic. to get stable output, this is called race around condition.

Negative logic Q4. Realize an AND gate using NOR gate.

Ans.

Positive logic
A
(A + B) = A.B=AB
NOR

Q2. Convert (27.10)10 (11011. 00011)2

NOR
2 27 1 = 11 0 11 A
NOR
2 13 1

2 6 0

2 3 1 Mathematically A + B = A . B = A.B ( using De morgns thrm.

1
( X +y) = X.y and X = x.

Q5. Realize OR gate using NOR.

. 10 A+B A+ B = A+ B
2 A
-----
.20 0
2 B
---- OR gate
.40 0
2 Q6.Realize OR, AND gate using NAND gate.
---- Ans.
.80 0 .00011
2 A
N N
---- AND AND
B
.60 1 =
2 AB
----
.20 1 Which is And gate A
N
2 A AND A.B =A+B
---- Mathematically = A + B ⇒ This OR-
N gate Mathematically
.40 0
B AND
N
B AND
Q7. Realize XOR, XNOR, XNOR gates. Draw their truth tables also.
Ans.

XOR gate
A B A B A + B ⇒(A + B) = A.B
T.T 0 0 1 1 0 1 1
A y
XOR A B 0 1 1 0 1 0 0
B Y 1 0 0 1 1 0 0
0 0 1 1 0 0 1 0 0
0 L.H.S = R.H.S
0 1
1
1 0 Q9. Discuss R-S flip flop. Also draw D flip flop using R-S flip flop.
XNOR
1 gate Ans. R-S (Reset – Set) flip flop used to set & reset or to store 1 bit at a time. It is
1 1 calculated that R-S flip flop, when R=S=o produces “NO CHANGE” in output,
0 which means output remain same as that previous one.
A XNOR y

A B R Q
Y=A.B+A.B Y NOR
0 0
1
0 1
0
1 0
0 Q
1 1 S
NOR
1

Q8. State & Prove Demorgans theorm using truth table. CLK
Ans. A.B = A+B R Q SR
CLK QQ
1
S Q 0 0
A B A B A.B A.B = A + B No change
1
0 0 1 1 0 1 1 0 1
0 1 1 0 0 1 1 0 1
1 0 0 1 0 1 1 1
L.H.S = R.H.S
1 1 0 0 1 0 0 1 0
1 0

(A + B) = A. B
 1
1 1 Q12. Exercise for students.
undefined.
1. (1011)2 = ( )8 = ( )16
2. (100.001)10 = ( )2 = ( )16
D- Flip Flop: When inputs of R-S F.F are connected to each other by an invertors shown
3. (7AB)16 = ( )2 = ( )10
in figure it becomes D-F.F. It is also called buffer as it produces output same as that of 4. Binary to gray code (a) 1010 b 01011
Input.
Q13. Simplify expression using Boolean algebra formulas.

Q 1. (x +y) (x + y) = x.x + x.y + x.y + y.y

S CLK D Q
Q [ As we know 1. A.A = A 2. A.A = 0 ]
1 0 0
CL R 1 = x + xy + xy
K S Q 1 1 1 = x(1 + y) + xy [using 1+A =1)
F
=x + x.y (or 1 + A =1)
R =x(1+y)
= x

Q10. Convert following Q14. Using two 2x4 decoders design 3x8 decoder.
Binary number into Gray code.
D0
a. (1011)2 It’s method is as follows by leaving carry A0 20 2x4
D1
A1 21 Decoder
1 0 1 1 D2

A2 E D3

1 1 1 0
D0
Q11. Convert Binary to Access-3 code. Add decimal.
20+
a. (100) 2 ⇒ 100 (3)10 or (11)2 to any binary to have Access-3 code
D1
100 4 21 2 x4
001 3 Decoder D2
----- + ------
111 7 E D3

Q11 Convert Gray code to Binary code.

Ans. A. (1110)

1 1 1 0
Here using A2 bit as a chip select.

Q15. Discuss half subtractor?

Ans. X Y Difference(D) Borrow (B)
(1 0 1 1) i.e. gray (1110) = (1011)2
0 0 0 0
 0 1 1 1
1 0 1 0 S1
1 1 0 0 S0
Y
0
D = X.Y + X.Y 0
I0
0
D = XY + XY
XOR 1
I1
1
B=X.Y
0
AND I2
1
1
NOT I3

Q16. Define 2 complement using example. Also subtract (5-7)10 using 2’s
complement.
Ans. It can be calculated by first calculating1’s complement & then by adding ‘1’ to
1’s complement we get 2’s complement. E.g. I0

I0 A
1011 =0100 1’s complement N
+1 D
------
101 2’s complement I1 I1
A
To subtract using 2’s complement N OR
D Y
i.e. 5 – 7 = 5 + (-7) = 5 + ( 2’s complement of(7) )
= 101 + 001 111 I2
= 101 000 1’s complement I2
A
001 1 N
-------- ----- D
110 001 - 2’s complement
=110 I3
I4
A
i.e. 110 is 2’s comp. Of (-2) N
As (-2) = (2’s comp. Of (2) )
010 1’s 101 2’s (110)…….

Q17. Draw & explain ( 4 to 1) MULTIPLEXER:-

Ans. Device having 4-Inputs & 1-output called MUX. Shown in figure. As 4 –
Input(2I02) device we need two select lines So & S1.
4X1 Q18. Write applications of MULTIPLEXER.
I1 MUX
y Ans.
I2 1. To convert signal from time Domain to frequency domain.
2. To transmit telephone signals on a same channel & at same time
I3 multiplexing is used.
S1 S0
 3. For analog information frequency division multiplexing is used i.e.
Telephone.
4. For digital information i.e (Audio signal video signal) we use time Division A
multiplexing. B

Long answer type question. C

Q1. Draw truth table of full adder circuit. Realize the full adder circuit using NAND
gates?
Ans.

A B C SUM CARRY
C
0 0 0 0 0
0 0 1 1 O As carry = ABC + ABC + ABC + ABC
0 1 0 1 0
0 1 1 0 1 Carry = ABC +
ABC + ABC + ABC AB\C C C
1 0 0 1 0
1 0 1 0 1 AB
1 1 0 0 1 AB 1
1 1 1 1 1 AB 1
AB 1
Su = ABC + ABC + ABC + ABC
(
i.e. carry (c) = AB + BC + AC
A A ABC
N
B
B A AB
NAND
C
C B

BC
AB . BC . AC
(ABC) B
A A Su NAND
NAND
N m
N C
B
= AB + BC + AC
C
A AC
C NAND = AB + BC + AC
(
C
ABC = Carry
N

(
A ABC Q2. Minimize following Boolean expression using K-map.
B F (A,B,C,D) = Σm (0,1,4,5,8,9,15) + ϕ ( 2,7,13).
Ans. Following expression can be written
 (A+B) 00 00 4

Pair (I) CD CD CD CD
AB\CD 00 01 11 10 (A+B) 01 01 5

A.B 00 10 14 12
18 Pair - II (A+B 11 3 7

A.B 01 11 15 *13
19 (A+B) 10 2
06
Pair - III
3
A.B 11 *7 115 11

A.B 10 *2 6 14 10
Here logic ‘0’ = A & logic ‘i’ = A opposite to previous question. It is of form (POS). By
pairing it is seen expression becomes.

Y = (A+C) (A+B+C) ----(1)

This equation can be represented by following ckt. Using only NOR. gates as follows.
Here A = logic ‘o’ A B A
A= log ‘1’ A+C
y
NOR
From above pairing scheme , it can be written as where ϕ ( 2,7,13) NOR
represents bits with * (denoting don’t care bits) used only for pairing C
purposes.
A
A
NOR A+B+C

F = A . C + A C D + ABD NOR

FROM PAIR I
FROM PAIR II FROM PAIR C
III NOR
C
NOTE:- In above (Σ) represents S.O.P (sum of products) form & ‘m’ represents minimum
terms.
If (Π) represented then it is (POS) (product of SUM) form. (M) represents maximum
terms.
In both above case while dealing with K-maps, methods used are opposite to each other. Where y = (A+C) + (A + B + C)
Explained in next question.
= (A + C) . (A + B + C) using Demorgans thrm.
Q3. Minimize following expressions using K-maps
= (A +C) (A + B + C) . (X+Y) = X.Y)
Ans. Y= Π M (0 , 1 , 6)

C C C
Q4. Find resultant of the following
AB 0 1
Ans. (101011101.1)2 = ( )16
 Make groups of 4 –bits of binary given.
i.e.
Truth table for 3-to-8-Line Decoder
0001 0101 1101 . 1000
Enable Inputs Outputs.
(15D. 8) 16 E A2 A1 A0 D7 D6 D5 D4 D3
D2 D1 D0
b. (76 A B)16 = (?)8 0 X X X 0 0 0 0 0

0 0 0

AISB LSB 1 0 0 0 0 0 0 0 0

(0111011010011010)2 0 0 1

=(073232)8 1 0 0 1 0 0 0 0 0
0 1 0

Above starting from LSB in binary & make groups of 3-bits as shown & we get 1 0 1 0 0 0 0 0 0

result. 1 0 0
0 1 0 1 1 0 0 0 0 1
A 0 D
c. (101010)2 + (11011)2 0 0 0
2 0
1 1 0 0 0 0 0 1 0

A⇒ 101010 0
0 0 0

1
11011 0 D 1 1 0 1 0 0 1 0 0

-------- 1
0 0 0
A
(1000101)2 1 1 1 0 0 1 0 0 0
0 0 0 0
0
Q5. What is decoder. Explain in detail with Truth Table of “3 to 8 line”
1 Decoder.
D 1 1 1 1 1 0 0 0 0

Ans. Decoder:- is a combinational circuit that converts binary information2 from the 0 0 0

‘n’-coded inputs toa maximum of ‘2n” unique outputs. It the n-bit coded
information has unused bit combinations. The decoder may have 0 less than 2n
outputs. 1 D Q6. Draw & explain working of Asynchronous shift counters. used for counting
N
Above is also called N to M line decoder. Where M≤ (2) . A decoder having N-
3 from 0000 to 1111 i.e. 0 to 15.
Ans. As we know for counting 0 to 15 ie 24 = 16, which means we need at least four.
inputs & M-outputs also called (NxM) decoder.
1 Flip Flops . So using D-Flip Flop we have following ckt.
3-to-8 line Decoder shown in fig using three data inputs A0, A1 0
& A2,
D
which are A B C
decoded into eight outputs. Where each output represents one of the D
4
combinations of the three binary input variables.
In this decoder, we also use one enable (E) inputs to control operation
1
when E=o
i.e. outputs are equal to ‘o’ regardless of inputs. 0 D CLK
D Q D Q D Q D Q

5
Q Q Q Q

1
1 D
6
CLK
1
1 D A
7

B 0
Enable (e) 0 1 0 1 0 1 1
C

3 – TO- 8- line decoder. D

0 0 1 1 0 0 1 1