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William Stallings Computer Organization and Architecture 6 Edition System Buses

This chapter discusses computer system buses and how they connect the central processing unit (CPU), main memory, and input/output (I/O) devices. It explains that a bus provides data transfer and control signal pathways between these components. Buses allow the CPU to fetch instructions and data from memory locations and transfer data to and from I/O devices using addresses, data, and control signals over the bus connections. The chapter also covers interrupt handling, where devices can signal the CPU to pause normal processing and handle the interrupt request.

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90 views29 pages

William Stallings Computer Organization and Architecture 6 Edition System Buses

This chapter discusses computer system buses and how they connect the central processing unit (CPU), main memory, and input/output (I/O) devices. It explains that a bus provides data transfer and control signal pathways between these components. Buses allow the CPU to fetch instructions and data from memory locations and transfer data to and from I/O devices using addresses, data, and control signals over the bus connections. The chapter also covers interrupt handling, where devices can signal the CPU to pause normal processing and handle the interrupt request.

Uploaded by

Pritam Sirpotdar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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William Stallings Computer Organization and Architecture 6th Edition Chapter 3 System Buses

Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals

What is a program? A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed

Function of Control Unit For each operation a unique code is provided


e.g. ADD, MOVE

A hardware segment accepts the code and issues the control signals We have a computer!

Components The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out
Input/output

Temporary storage of code and results is needed


Main memory

Computer Components: Top Level View

Instruction Cycle Two steps:


Fetch Execute

Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC
Unless told otherwise

Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

Execute Cycle Processor-memory


data transfer between CPU and main memory

Processor I/O
Data transfer between CPU and I/O module

Data processing
Some arithmetic or logical operation on data

Control
Alteration of sequence of operations e.g. jump

Combination of above

Example of Program Execution

Instruction Cycle State Diagram

Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program
e.g. overflow, division by zero

Timer
Generated by internal processor timer Used in pre-emptive multi-tasking

I/O
from I/O controller

Hardware failure
e.g. memory parity error

Program Flow Control

Interrupt Cycle
Added to instruction cycle Processor checks for interrupt
Indicated by an interrupt signal

If no interrupt, fetch next instruction If interrupt pending:


Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

Transfer of Control via Interrupts

Instruction Cycle with Interrupts

Program Timing Short I/O Wait

Program Timing Long I/O Wait

Instruction Cycle (with Interrupts) State Diagram

Multiple Interrupts Disable interrupts


Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur

Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

Multiple Interrupts - Sequential

Multiple Interrupts Nested

Time Sequence of Multiple Interrupts

Connecting All the units must be connected Different type of connection for different type of unit
Memory Input/Output CPU

Computer Modules

Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals
Read Write Timing

Input/Output Connection(1) Similar to memory from computers viewpoint Output


Receive data from computer Send data to peripheral

Input
Receive data from peripheral Send data to computer

Input/Output Connection(2) Receive control signals from computer Send control signals to peripherals
e.g. spin disk

Receive addresses from computer


e.g. port number to identify peripheral

Send interrupt signals (control)

CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts

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