EE 466: VLSI Design

Lecture 03
Channel Length Modulation
The inversion layer charge Q
I
represents the total mobile electron
charge on the surface and its
expression at the source end of the
channel is:
Q
I at x=0
=-C
ox
(V
GS
-V
T0
) and the
inversion layer charge at the drain end
of the channel is expressed as: Q
I at
x=L
=-C
ox
(V
GS
-V
T0
-V
DS
)
At the edge of saturation when the
drain-to-source voltage reaches
saturation (V
DS
=V
DSAT
=V
GS
-V
T0
) the
inversion layer charge at the drain end
becomes zero.
We can approximate the inversion
layer charge at the drain end by Q
I at
x=L
=0 (even though this is not quite
true)
When V
DS
=V
DSAT
, the channel is
pinched off at the drain end.
Further increase of the drain-to-
source voltage (V
DS
>V
DSAT
) results in
even a larger pinched-off portion of
the channel.
The effective channel length is
reduced to: L=L-AL where AL is the
length of the channel where Q
I
=0.
The pinch-off point moves from the
drain end of the channel towards the
source end with increasing V
DS
.
Channel Length Modulation
For L<x<L the channel voltage is
V
c at x=L
=V
DSAT
.
The electrons traveling from
source to drain traverse the
inverted channel segment of
length L and then they are
injected into the depletion region
of length AL that separates the
pinch-off point from the drain
edge.
The gradual channel
approximation is valid in this
region and is given by:
I
DSAT
=(
n
C
ox
)/2(W/L)[V
GS
-V
T0
]
2
The effective channel length for
the MOSFET operating in
saturation is now L and the above
equation accounts for the actual
shortening of the channel.
Shortening of the channel is also
known as channel length
modulation.
If L is replaced by L in the
equation we can show that the
computed saturation current using
L is greater than the new I
DSAT
computed using L.
Channel Length Modulation
We must modify the equation for
saturation current so that it
reflects the dependency on VDS.
Note that the saturation current
will increase with increasing VDS
since L decreases with increasing
VDS.
The first term of the equation
accounts for the channel length
modulation effect.
Let 1-AL~1-V
DS
, with being
an empirical model parameter
called the channel length
modulation coefficient.
Assume that V
DS
<<1 then the
saturation current becomes:
The above equation can be used
with sufficient confidence for
most first order hand calculations
( )
2
0
2
1
1
T GS
ox n
DSAT
V V
L
W C
L
L
I
|
|
|
|
.
|

\
|
A

=

DSAT
V
DS
V L A
( ) ( )
DS T GS
ox n
DSAT
V V V
L
W C
I

+ = 1
2
2
0
TheThresholdVoltage
Anygate-to-sourcevoltage
lessthanV
T0
isnot
sufficienttoestablishan
inversionlayer.
TheMOSFETconductsno
currentbetweenitssource
anddrainterminalsunless
V
GS
isgreaterthanV
T0
.
Increasingthegate-to-source
voltageaboveandbeyond
V
T0
willnotaffectthe
surfacepotentialandthe
depletionregiondepth.
Thereare4physical
propertiesthataffectthe
thresholdvoltagenamely(i)
theworkfunctiondifference
betweenthegateandthe
channel,(ii)thegatevoltage
componenttochangethe
surfacepotential,(iii)the
gatevoltagecomponentto
offsetthedepletionregion
chargeand(iv)thevoltage
componenttooffsetthefixed
chargesinthegateoxide
andinthesiliconoxide
interface.
qV
T0
E
c
E
i
E
Fp
E
v
2u
F
u
F
u
F
Metal
(Al)
Oxide
(SiO
2
)
P-typeSemiconductor
(Si)
TheThresholdVoltage
Theworkfunction
difference(u
gate-to-channel
)
reflectsthebuiltin
potentialoftheMOS
structurewhichconsistsof
thep-typesubstrate,the
thinsilicondioxidelayer
andthegateelectrode.
u
GC
=u
F
(substrate)u
M
ifthegatematerialis
metal(Aluminum)
Ifpolysiliconisthegate
material:u
GC
=
u
F
(substrate) u
F
(gate)
Anexternallyapplied
voltagemustbechanged
toachievesurface
inversioni.e.tochange
thesurfacepotentialby-
Thedepletionregion
chargedensityatsurface
inversion(u
S
=-u
F
)is
Q
B0
=-(2qN
A
c
Si
|-2u
F
|)
-1/2
Assumingthatthe
substrateisbiasedata
differentvoltagelevelthan
thesource(atground)
thenthedepletionregion
chargedensitycanbe
expressedasafunction
ofthesource-to-body
voltageV
SB
:Q
B
=-(2qN
A
c
Si
|-
2u
F
|+V
SB
)
-1/2
Thethirdcomponent
offsetsthedepletionregion
chargeandisequalto
Q
B
/C
ox
(C
ox
=c
ox
/t
ox
).
TheThresholdVoltage
Thegatevoltagethatis
necessarytooffsettothe
fixedpositivecharge
densityQ
ox
(atthe
interfacebetweenthegate
oxideandthesilicon
substrate)is
Q
ox
/C
ox
.
Combiningallthevoltage
componentswecan
determinethethreshold
voltage.Forzerosubstrate
biasV
T0
isgivenby:
V
T0
=u
GC
-2u
F
-Q
B0
/C
ox
-Q
ox
/C
ox
Thusdeterminethe
expressionfornonzero
substratebias.
Body effect
( )
F SB F T T
V V V u + u - + = 2 2
0

ox
Si A
C
qN c

2
=
Themostgeneralformof
thethresholdvoltageis:
V
T
=u
GC
-2u
F
-Q
ox
/C
ox
-Q
B
/C
ox
V
T
=V
T0
-(Q
B
-Q
B0
)/C
ox
(Q
B
-Q
B0
)/C
ox
=((2qN
A
c
Si
)
-1/2
)
/C
ox
*((|-2u
F
+V
SB
|)
-1/2
-(|2u
F
|)
-
1/2
)
This becomes the most
general expression of the
threshold voltage with the
parameter gamma being:
TheThresholdVoltage
Gammaiscalledthe
substrate-biasorthebody
effectcoefficient.
Thegeneralexpressionfor
thethresholdvoltagecan
beusedforboththen-
channelandp-channel
devices.
Thedifferencesareas
follows:
SubstrateFermipotential
u
F
isnegativeinnMOS
butpositiveforpMOS.
Thedepletionregion
chargedensitiesQ
B0
and
Q
B
arenegativefor
nMOSbutpositivefor
pMOS
Furtherdifferences:
Thesubstratebias
coefficient ispositivefor
nMOSandnegativefor
pMOS.
Thesubstratebiasvoltage
V
SB
ispositiveinnMOS
butnegativeforpMOS.
Typicallythethreshold
voltageofan
enhancementmoden-type
MOSFETisapositive
quantitywhilethatofap-
typeMOSFETisnegative.
Sub-Threshold Conduction
Ideally at V
GS
< V
T
, I
D
= 0.
The MOS device is partially
conducting for gate voltages below
the threshold voltage.
This is termed sub-threshold or weak
inversion conduction.
In most digital applications the
presence of sub-threshold current is
undesirable. Why?
.most digital applications . Does
this mean some digital applications
can tolerate sub-threshold currents?
A Sub-threshold digital circuit
manages to satisfy the ultra-low
power requirement. How?
What type of digital applications can
benefit from this ultra low power
design approach?
Subthreshold Conduction
Below cut off current does not abruptly
become zero
Falls off exponentially
Useful in low power CMOS VLSI design
) 1 (
0
T
ds
T
t gs
v
V
nv
V V
ds ds
e e I I

=
8 . 1 2
0
e v I
T ds
| =
Junction Leakage
Conduction even
when transistor is in
cut-off
Substrate to diffusion
junctions are reverse
biased
However reverse
biased diodes do
conduct leakage
current
) 1 ( =
T
D
v
V
S D
e I I
Leakge Current
When the junction bias voltage is
significantly more than the thermal voltage
(~26mV @room temperature) the leakage
current is Is
Junction leakage limits storage time in on-
chip memory elements
Requires refreshing dynamic nodes
Tunneling effects
Ideal MOS model
High input impedence
No static current flow through the gate terminal
Quantum mechanical effect
Carriers tunnel through insulating barriers with finite
probability
Insulating barrier has to be very thin for appreciable
current
Current gate oxide thickness ~10-15
Single atomic layer of silicon ~3
Tunneling current
Current technology nodes
Tunneling current as significant as junction leakage
and sub-threshold conduction
Technique to reduce tunneling current
Use high-K materials in the gate oxide layer
High dielectric constant makes high gate
capacitance
Reduces the need to reduce the oxide thickness
Silicon Nitride is a good candidate for such materials
Temperature Effects
Effect on Mobility
Carrier mobility
decreases with
temperature
k is a parameter
usually in the range
1.2-2.0

k
r
r
T
T
T T

|
|
.
|

\
|
= ) ( ) (
Temperature effects
Threshold voltage
Vt decreases linearly with increase in
temperature
Junction leakage also increases with
increase in temperature
All combined results in decrease of On
current and increase of Off current
Temperature Issues
Circuit performance is therefore generally worse at high
temperatures
Conversely cooling can enable better performance
Cooling techniques
Convection
Natural
Fans
Heat sinks
Active cooling
Water cooling
Liquid nitrogen
Cost of methods have to be justified
Non-Ideal I-V Effects (Summary)
Miniaturization has led to modern
devices having nonideal
characteristics
The saturation current increases
less than quadratically with
increasing V
GS
.
Velocity saturation and mobility
degradation are two of the effects
that cause the non quadratic
current increase with V
GS
.
When carrier velocity ceases to
increase linearly with field
strength we have velocity
saturation.
The current I
DS
is lower than
expected at high V
DS
.
There are several sources of
leakage that result in current flow
when the transistor is expected to
be OFF.
The source and drain diffusion
regions are form reverse biased
diodes which experience junction
leakage into the substrate or well.
The current into the gate I
G
is
ideal zero, however as gate oxide
thickness is reduced electrons
tunnel through the gate, causing
some current.