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VHDL Ass1 Binary Multiplier 2005

This document describes the design of an 8-bit by 8-bit binary multiplier for unsigned numbers. The design uses two 4-bit array multipliers, a 20-bit adder, and a 20-bit shift register controlled by a control unit. It performs multiplications by breaking numbers into 4-bit groups, multiplying those groups in parallel, adding the results, and shifting the registers. The deliverables are the control unit state tables, a circuit diagram, a test bench multiplying various cases, and VHDL code/schematics for each component.

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66 views2 pages

VHDL Ass1 Binary Multiplier 2005

This document describes the design of an 8-bit by 8-bit binary multiplier for unsigned numbers. The design uses two 4-bit array multipliers, a 20-bit adder, and a 20-bit shift register controlled by a control unit. It performs multiplications by breaking numbers into 4-bit groups, multiplying those groups in parallel, adding the results, and shifting the registers. The deliverables are the control unit state tables, a circuit diagram, a test bench multiplying various cases, and VHDL code/schematics for each component.

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rahulm135
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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THE UNIVERSITY OF WESTERN ONTARIO FACULTY OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING ECE434a: Advanced Digital Systems

Binary Multiplier for Unsigned Numbers


In class a serial-parallel multiplier and an array multiplier was described (section 4.3, pg 124-132 Digital Systems Design Using VHDL). Comparing these two designs reveal the following: The serial-parallel multiplier requires fewer components to implement then the array multiplier. For an N-bit by N-bit multiplier the circuit complexity increases linearly with N for a serial-parallel multiplier, whereas the circuit complexity increases by N2 for array multiplier. An array multiplier is significantly faster than a serial-parallel multiplier. This is due to the fact that many clock cycles are required to manipulate the control unit of the serial-parallel multiplier.

The goal of this assignment is to design 8-bit by 8-bit multiplier for unsigned numbers. The proposed design will encompass the attributes of both the serial-parallel multiplier and the array multiplier. Your design will have the following components: 1. Two array multipliers capable of multiplying two 4-bit numbers (see figure 4.7, pg 131 of textbook). 2. One adder capable of adding two N-bit by N-bit numbers including a carry in. The output of the adder has N-bits for the sum and a carry out bit. Determine the minimum number of N required by the adder for the overall circuit to work. 3. 20-bit shift register. Before starting the multiplication, bits 0 to 7 will be used to hold the multiplier and bits 8 to 15 are used as the accumulator. Bits 16 to 20 can be used to store carry bits. When the multiplication is done bits 0 to 15 will hold the product. This setup is similar to the design in figure 4.3, pg 125 of textbook. 4. Control unit. The control unit outputs appropriate signals to perform multiplication. The multiplication circuit performs the following steps. Consider the following example

step1 step2

BC 23 24 21 234 18 16 19B4

(hex) (hex) (3*12) (3*11)

188 35 6580

(decimal) (decimal) (decimal)

(2*12) (2*11) (hex) = 6580 (decimal

Each step requires 2 multiplications and 2 additions. The multiplications are preformed in parallel using the 2 array multipliers. Next, 2 clock cycle is required to perform the 2 additions. For each addition, the control unit must output appropriate signals so that the results of the adder are stored at the appropriate register location. Additional clock cycles are required to shift the registers by 4 to the right. For the example described the register should contain the following values after each multiply/add and shift command

20 bit shift register


(19-16) (15-12) (11-8) (7-4) (3-0)

load Mult/Add Shift 4 Mult/Add Shift 4


Deliverables

0 2 0 1 0

0 3 2 9 1

0 4 3 B 9

2 2 4 4 B

3 3 2 2 4

Implemented the proposed binary multiplier in using the Altera MAX +plus II software package or Modelsim. Include: State tables or state graphs of the control unit. Circuit diagram Create a test bench that multiplies the following numbers. Case 1: BC (hex) * 23 (hex) Case 2: Let x4 to x1 be the 4 lower digits of your student number. Multiply: x4x3 (hex) * x2x1 (hex). For example if the 4 lower digits of your student number are 4321 then multiply 43 (hex) * 21 (hex) Case 3: FF (hex) * 00 (hex) Case 4: 00 (hex) * FF (hex) Case 5: FF (hex) * FF (hex) Show simulation results. Show VHDL code and/or schematic for each component

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