CS M51A Summer'13 Section 1 Logic Design of Digital Systems: August 1, 2013
CS M51A Summer'13 Section 1 Logic Design of Digital Systems: August 1, 2013
August 1, 2013
3 Su 1
Outline
Administrative Matters Chapter 7:
Spec of Sequential Systems
Summary
CSM51A-Sec.1 Su 13
L11.2
Y. He @ 8/1/13
Administrative Matters
There is no quiz on Friday August 2nd HW #6
Be posted on-line tonight
CSM51A-Sec.1 Su 13
L11.3
Y. He @ 8/1/13
On Off Off On
System
Light
CSM51A-Sec.1 Su 13
L11.4
Y. He @ 8/1/13
Basic Concepts
Synchronous sequential systems Clocks States Finite state machines Mealy and Moore machines
Specification
Time behavior (I/O sequence) State transition table State diagram
Sync. Async.
Minimization Implementation
L11.5 Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
CSM51A-Sec.1 Su 13
L11.6
Y. He @ 8/1/13
Synchronous
Asynchronous
CSM51A-Sec.1 Su 13
L11.7
Y. He @ 8/1/13
Clock
An independent periodic reference signal Provided by
An internal crystal An external 60 Hz alternating current
CSM51A-Sec.1 Su 13
L11.8
Y. He @ 8/1/13
Time-Behavior Specification
Behavior of a sequential system can be specified by a sequence of input(s)/output(s) pairs with respect to the clock signal
Time t Input xi(t) Output zi(t) 0 1 2 ...
CSM51A-Sec.1 Su 13
L11.9
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.10
Y. He @ 8/1/13
State
Introduced to help memorize the complete input/output sequences Usually number of states are finite Itself is also a time function Two types of states are defined:
present state (PS): s(t) next state (NS): s(t+1)
CSM51A-Sec.1 Su 13
L11.11
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.12
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.13
Y. He @ 8/1/13
PS
Inputs x(t)
CSM51A-Sec.1 Su 13
L11.14
Y. He @ 8/1/13
State Diagram
A graphical specification of a sequential system
CSM51A-Sec.1 Su 13
L11.16
Y. He @ 8/1/13
b/1
CSM51A-Sec.1 Su 13 L11.17 Y. He @ 8/1/13
Moore Machine:
Its output depends only upon present state
inputs
logic for
outputs combinational logic for next state
outputs inputs
reg
reg
outputs
state feedback
state feedback
Mealy Machine
Moore Machine
CSM51A-Sec.1 Su 13
L11.18
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.19
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.20
Y. He @ 8/1/13
Example:
A sequential system that counts the occurrence of 55 different events. When the count of event I is a multiple of 100, the output is z(t) = i, otherwise, z(t) = 0 Input: x(t) {1, 2, , 55} Output: z(t) {0, 1, 2, , 55} State: s(t) = (s55,,s1), si {0,1,,99} State: s(0) = (0,0,,0) Functions:
* Transition function: si(t+1) = * Output function:
CSM51A-Sec.1 Su 13
z(t) =
L11.21
Example 7.12:
z(t) =
p q if x(t-3,t) = aaba otherwise
All finite-memory machines are FSMs Not all FSMs are finite-memory
z(t) =
1 0 if number of 1 s in x(0, t) is even otherwise
CSM51A-Sec.1 Su 13
L11.22
Y. He @ 8/1/13
Example:
Input: x(t) {0,1} Output: z(t) {0,1} 1 Function: z(t) =
0 if x(t-3,t) = 1101 otherwise
CSM51A-Sec.1 Su 13
L11.23
Y. He @ 8/1/13
Note:
a note letter a note letter followed by an accidental sign a note letter followed by a digit a note letter followed by an accidental sign followed by a digit
CSM51A-Sec.1 Su 13
L11.24
Y. He @ 8/1/13
Non-autonomous
* The transition is decided by external inputs
CSM51A-Sec.1 Su 13
L11.25
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.26
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.27
Y. He @ 8/1/13
State Minimization
Motivation:
High-level design may generate many redundant states Fewer states may mean fewer state variables To reduce the complexity and cost
Basic concept:
Two states are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same
* (1) Output must be the same in both states * (2) Must transition to equivalent states for all input combinations
Basic Methods:
Table matching Implication Chart
CSM51A-Sec.1 Su 13 L11.28 Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.30
Y. He @ 8/1/13
Column Matching:
CSM51A-Sec.1 Su 13
L11.31
Y. He @ 8/1/13
Column Matching:
Row Matching:
P3 = (A, C) (E) (B, D) (F)
Column Matching:
CSM51A-Sec.1 Su 13
L11.32
Y. He @ 8/1/13
CSM51A-Sec.1 Su 13
L11.33
Y. He @ 8/1/13
Summary
Specification of sequential systems
time-behavior state-transition table equation state diagram
CSM51A-Sec.1 Su 13
L11.34
Y. He @ 8/1/13
Next Lecture
Chapter 8: Sections 8.1-8.7
CSM51A-Sec.1 Su 13
L11.35
Y. He @ 8/1/13