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    V HDL Tutorial

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    Salah-Eddine Nasmi
    The document introduces VHDL, a hardware description language used to program circuits using code rather than schematics. It describes the structure of a VHDL file, including the entity declaration and architecture body. It also covers VHDL syntax, such as statements ending with semicolons and logic operators like and, or, and not. Finally, it provides steps for writing a VHDL module, including defining inputs/outputs, writing the architecture, checking syntax, and creating a test bench waveform.

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    V HDL Tutorial

    Uploaded by

    Salah-Eddine Nasmi
    64 views4 pages
    The document introduces VHDL, a hardware description language used to program circuits using code rather than schematics. It describes the structure of a VHDL file, including the entity declaration and architecture body. It also covers VHDL syntax, such as statements ending with semicolons and logic operators like and, or, and not. Finally, it provides steps for writing a VHDL module, including defining inputs/outputs, writing the architecture, checking syntax, and creating a test bench waveform.

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    The document introduces VHDL, a hardware description language used to program circuits using code rather than schematics. It describes the structure of a VHDL file, including the entity declaration and architecture body. It also covers VHDL syntax, such as statements ending with semicolons and logic operators like and, or, and not. Finally, it provides steps for writing a VHDL module, including defining inputs/outputs, writing the architecture, checking syntax, and creating a test bench waveform.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    64 views4 pages

    V HDL Tutorial

    Uploaded by

    Salah-Eddine Nasmi
    The document introduces VHDL, a hardware description language used to program circuits using code rather than schematics. It describes the structure of a VHDL file, including the entity declaration and architecture body. It also covers VHDL syntax, such as statements ending with semicolons and logic operators like and, or, and not. Finally, it provides steps for writing a VHDL module, including defining inputs/outputs, writing the architecture, checking syntax, and creating a test bench waveform.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    of 4

    University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory

    VHDL Tutorial
    Introduction
    VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. It provides a way of programming a circuit using code rather than schematics. VHDL is one type of hardware description language (HDL). Verilog is another HDL, and is the language used in CIS371. In later labs, we will explore the many features and capabilities of this powerful tool. For now, we will introduce you to the very basics of the language and how it can greatly simplify the representation of a circuit.

    Structure of a VHDL File The Entity


    A digital system in VHDL consists of a design entity which can contain other entities. Each entity is modeled by an entity declaration and an architecture body. The declaration appears in the following form: entity NAME_OF_ENTITY is Port ( signal_name1 : mode type; signal_name2 : mode type; : signal_name2: mode type; end NAME_OF_ENTITY ; As you will soon see, Xilinx helps generate the above code based on the input and output signals you provide.

    Architecture
    The architecture body specifies how the circuit operates and how it is implemented. For a simple circuit such as the half adder, all of your actual coding can go here. It appears as follows: architecture architecture_name of NAME_OF_ENTITY is begin your statements here : end architecture_name

    Updated January 14, 2012

    Syntax
    VHDL is similar to other programming languages in its syntax. For example, statements must end in a semi-colon (;). Also, with the assignment operation, the value of the argument to the right gets stored in the variable on the left as follows: Assignment: signalout <= signalin; For the above statement to be true, both signalin and signalout must be defined earlier. Similar to binary operators in other languages (i.e. +, -, *), VHDL statements use particular keywords for logic gates to function as binary logic operators. Some Logic Operators: and, or, not, xor One point worth mentioning is the use of parentheses, which can be used to clarify an assignment as well as specify grouping. Incorrect (or lack of) use may change a statements meaning altogether. Parentheses: C <= (not A) and B; is not the same as C <= not (A and B); One last note to make is the use of comments. In VHDL, when a double dash ( -- ) is used, any text to the right will be treated as a comment and will not be interpreted by the compiler. Comments are useful in explaining code. Comments: C <= not A
    -- this is a comment

    With these tools in hand, you should be able to code the adders designed in this lab. The guide below will explain the process, while walking you through a trivial case.

    Updated January 14, 2012

    Procedure
    1. To begin, right-click on your project in the Sources window, and select New Source.

    2. Choose VHDL Module and give it a new name. Click Next.

    3. On the next screen, you define the modules. For Port name you will enter the name for an input or output signal, one on each line. Under Direction specify whether it is input or output. Architecture Name should be Behavioral. The rest of the other entries should remain empty. When you are done, click Next.

    4. The next and last screen should provide a summary of your module. If you are satisfied, click Finish. 5. Xilinx should automatically generate most of the VHDL code necessary for your module to run. You will see many commented lines as well as use and library statements. Ignore these for now.

    Updated January 14, 2012

    6. Now you must write lines of code to describe the architecture properly. Using the syntax described earlier and the definition for your outputs, you should be able to define the outputs in terms of the inputs.

    7. Select the Processes window to the left (if you see the Hierarchy window, you will need to click the left tab). Double-click Check syntax to verify that you have coded correctly. If there are any errors, they will be shown in the bottom window.

    8. To test the operation of your module, create a new source within your project and select Test Bench WaveForm (similar to testing schematics). This time, however, you must associate the VHDL module with the waveform. Repeat the process as before to assign input waveforms and generate the output waveforms.

    Updated January 14, 2012

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