CDC

Clock Domain Crossing
Presented by Abramov B.
Register Transfer Logic

Logic
Transfer
R E G I S T E R R E G I S T E R
Logic
RTL (cont)
An RTL circuit is a digital circuit composed of:
(R) registers of FFs responding to the edge of a clock signal
(T) Transfer of wires are the connecting elements
(L) Combinatorial Logic gates.
RTL (cont)
A logic path in RTL circuit is a set of transfer and logic elements connected to each other. A logic path starts at the registers Q output and ends at the registers D input.
RTL (cont)
Clock Domain in a RTL circuit such that: Registers =>R The clock signal is the same clock signal as for all other Registers.
Transfers =>T is part of a Logic path that starts and ends at Registers.
Logics => L is agate in a Logic path that starts and ends at RRs.
RTL (cont)
Clock Speed is limited by the flip-flop delay (clock to output), combinational delay, and setup time.
Bridge path
Bridge path : A bridge path in an RTL circuit is a logic path that starts at registers Q outputs of one clock domain and ends at registers D inputs of the second clock domain. Bridge Path rule: Bridge path must be sampled with a register clocked by the target domains clock.
Clock Skew
Clock Skew : is the difference measured in time between the clock edge (rising or falling edge) of two FFs. Data Delay : is a difference measured in time between the beginning and end of a logic path. Clock domain Rule :
CLOCK SKEW << DATA DELAY

Critical in shift registers, counters and combinatorial systems.
Clock Tree Example H-Tree

Most of VLSI circuit signal propagation delay is caused by the wiring
Same distance from clock source to all Xs
CLK X X X X X X X X
Chip X X X X X X X X
9
Meta-Stability
What are the cases in which meta-stability occurs? When the input signal is an asynchronous signal. When the clock skew/slew is too much (rise and fall time are more than the tolerable values). When interfacing two domains operating at two different frequencies or at the same frequency but with different phase. When the combinational delay is such that flip-flop data input changes in the critical window (setup + hold window) Digital components recover from meta-stable states quickly but the end value is indeterminate
Presented by Abramov B. 10
Meta-Stability
11
Meta-Stability
No other connection to these points
Asynchronous Input
SET
Q Q
SET
Q Q
Edge detection can be placed at this point
Clock
CLR
CLR
Reset from clock tree
12
Meta-Stability
13
Meta-Stability
MTBF Mean Time Between Failures
e MTBF = f clk f dat C1

c2tMET
fclk = Clock frequency fdat =The average frequency of asynchronous data changes tMET = Time allowed for the FF to settle in a stable state C1 = probability of meta-stability catching setup/hold time window C2 =Technology dependent. Describes the speed with which the meta-stable condition is being resolved
CDC failure
Difficulties causes when interfacing two or more asynchronous clock domains
Synchronization failure nUn-reliable data transfers NTransaction never happen NTransaction Happen too many times NTransaction delivered wrong data
n
15
CDC Feedback
Although synchronizing a feedback signal is a very safe technique to acknowledge that the first control signal was recognized and sampled into the new clock domain, there is considerable delay associated with synchronizing control signals in both directions before releasing the control signal.
16
CDC - Edge detection
Clk Sig_in Sig_in events changes for a long time period. Our aim is to detect moment of change (either rise-detect or fail-detect) and to create one-clock length signal that will advice about sig_in changes. Use this one-cycle edge detection output to control data capture and other necessary functions avoids multiple samples or counts per clock/data input pair
17
CDC - Edge detection (cont)

Edge detect only performed after 2nd Meta DFF
0
Signal from other clock domain
SET
Q Q
SET
Q Q
SET
Q Q
CLR
CLR
CLR
Reset from clock tree
Clock
18
CDC - Edge detection (cont)
19
Synchronizing Fast Signals Into Slow Clock Domains (Fast 2 Slow)
20
Fast 2 Slow
One potential solution to this problem is to assert control signals for a period of time that exceeds the cycle time of the sampling clock. The assumption is that the control signal will be sampled at least once and possibly twice by the receiver clock.
21
Fast 2 Slow
D Comb Logic en srst D D
Fast clock side ==N
srst Counter en Slow clock side
N > Tslow Tfast

Fast 2 Slow
A second possible solution to this problem is pulse extracting (stretch)
23
Fast 2 Slow
Lengthened pulse to guarantee that the control signal will be sampled
24
Fast 2 Slow
Using acknowledge feedback flag
Clock domain A Clock domain B Parallel data bus Flag
Disadvantages: Global reset is not used
1 Clock A - fast req
SET
SET
1 Clock B - slow ack
Asynchronous solution Uncertainty in timing constrain boundaries
en
CLR
CLR
en
25
Fast 2 Slow
Better than previous solution, but still asynchronous
26
Fast 2 Slow
The synchronous decision of a transfers of single pulses between two clock domains problem applicable as well as in FPGA and in ASIC is below resulted completely:
Clock A domain - fast One-shot pulse Comb logic T
Clock B domain - slow
27
Two simultaneously required control signals

A register in the new clock domain requires both a load signal and an enable signal in order to load a data value into the register. If both the load and enable signals are being sent from one clock domain, there is a chance that a small skew between the control signals could cause the two signals to be synchronized into different clock cycles within the new clock domain.
28
29

Solution - Consolidating control signals before passing them between clock domains
30
31
Two phase-shifted sequencing control signals
32
33

The solution to the problem is to send only one control signal into the new clock domain and generate the second phaseshifted sequential control signal within the new clock domain.
34
Control Buses synchronizing between clock domains
35
One-Hot Checker
Q: How to check the one-hot code ? A: Use dual-rail code! The dual-rail code for 4 bit example:
Y1 , Y2 , Y3 , Y4 - the outputs from second register of receive

r1 = y3 + y4 + y1 y2
clock domain, in which coded by one-hot code.
r0 = y1 + y 2 + y 3 y 4
The result of checking XOR between outputs of these symmetric functions. The dual-rail checker should be simply cascaded for any width of checked word.
36
One-Hot Checker
8 bit One-hot code checker architecture
37
Control Buses synchronizing between clock domains

Clock domain crossing with data XOR de-correlator/correlator
ACLOCK Domain BCLOCK Domain
EC
2n
XOR REG
2n
REG REG
2n
XOR
DC
REG
REG
38

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Clock Domain Crossing

Register Transfer Logic

(R) registers of FFs responding to the edge of a clock signal

(T) Transfer of wires are the connecting elements

(L) Combinatorial Logic gates.

CLOCK SKEW << DATA DELAY

Clock Tree Example H-Tree

Reset from clock tree

e MTBF = f clk f dat C1

CDC - Edge detection

CDC - Edge detection (cont)

Reset from clock tree

CDC - Edge detection (cont)

Synchronizing Fast Signals Into Slow Clock Domains (Fast 2 Slow)

Fast clock side ==N

srst Counter en Slow clock side

N > Tslow Tfast

Disadvantages: Global reset is not used

1 Clock A - fast req

1 Clock B - slow ack

Asynchronous solution Uncertainty in timing constrain boundaries

Clock A domain - fast One-shot pulse Comb logic T

Clock B domain - slow

Two simultaneously required control signals

Two simultaneously required control signals

Two simultaneously required control signals

Two simultaneously required control signals

Two phase-shifted sequencing control signals

Two phase-shifted sequencing control signals

Two phase-shifted sequencing control signals

Control Buses synchronizing between clock domains

Y1 , Y2 , Y3 , Y4 - the outputs from second register of receive

clock domain, in which coded by one-hot code.

Control Buses synchronizing between clock domains

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