Preliminary: SPCA702A

Preliminary SPCA702A
VCD DECODER
GENERAL DESCRIPTION
The SPCA702A VCD decoder is designed to maximize system performance and minimize cost. The standard
configuration requires only a 256K x 16 DRAM, a ROM, a VCD-AV interface IC and a CD-kit to build a complete
VCD player. An enhancement mode extends external DRAM from 4Mbits to 8Mbits (extendable to 16Mbits if
package uses a 160 pin QFP).
The SPCA702A integrates functions needed for a VCD system, such as Stereo Key controller for Karaoke, Audio
wide sound and Digital audio decoder. And in order to make the VCD system more sophisticated, the
SPCA702A also includes a flexible programmable interface. Through the interface, not only can the
microprocessor in a VCD player be neglected, but it also allows the VCD player to be programmed for numerous
applications.
The SPCA702A is designed as a glueless connection for traditional TV encoder and audio DAC. In order to
further reduce costs, it can also be directly interfaced with CD-DSP IC, AV interface IC, and echo generator.
Designed to fulfill VCD requirements, the SPCA702A includes, not only the latest technology, but also the full
service and support of Sunplus.
A common implementation utilizing the SPCA702A is presented below:
DRAM ROM
CD-DSP TV Encoder TV
SPCA702A
up(optional)
Stereo
Audio DAC
Audio
Front Function
Panel Keys
Figure 1-1 VCD System Block Diagram
Sunplus Technology Co., Ltd. 1 Rev.: 0.1 2000.10.05

Preliminary
SPCA702A
FEATURES
✝General features ✝Built-in Programmable Karaoke processor with
─ Only requires one 256K x 16 DRAM ─ Key control for MPEG audio layer1, layer2 and
─ 14K bytes free space for user usage and OSD layer3
─ Glueless interface to CD-DSP, DRAM, ROM, ─ Programmable wide sound
Audio DAC and TV encoder ✝Built-in PLLs generating system and audio clocks
✝Real time video decompression ✝Programmable serial bitstream CD interface
─ MPEG1 video decoder conforming to ISO-11172 ✝Supports parallel mode Host control Interface
─ Programmable hybrid video error concealment ✝Low voltage detection circuit to prevent power
✝Real time audio decompression instability
1)
─ MPEG audio layer 1, 2 and 3 decompression ✝Software Drivers
conforming to ISO-11172 standard ─ Drivers for CD-I (green book, white book),
─ Automatic audio error concealment Karaoke CD, Video CD 2.0/1.1 and Audio CD
─ Digital volume control (CD-DA)
✝Real time system layer decompression conforming ─ Preview
to ISO-11172 standard ─ User definable features
✝Advanced video processing and display ─ RISC game software
─ Supports NTSC and PAL TV standards ─ ZoomPro: Programmable video Zoom-in/out
─ Performs vertical scaling to allow NTSC/PAL ─ ImagePro: Programmable digital image
source to be displayed on PAL/NTSC TV in processing
correct aspect ratio ✝Versatile programmable interface
─ Performs real-time processing at 720x480x30 ─ Support system controller emulation
fps, 720x240x60 fps, 720x576x25 fps or ─ Programmable serial I/O interface for IR in/out,
720x288x50 fps CD-kit (DSA or CD-DSP IC) control and VFD
─ Horizontal and Vertical Interpolation for high control etc.
quality video output ─ Accept digital audio PCM format input
─ Video fade-in/fade-out
✝Component features
─ Supply voltage : 3.0 volts to 3.6 volts
─ I/O interface : 5 volts tolerance
─ Package : 128-pin QFP
License Notice:
Supply of this implementation of MPEG audio layer 3 technology does not convey a license nor imply any right to use this
implementation in any finished end-user or ready-to-use final product. An independent license for such use is required.
For more information contact: [email protected].

Preliminary
SPCA702A
DRAM Video
Interface Interface
Programmable
I/O Interafce
CD Interafce MPEG1
Video Decoder
Host Interafce
PCM
Interface
KaraOk&
RISC
Sound Effect
Processor
Processor
Clock MPEG1
Generator Audio Decoder

SPCA702A
Preliminary
SPCA702A
✝CD INTERFACE SIGNALS

CD_DATA CD serial data Input
This pin is input for serial data from CD-DSP.
CD_LRCK CD left/right clock Input
CD_LRCK provides 16-bit word synchronization to the
SPCA702A and has several programmable features,
such as polarity, delay and pulse mode.
CD_BCK CD bit clock Input

Preliminary
SPCA702A
ROM/GIO INTERFACE SIGNALS DSA_ACK Ack signal Bidirectional
ROM_DATA(7:0) ROM data bus Input Ack signal for DSA interface
Generic 8-bit parallel ROM data bus. DSA_DATA Data signal Bidirectional
ROM_ADDR(17:0) ROM address bus Output Data signal for DSA interface.
Generic ROM address bus. DSA_STB Strobe signal Bidirectional
VFD_DATA data signal Bidirectional Strobe signal for DSA interface.
Data signal for VFD. IR_IN IR input Input
VFD_CLK clock signal Output IR input pin. This input supports both NEC and Philips
Clock signal for VFD. format IR signal.
VFD_STB strobe signal Output IR_OUT IR output pin Output
Strobe signal for VFD. IR output pin.
SYSTEM SYNC
SOME ABBREVIATIONS FOR SYSTEM SYNC MODULE
STC - System Time Clock
SCR - System Clock Reference
DTS - Decode Time Stamp
PTS - Presentation Time Stamp
STD - System Target Decoder (ideal decoder)
PU - Presentation Unit
AU - Access Unit
DSM - Digital Storage Medium
Fs - Sampling Frequency
TIMERS AND TIME STAMPS

─ System Time Clock (STC)

Preliminary
SPCA702A
─ Decode Time Stamp (DTS)

The Decode Time Stamp value represents the time when an access unit should be ready for decoding.
For the Audio stream, the DTS == PTS so it is not used. In the Video stream, the DTS for I-Frames and
P-Frames are nominally equal to the PTS value minus the number of picture periods of video reordering
delay multiplied by the picture period, in units of the 90KHz STC.
─ Presentation Time Stamp (PTS)

A Presentation Time Stamp represents the time at which a presentation unit should be displayed. In the
case of Audio, this is the time when the decoder should begin the playback of an audio frame. In the
case of Video, this is the time when the corresponding video frame should be displayed.
TIME MASTER
A decoding system, including all of the synchronized decoders and the source of the coded data, must have
exactly one independent time master. The SPCA702A chip allows the microcode to use either the DSM or
Audio block as the time master. The time master selection depends on how the STC is updated.
─ DSM as Time Master

To use the Digital Storage Medium, in this case the Video CD reader, as the time master, follow the
synchronization guidelines given below:
1) Initialize the STC to the first SCR received.
2) Set the STC to run (incrementing at 90kHz).
3) Maintain the STC by updating it with SCR values received.
4) Video presentations are made when the video PTS==STC.
5) Audio presentations are made when the audio PTS==STC.
─ Audio as Time Master

To use the Audio block as the time master, follow the synchronization guidelines given below:
1) Initialize the STC to the first SCR received.
2) Set the STC to run (incrementing at 90kHz)
3) Maintain the STC by updating it with Audio PTS values received.
4) Video presentations are made when the video PTS==STC.
5) Use SRC values to determine if the DSM data rate is correct.

Preliminary
SPCA702A
VIDEO DECODER
The Video Decoder is an MPEG 1 video decoder optimized for minimum size while conforming to ISO 11172
standard. The module will read an MPEG 1 video stream in and continuously generate frames in external
DRAM. The frames will then be processed by a video processor for final display. The Video Decoder performs
the following functions:
1) Huffman Decoding
2) Dequantization
3) Inverse Cosine Transform
4) Motion Vector Generator
5) Address Generator
6) Motion Compensation
VIDEO PROCESSOR
The Video Processor & Output Interface is responsible for taking decompressed data from memory (DRAM), and
process the data into raster (interlaced or non-interlaced) video. Some of the important processing functions
include horizontal/vertical interpolation, filtering and clipping.
The video processing functions performed by the video processor include vertical interpolation, horizontal
interpolation, horizontal filtering, proprietary high-resolution functions and clipping functions. Video
interpolations allow for small SIF images of MPEG video decoding to be enlarged without blocking or
discontinuity effects. The final display of the SIF image will have smooth transitions in both horizontal and
vertical directions. Horizontal filtering will also be performed to reduce any aliasing effects. The proprietary

Preliminary
SPCA702A
VIDEO PROCESSOR INTERFACE

The I/O interface to the video processor is defined below:
HSYNC_IN Horizontal sync Input
Horizontal sync signal input from TV encoder.
VSYNC_IN Vertical sync Input
Vertical sync signal input from TV encoder.
DATA_TV(7:0) Video out Output
These pins form the video data output bus. It contains multiplexed Luminance and Chrominance video data.
PAL_NTSC PAL/NTSC control Output
This pin control the PAL/NTSC mode of TV encoder.
CLK27OUT 27 MHz clock Output
27 MHz video pixel clock output to the TV encoder signal.
The recommended interface scheme is shown in Figure 5-1 below:
SPCA702A PAL_NTSC
CLK27OUT
8
DATA_TV
TV
Encoder
VSYNC_IN
HSYNC_IN
Figure 5-2 Video Processor Interface
USAGE FOR 8 BIT VIDEO INTERFACE

SPCA702 co-operates with master-mode TV-encoders. VSYNC_IN and HSYNC_IN signals come from a
standard TV-encoder(as in figure 5-2.) SPCA702 will lock to these reference timing and put the data onto the
DATA_TV[7:0]. Data on the DATA_TV[7:0] is multiplexed data of 4_1_1 format. The data is sequenced out
(Cb0,Y0,Cr0,Y1,Cb2,Y2,Cr2,Y3..) after HSYNC_IN. Detailed timing diagram of TV encoder interface is
presented in Figure 5-3 below:
CLK27OUT
HSYNC_IN
DATA_TV(7:0) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11
Figure 5-3 8 bit Video Interface Timing

Preliminary
SPCA702A
ON SCREEN DISPLAY
The on screen display feature is intended to display a rectangular area which can be a graphic or text overlay the
decoded video on the screen. There are flexible numbers of rectangular regions that can be in a field and each
region consists of a region header and data. Host or RISC will program these headers and data then store to
the DRAM for various application purpose. OSD decoder reads the header and data, then interpreted as
graphic data and overlaid with video 3.2(o)(e)-0S purpose.d data, pur 8dec4105 Tithvideo am t6video 3. c ists01279-8.4

Preliminary
SPCA702A
COLOR TABLE UPDATE

If this bit is active, there will be a color look up table following the header. The luminance part, Y, is represented
by 6 bit and the chrominance part, Cb and Cr, are represented by 4 bit for each. The bitmapped data following
the OSD header are 2 bits per pixel.
BLEND LEVEL
This parameter gives the ratio of OSD that will mix with the corresponding video data to be displayed on the
screen.
AUDIO DECODER
The Audio Decoder will process all computation intensive functions for the MPEG 1 Layer1, Layer 2 and Layer3
decompression tasks. However, Layer3 can not be decoded when the video decoding function is in progress.
Layer1 and Layer2 can be smoothly decoded when the video decoding function is enabled. RISC and Audio
Decoder cooperate in the audio decoding procedure. Front-end decoding functions, which have low
computational requirements, are handled by the RISC processor. The Re-quantization and Synthesis Subband
Filter functions are the most computationally intensive portions of audio decompression and are processed by
the Audio Decoder. After audio data has been decompressed, the resulting PCM data is stored in DRAM for
final output by the Audio Output Interface Module.
AUDIO OUTPUT INTERFACE

The Audio Output Interface takes PCM data from memory (DRAM) and outputs it in bit-serial format to external
audio DACs. The PCM audio data will be in alternating left/right channel format if the data is in stereo mode.
In mono mode, the data will be a list of PCM values.
AUDIO OUTPUT INTERFACE SIGNALS

The signals from the Audio Output Interface are as follows:
AUD_DATA Audio data bus Output
Serial audio data clocked out relative to AUD_BCK.
AUD_LRCK Audio Left/Right clock Output
Left/Right data channel indicator.
AUD_BCK Audio bit clock Output
Audio bit clock output. Depending on audio output mode, this signal can be derived from the master clock or
be AUD_XCK divided by 8. It can be either 48 or 32 times the sampling clock.
AUD_XCK External audio clock Input
When the SPCA702A is programmed for external audio clock mode, the audio clock will come from this signal.
When programmed for internal audio clock, this signal will reflect the internal audio clock.
AUD_EMP Emphasis Control Output

Preliminary
SPCA702A
This signal is used to control the de-emphasis circuitry of the audio output DACs. In CD-DA pass-through
mode, this output follows the state of the CD_EMP signal; when in VCD mode, this pin follows the LSB of the
emphasis field of the MPEG-1 audio header.
A typical connection scheme is shown in Figure 8-1 below:
AUD_XCK
SPCA702A AUD_DATA
AUD_LRCK Audio
AUD_BCK DAC
AUD_EMP
Figure 8-1 Audio Output Interface
A timing diagrams of the audio interface clocking modes are presented in Figure 8-2 below.
AUD_BCK
AUD_LRCK
AUD_DATA 0 15 14 1 0 15 14 1 0 15
BCK = 32 x Fs
AUD_BCK
AUD_LRCK
AUD_DATA 0 15 14 1 0 15 14 1 0 15 14
BCK = 48 x Fs
Figure 8-2 Audio Interface Clocking Modes
RISC PROCESSOR
The RISC processor is used to help decode high level data formats, MPEG system layers, low bandwidth MPEG
audio and video decoding and assorted miscellaneous functions. If the SPCA702A were used in a low cost
system with simple user interfaces, additional savings can be accomplished by using the RISC core to perform
host micro-controller functions; thereby dropping the micro-controller from the bill-of-materials.

Preliminary
SPCA702A
DRAM INTERFACE
The DRAM interface is used by the SPCA702A to access DRAM for all required functions in the system including
bit stream store after parsing, reading bit stream into the VLD, reference macroblock read and motion
compensated macroblock write, display data read for display interface, OSD data store and read, and so on.

Preliminary
SPCA702A
DRAM MAMORY MAP

Figure 10-4 shows the DRAM memory map of the SPCA702A. The memory is partitioned into several regions.
These regions are:
1) Software Usage
2) Audio Work Buffer
3) OSD buffer
4) CD buffer
5) Video Channel Buffer
6) Audio Channel Buffer
7) Reference Frame0 of Luminance
8) Reference Frame0 of Chrominance
9) Reference Frame1 of Luminance
10) Reference Frame1 of Chrominance
11) B Frame of Luminance
12) B Frame of Chrominace
A programmable pointer points to each region. RISC can change the content of any pointer via register file.

Preliminary
SPCA702A
Software usage
Audio work buffer
OSD
CD
Video Channel Buffer
Audio Channel Buffer

REF0_LUMA
Reference Frame 0 - (Luma)
REF0_CHROMA
Reference Frame 0 - (Chroma)
Reference Frame 1 - (Luma)
REF1_CHROMA
Reference Frame 1 - (Chroma)
BIDIR_LUMA
BF - (Luma)
BIDIR_CHROMA
BF - (Chroma)

Preliminary
SPCA702A
CD INTERFACE
The CD interface is a simple serial interface for standard CD-DSPs. Serial data from the CD-DSP is shifted into
the SPCA702A, preprocessed by the CD interface module, then written to DRAM for post-processing by the
RISC processor. Since post-processing is accomplished by the RISC processor, the data stream can be in any
format. For example CD-DA, CD-ROM, CD-ROM/XA, CD-I, MPEG1 system streams, MPEG1 video streams
and MPEG1 audio streams. Note that for the CD-DA format, since no post-processing is necessary, the serial
data can be routed directly to the audio DACs.
The RISC processor and dedicated hardware is responsible for the following CD data stream post-processing
functions when the data format is not CD-DA :
─ Real-time parsing for Mode 2 form 2 sectors.
─ Real-time parsing for Mode 1 and Mode 2 form 1 (e )12u6.1(oc)10.3(r)-6.5 ((e )12u4.1 Tf9.96 0 D )]TJ/M(e -13.y96

Preliminary
SPCA702A
Table 11-1: BCK/Data rate/ LRCK relationships

BCK CD Speed Data Rate BCK per LRCK
1.42 MHz Normal 1.42 Mbits/sec 32

2.84 MHz Double 2.84 Mbits/sec 32
Table 11-2: CD Input Format

Mode # of BCK Data MSB/LSB first LRCK left/right polarity Data latch timing
1 32 MSB Right 1
2 32 MSB Left 0
3 24 MSB Right 1
4 24 LSB Right 0
5 24 MSB Right 1
6 16 MSB Left 1

Preliminary
SPCA702A
Functional timing diagrams of the above six formats are detailed below:
CD-BCK
CD_LRCK Left Channel Right Channel

MSB LSB MSB LSB
CD_DATA 0 Invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Invalid

Preliminary
SPCA702A
Some common CD Sector Formats are presented below :
CD-DA Sector : 2352 Bytes
User Data
CD-ROM Sector : 2352 Bytes

Mode0 Sync User Data
Header
Mode2 12 2336
Min Sec Frame Mode
1 1 1 1
Scrambled
CD-ROM Sector : 2352 Bytes

Mode1 User Data
Sync Header EDC Space ECC
12 2048 4 8
Min Sec Frame Mode P-parity Q-parity
1 1 1 1 172 104
Scrambled
CD-ROM/XA Sector : 2352 Bytes

CD-I Mode 2
Sync User Data EDC ECC
Mode2-Form1 12
Header
2048 4
Min Sec Frame Mode FN CNSM CI FN CNSM CI P-parity Q-parity
1 1 1 1 1 1 1 1 1 1 1 1 172 104
Scrambled
CD-ROM/XA Sector : 2352 Bytes

CD-I Mode 2 User Data
Sync EDC
Mode2-Form2 12
Header
2324 4
Min Sec Frame Mode FN CNSM CI FN CNSM CI
1 1 1 1 1 1 1 1 1 1 1 1
Scrambled
Figure 11-2 Some Common CD Sector Formats

SPCA702A
Sunplus Technology Co., Ltd. Rev.: 0.1 2000.10.05

Preliminary
SPCA702A
IR INPUT/OUTPUT
There are two commonly used IR format, i.e., NEC and PHILIPS. The timing diagramming are listed below.
These timing diagrams are extracted from the HT6221 / HOLTEK and SA3010 / PHILIPS. For the NEC format,
two instruction commands are defined. One is normal command and the other is repeat command. The
normal command consists of pre-emble, address and data field. The parameters that ar thatr16.and dat234cr thnd dat

Preliminary
SPCA702A
IR INPUT
Register Name Reg Bits Description RW RST
Initial polarity of signal

[0] 0: negative
1: positive (normal)
Waveform type
IR_MISC 160 [1] 0: PHILIP format W 16’h001F
1: NEC format
Bit polarity
[2] 0: waveform of 1 and 0 is reversed
1: waveform of 0/1 is as WAVEFM registers
[7:0] wavfm_a
IR_WAVFM_AIS 161 W 16’h0D1A
[15:0] wavfm_a_i_sub
[7:0] Preamble C (NEC)
IR_PRE_CD_NEC 162 W 16’h366C
[15:8] Preamble D (NEC)
[7:0] RPT_E: NEC type repeat word
IR_RPT_EF_NEC 163 W 16’h1E6C
[15:8] RPT_F: NEC type repeat word
[7:0] RPT_G: NEC
IR_PRE_RPT_NEC 164 W 16’h1806
[15:8] wavfm_pre_rpt_sub
[2:0] PRE_NO: number of start and control bits.
[5:3] CNL_NO: number of control bits
IR_PRE_PHILIPS 165 RPT_TYPE: W 16’h0042
[6] 0: no repeat-word
1: with repeat-word
[7:0] STRT_PATT: start bit-pattern.
IR_PRE_PATT_PHILIPS 166 W 16’h0607
[15:8] CNT_PATT: control bit-pattern
GRD_ADDR (NEC)
[0] 0: no guard band between address and data
1: guard band between address and data
IR_GUARD 167 GRD_DATA (NEC) W 16’h0000
[1] 0: no guard band between data and data
1: guard band between data and data
[15:8] duration of guard band between data and data
IR_ADDR_PATT 169 8 Address patterns W 16’hAA55
IR_DATA_RECV 170 [3:0] Preamble received R
IR_CLK 172 W 16’d404

Preliminary
SPCA702A
[3:0] # of address bits

[7:4] # of data bits
IR_ADDR_DATA_CONFIG 168 [9:8] # of data repetition W 16’h057F
POL_TOGGLE_DATA: toggle bit-polarity
[10]
between data
[0] RX_OK: receive ok
IR_STATUS 171 R
[1] RPT_FLAG: receive repeat word
The register programming value for these two type are in the table.
Register NEC PHILIPS
MISC 0x001F 0x001D

IR_WAVFM_AIS 0x0D1A 0x0D15
IR_PRE_CD_NEC 0x366C X
IR_RPT_EF_NEC 0x1E6C X
IR_PRE_RPT_NEC 0x1806 X
IR_PRE_PHILIPS 0x002X 0x0002
IR_PRE_PATT_PHILIPS X 0x0007
IR_GUARD 0x0000 0x0000
IR_ADDR_DATA_CONFG 0x057F 0x0054
IR OUTPUT
IROUT_PRE_CD 77
IROUT_RPT_EF 78
IROUT_STRT_G 79
IROUT_DATA_PER 156
IROUT_ADDR 157
IROUT_GUARD 158
IROUT_STATUS 159 read the transmission status of IR out
IROUT_DATA 69 IR data to be transmitted
The IR output is for the control of VCD 1.0 loader. The format must be NEC. There are reset value for all the
programming registers. No action by the user is required.

Preliminary
SPCA702A
HOST INTERFACE
The host interface consist of ten signals which are D7 - D0, and nstrobe / nwrite. The Mpeg chip is master and
the host is slave. Whenever the host wants to access Mpeg, it has to read D0 - D7. At this time, the nstrobe
and nwrite are high. The following table defines the actions that the host can take after read.

Preliminary
SPCA702A
Register Name Reg. Bits Description RW RST

[15-8] Reserved
EPP_DATA 18
[7-0] EPP Data Port rw 0
EPP Interface Control (Bit 14-11) Update
[15] 0: Disable rw 0
1: Enable
EPP Interface Function
1: Enable
Data Input Function
1: Enable
Data Output Function
1: Enable
NWRITE, NSTROBE sync mode
1: Enable
[10-6] Reserved.
Reset Input FIFO
EPP_STATUS 19
[5] 0: Disable w 0
1: Enable
Reset Output FIFO
[4] 0: Disable w 0
1: Enable
Input FIFO Full
[3] 0: No r 0
1: Yes
Input FIFO Empty
[2] 0: No r 1
1: Yes
Output FIFO Full
[1] 0: No r 0
1: Yes
Output FIFO Empty
[0] 0: No r 1
1: Yes

Preliminary
SPCA702A
VFD CONTROL
[15-13] Reserved.
[12-9] VFD Pin Status
Bit 12: CLK 1
Bit 11: STB 1

Preliminary
SPCA702A
Command Type
00: Read
[9-8] 01: Write rw 0
10: Write Form 1
11: Reserved.
[7-5] Data Size in Command Mode rw 0
[4-2] Data Size in Polling Mode rw 0
Command Mode Control
[1] 0: Disable rw 0
1: Enable
Polling Mode Control
[0] 0: Disable rw 0
1: Enable
[15-8] Command 0 rw 0
VFD_CMD 179
[7-0] Command 1 rw 0
[15-8] Data Byte 0 rw 0
VFD_DAT0 180
VFD_DAT1 181
VFD_DAT2 182
VFD_DAT3 183

Preliminary
SPCA702A

Preliminary
SPCA702A
read VFD_DAT0[15:8]
the read data is stored here.
write VFD_FUNC, 0x0000
command mode control: disable
cycle complete
MACRO COMMANDS
For the application of SPCA702, programmers could access and modify most firmware options directly.
However for most VCD playback applications the SPCA702 firmware also provides a generic program interface
for popular functions. The programming interface covers most CDDA, VCD1.0, VCD1.1 and VCD2.0 playback
functions. For example, play a CD track in A/V mode or read a specific CD sector. A generic navigator or
specialized playback path can be built by utilizing the control interface.
The programming interface is consisted of macro commands. Generally they could be classified into 2 groups
of functions, initialization functions and playback functions. An initialization function is to setup the playback
environment ready for playback, and a playback function will execute the playback (or any other specific
operations) request. To achieve most functions, an application should issue an initialization macro command
before it issues the playback command. A generic control flow would look like:
while (task_not_finished)
{
/* issue playback_track macro-command */
PlayTrack(2);
/* execute the playback command until finished */

MediaMainLoop();
/* check result and change program flow */

------
}

Preliminary
SPCA702A
These macro commands are listed below:

Classification Name Description
CONTROL Init() Initialize the system hardware and software interface

Abort() Terminate current playback task
Sync() Wait for last playback finish
Pause() Pause current playback
Freeze() Freeze video playback
Continue() Continue paused/frozen playback
PLAYBACK PlayTrack() Initialize playback of a general track
Initialize playback of a general track using preview
PlayTrackPreview()
(vcd 2.0 only)
Initialize playback from a PSD ENTRY
PlayEntry()
(vcd 2.0 only)
Initialize playback from a PSD SEGMENT
PlaySegment()
(vcd 2.0 only)
PlayMP3() Initialize MP3 playback
PlayRomSlide() Initialize ROM-based video-bistream playback
DisplayPreviewBackground() Initialize preview background
OSD OSD_OnOff() Turn on/off specific OSD regions
SetOsdColor() Set OSD display color
CD
ReadCD() Initialize CD reading operation
OPERATION
ReadCDMSF() Initialize CD reading operation (MSF addressing)
MAIN MediaMainloop() Playback main path

Preliminary
SPCA702A
MACRO
Init()
Parameter
None
Description
Init() will reset system to a known state.
Applicable
Always
MACRO
Abort()
Parameter
None
Description
Abort() will terminate current playback process.
Applicable
Always

Preliminary
SPCA702A
MACRO
Sync()
Category
CONTROL
Parameter
None
Description
Sync() is used to wait until a locked state of system when issue command will be safe.
Applicable
Always
MACRO
Pause()
Category
CONTROL
Parameter
None
Description
Pause() command stops the current program playback. After receive this command the A/V decoder would
stop decoding incoming bitstream. If playing from CD kit, the A/V decoder also issue CDKIT to pause.
Applicable
CDDA, VCD1.0, VCD1.1 and VCD2.0.

Preliminary
SPCA702A
MACRO
Continue()
Category
CONTROL
Parameter
None
Description
Continue() undo the effect of command Pause() and Freeze(). If A/V decoder is not paused nor frozen, this
command has no effect on the system.
Applicable
CDDA, VCD1.0, VCD1.1 and VCD2.0.
MACRO
Freeze()
Category
CONTROL
Parameter
None
Description
Freeze() will instruct the A/V decoder stop video decoding. The overall effect will look like the video program is
frozen and only audio playback carry on.
Applicable
Motion picture sequences within VCD1.0, VCD1.1 and VCD2.0.

Preliminary
SPCA702A
MACRO
Play()
Category
PLAYBACK
Parameter
None
Description
Play() will instruct the VCD A/V decoder to prepare for LINEAR PLAYBACK for a program.
MACRO
PlayTrack(Track)
Category
PLAYBACK
Parameter
Name Type Description
Track BYTE Specified Track number (1-99)
Description
PlayTrack() will instruct the VCD A/V decoder to prepare for a CD track. Track format will be decided from
current CD format and TOC content of this track.
Applicable
CDDA, VCD1.0, VCD1.1, VCD2.0

Preliminary
SPCA702A
MACRO

Preliminary
SPCA702A
MACRO

Preliminary
SPCA702A
MACRO
PlayRomSlide(RomAddr)
Category
PLAYBACK
Parameter
RomAddr UINT32 Specified ROM bitstream address
Description
PlayRomSlide() will instruct the VCD A/V decoder to prepare for video-elementary bistream playback, where
the bitstream comes from ROM embedded pattern.
Applicable
Always
MACRO
DisplayPreviewBackground()
Category
FRAMEBUFFER
Parameter
None
Description
DisplayPreviewBackground() will configure the memory mapping into 9-digest PREVIEW and clear the
background. After this operation
Applicable
Always

Preliminary
SPCA702A
Reference Value
Color Y Cr Cb
White 0xEB 0x80 0x80
Yellow 0xA2 0x8E 0x2C
Cyan 0x83 0x2C 0x9C
Green 0x70 0x3A 0x48
Magenta 0x54 0xC6 0xB8
Red 0x41 0xD4 0x64
Blue 0x23 0x72 0xD4
Black 0x10 0x80 0x80
MACRO
SetOsdColorDirect(region,color,value)
Category
CONTROL
Parameter
region BYTE OSD region selected
0xFF write to all OSD regions.
color BYTE Color index of the specified OSD region
(0-3 for 4-color OSD)
value UINT16 value of color entry
Description
SetOsdColorDirect() will set the color of a specified OSD (On Screen Display) region according to the color
value.

Preliminary
SPCA702A
MACRO
ReadCDMSF(DST,MSF,SKIP,SIZE)
Category
CD OPERATION
Parameter
DST UINT32 Memory address pointer to store the result
MSF UINT32 Packed Red-book MM:SS:FF CDROM address of the
starting sector to be read
SKIP UINT32 Bytes to skip before storing into memory
SIZE UINT32 Bytes to read
Description
ReadCDMSF() will try to read a specified CDROM address into a memory portion. The memory address is
assigned in RISC memory space. After the command issued, the A/V decoder will try to seek to the specified
CDROM position and wait for the starting sector. CDROM data is extracted from CDROM/XA format and store
to the memory position.
Applicable
Any CD format conforms to CDROM (Yellow book) or CDROM/XA.
MACRO
ReadCD(DST,EXT,SKIP,SIZE)
Category
CD OPERATION
Parameter
DST UINT32 Memory address pointer to store the result
EXT UINT32 High-Sierra CDROM address of the starting sector to be read
SKIP UINT32 Bytes to skip before storing into memory
SIZE UINT32 Bytes to read
Description
ReadCD() acts just like ReadCDMSF(). Except that the CDROM address is in High-Sierra CDROM format.
Applicable
see ReadCDMSF()

Preliminary
SPCA702A
ELECTRICAL SPECIFICATIONS
✝OPERATING CONDITIONS
Table 16-1: Absolute Maximum Ratings
Symbol Parameter Rating Units
VCCKP, VCCAP Power Supply -0.3 to 3.6 V

VCC5OP, VCC5IP, VCCTVP Power Supply -0.3 to 6 V
Tstg Storage Temperature -40 to 125 ℃
Tsolder Soldering Temp. (Max. Time) 240 (for 5 Sec. Max.) ℃
Table 16-2: Recommended Operating Conditions

Symbol Parameter Min. Typ. Max. Units
VCCKP, VCCAP Power Supply 3.0 3.3 3.6 V

VCC5OP, VCC5IP, VCCTVP Power Supply 4.75 5.0 5.25
VIN Input Voltage 0 - 5.0 V
TOPR Operating Temperature 0 - 70 ℃
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are
stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the
operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 16-3-1 DC CHARACTERISTICS

Conditions: I/Opower VDD-VSS = 5V, Kernel power VDD-VSS = 3V, VCCTVP=3V, TA = 25℃, MCLK = 27MHz
Limit
Characteristics Symbol Unit Conditions
Min. Typ. Max.
I/O Operating Voltage VDD 4.5 5 5.5 V Kernal Voltage @ 3.34V

Kernel Operating Voltage VDD 2.8 3.0 4.0 V I/O Voltage @ 5V
Operating Current IOP - 280 - mA Kernal = 3V
Input High Level (ROM, CD, Video) VIH 2.2 - - V
Input Low Level (ROM, CD, Video) VIL - - 0.8 V
Output High I
IOH - -8.0 - mA VOH = 4.2V
(Dram, ROM, Audio, Host, Video)
Output Sink I
IOL - 8.0 - mA VOL = 0.8V
(Dram, ROM, Audio, Video)
Output Capacitance COUT - - 10 pF

Preliminary
SPCA702A
Table 16-3-2
Conditions: I/Opower VDD-VSS = 5V, Kernel power VDD-VSS = 3V, VCCTVP = 5V, TA = 25℃, MCLK = 27MHz
Limit
Characteristics Symbol Unit Conditions
Min. Typ. Max.
Input High Level (Video) VIH 2.2 - - V

Input Low Level (Video) VIL - - 0.8 V VOH = 4.2V
Output High I (Video) IOH - -8.0 - mA VOL = 0.8V
Output Sink I (Video) IOL - 8.0 - mA

Preliminary
SPCA702A
AC TIMING CHARACTERISTICS
✝DRAM INTERFACE TIMING DIAGRAM
CLK
t15
t25 t26 t14
RAS_B
t8 t12 t13 t7
t6
CAS_B
t20 t28
t11 t9 t24
t10
t3
DA[11:0] row addr. col. addr. . addr. . a67( a67(4)]TJ-1772 l33(.)-7.7(.)-562.3(.)-7.766.921841-.88 .3(.)-7.766.921841
t16 t17
WE_B
t4 t5
t9
DD[15:0]
t1

Preliminary
SPCA702A
Limit
Time Description Units
Min. Typ. Max.
t19 Col address to CAS_B ligh 30 35 - ns

t20 RAS_B to CAS_B delay 20 55 60 ns
t24 Col address to RAS_B high 40 55 - ns
t25 RAS_B low to CAS_B high 72 75 - ns
t26 RAS_B holg time from CAS_B precharge 48 52 - ns
t28 Read command hold time from CAS_B 0 75 - ns

Preliminary
SPCA702A
✝ROM READ TIMING DIAGRAM
ROM_ADDR[17:0]
t
ROM_DATA[7:0]
✝ROM READ TIMING TABLE
Limit
Min. Typ. Max.
t ROM_DATA ready from ROM_ADDR - 50 75 (350) ns

Preliminary
SPCA702A
✝HOST READ TIMING DIAGRAM
t0 t1
nstrobe
t2 t3
data
t4
nwrite
✝HOST WRITE TIMING DIAGRAM
nstrobe
t5
data
nwrite
✝HOST INTERFACE TIMING TABLE
Limit
Min. Typ. Max.
t0 nstrobe low time 20 - - ns

t1 nstrobe high time 10 - - ns
t2 data setup time 43 - - ns
t3 data hold time from nstrobe 48 - - ns
t4 nwrite delay from nstrobe 88 - - ns
t5 data hold time from nstrobe 50 - - ns

Preliminary
SPCA702A
✝CD INPUT TIMING FOR CD_BCK RISING EDGE DIAGRAM
t1 t2
CD_BCK
CD_LRCK t3 t5
CD_DATA t4 t6
✝CD INTERFACE TIMING TABLE
Limit
Min. Typ. Max.
t1 CD_BCK high pulse width 100 235 - ns

t2 CD_BCK low pulse width 100 235 - ns
t3 CD_LRCK setup 10 235 - ns
t4 CD_DATA setup 10 235 - ns

Preliminary
SPCA702A
✝AUDIO INTERFACE TIMING DIAGRAM
AUD_XCK
AUD_BCK t1
AUD_LRCK t2
AUD_DATA t2
✝AUDIO INTERFACE TIMING TABLE
Limit
Min. Typ. Max.
t1 AUD_XCK high to AUD_BCK valid 1.0 2.0 5.0 ns

t2 AUD_BCK low to AUD_LRCK,AUD_DATA valid 1.0 2.0 5.0 ns

Preliminary
SPCA702A
✝8BIT VIDEO OUT TIMING DIAGRAM
t0 t1 t2
CLK27_OUT

Preliminary
SPCA702A
✝RESET AND CLOCK SIGNALS TIMING TABLE
RESET_B t1
RESET_B Signal Timing
t2
t3
CLK_OUT27 t4
CLK_OUT27 Signal Timing
✝RESET AND CLOCK SIGNALS TIMING DIAGRAM
Limit
Min. Typ. Max.
t1 RESET_B width 250 - - ns

t2 CLK_OUT27 period 35.2 37 38.9 ns
t3 CLK_OUT27 high width 16 20 21 ns
t4 CLK_OUT27 low width 16 17 21 ns
The Relationship Between Voltage (V) and the Current (mA):
400
Current (mA)
300
200
100
0
2.8 3 3.2 3.4 3.6 3.8 4
Voltage (V)
Note: Variation of Kernel voltage. I/O Voltage is @ 5V.

Preliminary
SPCA702A
APLICATION CIRCUIT NOTES

✝APPLICATION CIRCUIT - (1)
DRAM_D[0..15] ROM_D[0..7]
DRAM_A[0..8]
VCC
ROM_A[0..17]
VCC
VCC
VCC
/RAS0 GND
/CAS
/DRAM_WR
GND
VCC
GND
AVCC3
GND
GND
/HSYNC
/VSYNC
AUDIO FILTER ( 20 mil wire ) LOUT JACK
YC[0..7]
S-VIDEO JACK
AUD_XCK
AUD_LRCK
AUD_DATA
AUD_BCK
AGND
AVCC
PAL/NTSC
VID_CLK VGND
AVCC3
3.3V VGND AGND
GND GND
VGND CVBS JACK
3.3V GND 3.3V
AVCC
GND
=0, CVBS
=1, S-VIDEO
AVCC3 3.3V VGND AGND
AGND
AGND ROUT JACK

VGND
VGND GND

Preliminary
SPCA702A
V ID _C LK
D S A_ STB/I 2C _S D A
D SA _D ATA/ I2C _S C L
D SA _A CK
IR _O U T
IR _IN
V FD _S TB
V FD _C LK
VF D _ DA TA
G ND
GND 3 .3V G ND V CC 2. 5 3 .3V
V CC 2. 5
VCC
3 .3V
R ES E T
NW R ITE
N STR O BE 3 .3V
ND A TA 0 V CC 2. 5
ND A TA 1
ND A TA 2
ND A TA 3 VCC
ND A TA 4
ND A TA 5
ND A TA 6
ND A TA 7
GND
G ND
V CC 2. 5
G ND
3 .3V
V CC 2. 5
G ND
G ND
3 .3V
G ND

Preliminary
SPCA702A
GND
G ND
V CC3

Preliminary
SPCA702A
AVCC3
VVCC
VVCC
AVCC3
3.3V VGND
GND GND VGND
VGND
3.3V GND 3.3V
GND
VGND
VGND
AVCC3 3.3V VGND
VGND GND
AVCC3
3.3V VGND
GND
VGND
GND 3.3V
GND
AVCC3 3.3V
GND
AGND
GND
AVCC
AGND
AVCC
AGND
AGND
AGND AVCC
AGND

Preliminary
SPCA702A
PACKAGE OUTLINE DIMENSIONS

Preliminary
SPCA702A
DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions
stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description
regarding the information in this publication or regarding the freedom of the described chip(s) from patent
infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR
ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any
time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in
this publication are current before placing orders. Products described herein are intended for use in normal
commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military
equipment or medical life support equipment, are specifically not recommended without additional processing by
SUNPLUS for such applications. Please note that application circuits illustrated in this document are for
reference purposes only.

Preliminary: SPCA702A

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Preliminary SPCA702A

A common implementation utilizing the SPCA702A is presented below:

Figure 1-1 VCD System Block Diagram

Sunplus Technology Co., Ltd. 1 Rev.: 0.1 2000.10.05

Sunplus Technology Co., Ltd. 2 Rev.: 0.1 2000.10.05

Sunplus Technology Co., Ltd. 3 Rev.: 0.1 2000.10.05

✝CD INTERFACE SIGNALS

This pin is input for serial data from CD-DSP.

CD_LRCK CD left/right clock Input

CD_LRCK provides 16-bit word synchronization to the

SPCA702A and has several programmable features,

such as polarity, delay and pulse mode.

CD_BCK CD bit clock Input

Sunplus Technology Co., Ltd. 6 Rev.: 0.1 2000.10.05

ROM/GIO INTERFACE SIGNALS DSA_ACK Ack signal Bidirectional

Generic ROM address bus. DSA_STB Strobe signal Bidirectional

VFD_DATA data signal Bidirectional Strobe signal for DSA interface.

Data signal for VFD. IR_IN IR input Input

Clock signal for VFD. format IR signal.

VFD_STB strobe signal Output IR_OUT IR output pin Output

Strobe signal for VFD. IR output pin.

TIMERS AND TIME STAMPS

Sunplus Technology Co., Ltd. 7 Rev.: 0.1 2000.10.05

─ Decode Time Stamp (DTS)

─ Presentation Time Stamp (PTS)

─ DSM as Time Master

─ Audio as Time Master

Sunplus Technology Co., Ltd. 8 Rev.: 0.1 2000.10.05

Sunplus Technology Co., Ltd. 9 Rev.: 0.1 2000.10.05

VIDEO PROCESSOR INTERFACE

The recommended interface scheme is shown in Figure 5-1 below:

Figure 5-2 Video Processor Interface

USAGE FOR 8 BIT VIDEO INTERFACE

DATA_TV(7:0) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11

Figure 5-3 8 bit Video Interface Timing

Sunplus Technology Co., Ltd. 10 Rev.: 0.1 2000.10.05

Sunplus Technology Co., Ltd. 11 Rev.: 0.1 2000.10.05

COLOR TABLE UPDATE

AUDIO OUTPUT INTERFACE

AUDIO OUTPUT INTERFACE SIGNALS

Sunplus Technology Co., Ltd. 12 Rev.: 0.1 2000.10.05

A typical connection scheme is shown in Figure 8-1 below:

Figure 8-1 Audio Output Interface

Figure 8-2 Audio Interface Clocking Modes

Sunplus Technology Co., Ltd. 13 Rev.: 0.1 2000.10.05

Sunplus Technology Co., Ltd. 14 Rev.: 0.1 2000.10.05

DRAM MAMORY MAP

Sunplus Technology Co., Ltd. 15 Rev.: 0.1 2000.10.05

Audio work buffer

Video Channel Buffer

Audio Channel Buffer

Reference Frame 0 - (Luma)

Reference Frame 1 - (Luma)

Sunplus Technology Co., Ltd. 16 Rev.: 0.1 2000.10.05

Sunplus Technology Co., Ltd. 17 Rev.: 0.1 2000.10.05

Table 11-1: BCK/Data rate/ LRCK relationships

1.42 MHz Normal 1.42 Mbits/sec 32

Table 11-2: CD Input Format

Sunplus Technology Co., Ltd. 18 Rev.: 0.1 2000.10.05