ECE 301 - VLSI System Design: Verilog HDL Dataflow Modeling Verilog HDL Dataflow Modeling
ECE 301 - VLSI System Design: Verilog HDL Dataflow Modeling Verilog HDL Dataflow Modeling
U N IVE R S ITY
Objectives
After completing this lecture, you will be able to: Describe what is the dataflow modeling Describe how to use continuous assignments Describe how to specify delays in continuous assignments Describe the data types allowed in Verilog HDL Describe the operation of the operators used in Verilog HDL Describe the operands may be used associated with a specified operator
Slides are adopted from Digital System Designs and Practices Using Verilog HDL and FPGAs , John Wiley ECE301 VLSI System Design FALL 2012 S.Sivanantham
Why Dataflow ?
Rationale of dataflow: any digital system can be constructed by interconnecting registers and a combinational logic put between them for performing the necessary functions. Dataflow provides a powerful way to implement a design. Logic synthesis tools can be used to create a gate-level circuit from a dataflow design description. RTL (register transfer level) is a combination of dataflow and behavioral modeling.
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Continuous Assignments
Continuous assignment: the most basic statement of dataflow modeling. It is used to drive a value onto a net. It is always active. Any logic function can be realized with continuous assignments. It can only update values of net data types such as wire, triand, etc.
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Example:
Continuous Assignments
A continuous assignment begins with the keyword assign.
assign net_lvalue = expression; assign net1 = expr1, net2 = expr2, ..., netn = exprn;
net_lvalue is a scalar or vector net, or their concatenation. RHS operands can be variables or nets or function calls. Registers or nets can be scalar or vectors. Delay values can be specified.
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Continuous Assignments
An implicit continuous assignment is the shortcut of declaring a net first and then writing a continuous assignment on the net. is always active. can only have one implicit declaration assignment per net.
wire out; // regular continuous assignment assign out = in1 & in2; wire out = in1 & in2; // implicit continuous assignment
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Continuous Assignments
An implicit net declaration is a feature of Verilog HDL. will be inferred for a signal name when it is used to the left of a continuous assignment.
wire in1, in2; assign out = in1 & in2;
Note that: out is not declared as a wire, but an implicit wire declaration for out is done by the simulator.
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Delays
Three ways of specifying delays Regular assignment delay Implicit continuous assignment delay Net declaration delay Regular assignment delays The delay value is specified after the keyword assign. The inertial delay model is used (default model).
wire in1, in2, out; assign #10 out = in1 & in2;
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Delays
Implicit continuous assignment delays An implicit continuous assignment is used to specify both the delay and assignment on the net. The inertial delay model is used (default model).
// implicit continuous assignment delay wire #10 out = in1 & in2; // regular assignment delay wire out; assign #10 out = in1 & in2;
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Delays
Net declaration delays A net can be declared associated with a delay value. Net declaration delays can also be used in gate-level modeling.
// net delays wire #10 out; assign out = in1 & in2; // regular assignment delay wire out; assign #10 out = in1 & in2;
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Operators
Arithmetic +: add - : subtract * : multiply / : divide % : modulus **: exponent Shift << : left shift >> : right shift <<< : arithmetic left shift >>>: arithmetic right shift
Bitwise ~ : NOT &: AND | : OR ^: XOR ~^, ^~: XNOR case equality ===: equality !==: inequality Equality ==: equality !=: inequality
Reduction &: AND |: OR ~&: NAND ~|: NOR ^: XOR ~^, ^~: XNOR Logical &&: AND || : OR ! : NOT
Relational >: greater than <: less than >= : greater than or equal <=: less than or equal Miscellaneous { , }: concatenation {c{ }}: replication ? : conditional
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Precedence of Operators
Operators Unary Exponent Multiply, divide, modulus Add, subtract Shift Relational Equality Reduction Symbols + - ! ~ ** * / % + << >> <<< >>> < <= > >= == != === !== & ~& ^ ^~ | ~| && || ?:
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Precedence Highest
Logical Conditional
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Operands
The operands in an expression can be any of: constants, parameters, nets, variables (reg, integer, time, real, realtime), bit-select, part-select, array element, and function calls
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Constants
Three types of constant in Verilog HDL are integer, real, and string Integer constant simple decimal form
-123 12345 // is decimal -123 // is decimal 12345
Constants
Real constant decimal notation
1.5 // .3 // illegal --1294.872 //
scientific notation
15E12 32E-6 26.176_45_e-12
String constant A string is a sequence of characters enclosed by double quotes (""). It may not be split into multiple lines. One character is represented as an 8-bit ASCII code.
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Data Types
Two classes of data types: nets: Nets mean any hardware connection points. variables: Variables represent any data storage elements. Variable data types reg integer time real realtime
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Vectors
A vector (multiple bit width) describes a bundle of signals as a basic unit. [high:low] or [low:high] The leftmost bit is the MSB. Both nets and reg data types can be declared as vectors. The default is 1-bit vector or called scalar.
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The Memory
Memory Memory is used to model a read-only memory (ROM), a random access memory (RAM), and a register file. Reference to a memory may be made to a whole word or a portion of a word of memory.
reg [3:0] mema [7:0]; // 1-d array of 4-bit vector reg [7:0] memb [3:0][3:0]; // 2-d array of 8-bit vector wire sum [7:0][3:0]; // 2-d array of scalar wire mema[4][3] // the 3rd bit of 4th element mema[5][7:4] // the higher four bits of 5th element memb[3][1][1:0] // the lower two bits of [3][1]th element sum[5][0] // [5][0]th element
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Bitwise Operators
Bitwise operators They perform a bit-by-bit operation on two operands. A z is treated as x in bit-wise operation. The shorter operand is zero-extended to match the length of the longer operand.
Symbol ~ & | ^ ~^, ^~ Operation Bitwise negation Bitwise and Bitwise or Bitwise exclusive or Bitwise exclusive nor
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un1_out
out
un4_out
out
un6_out
i3
un8_out
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Arithmetic Operators
Arithmetic operators If any operand bit has a value x, then the result is x. The operators + and can also used as unary operators to represent signed numbers. Modulus operators produce the remainder from the division of two numbers. In Verilog HDL, 2s complement is used to represent negative numbers. Symbol Operation
+ * / ** %
ECE301 VLSI System Design
module four_bit_adder(x, y, c_in, sum, c_out); // I/O port declarations input [3:0] x, y; // declare as a 4-bit array input c_in; output [3:0] sum; // declare as a 4-bit array output c_out;
x[3:0]
[3:0] [3:0] [3:0] [3:0]
// Specify the function of a 4-bit adder. assign {c_out, sum} = x + y + c_in; endmodule
y[3:0] c_in
+
sum_1[4:0]
[4:0]
[3:0]
[3:0]
[3:0]
sum[3:0]
sum[3:0]
[4]
c_out
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+
sum_1[4:0]
[4:0]
[3:0]
[3:0] [3:0]
sum[3:0]
t[3:0]
c_in
sum[3:0]
[4]
c_out
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Reduction Operators
Reduction operators perform only on one vector operand. carry out a bit-wise operation on a single vector operand and yield a 1-bit result. work bit by bit from right to left.
Symbol & ~& | ~| ^ ~^, ^~
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Operation Reduction and Reduction nand Reduction or Reduction nor Reduction exclusive or Reduction exclusive nor
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op
x[8:0]
[8:0]
[7] [8]
op
ep
ep
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zero
un1_zero
one
one
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Logical Operators
Logical operators They always evaluate to a 1-bit value, 0, 1, or x. If any operand bit is x or z, it is equivalent to x and treated as a false condition by simulators.
Symbol ! && || Operation Logical negation Logical and Logical or
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Relational Operators
Relational operators They return logical value 1 if the expression is true and 0 if the expression is false. The expression takes a value x if there are any unknown (x) or z bits in the operands.
Symbol > < >= <= Operation Greater than Less than Greater than or equal Less than or equal
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Equality Operators
Equality operators compare the two operands bit by bit, with zero filling if the operands are of unequal length. return logical value 1 if the expression is true and 0 if the expression is false. The operators (==, !=) yield an x if either operand has x or z in its bits. The operators (===, !==) yield a 1 if the two operands match exactly and 0 if the two Symbol Operation operands not match == Logical equality exactly. != Logical inequality
=== !==
ECE301 VLSI System Design FALL 2012
module four_bit_comparator(Iagtb, Iaeqb, Ialtb, a, b, Oagtb, Oaeqb, Oaltb); // I/O port declarations input [3:0] a, b; input Iagtb, Iaeqb, Ialtb; output Oagtb, Oaeqb, Oaltb; // dataflow modeling using relation operators assign Oaeqb = (a == b) && (Iaeqb == 1); // equality assign Oagtb = (a > b) || ((a == b)&& (Iagtb == 1)); // greater than assign Oaltb = (a < b) || ((a == b)&& (Ialtb == 1)); // less than endmodule
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Shift Operators
Logical shift operators >> operator: logical right shift << operator: logical left shift The vacant bit positions are filled with zeros. Arithmetic shift operators >>> operator: arithmetic right shift <<< operator: arithmetic left shift
The vacant bit positions are filled with zeros.
Symbol >> << >>> <<< Operation Logical right shift Logical left shift Arithmetic right shift Arithmetic left shift
The vacant bit positions are filled with the MSBs (sign bits).
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Shift Operators
// example to illustrate logic and arithmetic shifts module arithmetic_shift(x,y,z); input signed [3:0] x; output [3:0] y; output signed [3:0] z; assign y = x >> 1; // logical right shift assign z = x >>> 1; // arithmetic right shift endmodule
Note that: net variables x and z must be declared with the keyword signed. Replaced net variable with unsigned net (i.e., remove the keyword signed) and see what happens.
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un1_s1_1
e d e d out
un1_s1_2
e d e d
out un1_s0_1
un1_s0_2
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