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Gujarat Technological University: Instructions

This document appears to be an exam for a course on VLSI Technology and Design. It contains 5 questions related to concepts in VLSI design, including approaches to reduce complexity in IC design, isolation techniques between transistors, layout rules for a CMOS inverter, expressions for threshold voltage and drain current in MOSFETs, scaling techniques, and basic logic gates like the CMOS inverter and NOR gate. It also asks about concepts like propagation delay, switching threshold voltage, power dissipation, transmission gates, D flip-flops, dynamic CMOS logic issues, and voltage bootstrapping.

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Archana Trivedi
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74 views2 pages

Gujarat Technological University: Instructions

This document appears to be an exam for a course on VLSI Technology and Design. It contains 5 questions related to concepts in VLSI design, including approaches to reduce complexity in IC design, isolation techniques between transistors, layout rules for a CMOS inverter, expressions for threshold voltage and drain current in MOSFETs, scaling techniques, and basic logic gates like the CMOS inverter and NOR gate. It also asks about concepts like propagation delay, switching threshold voltage, power dissipation, transmission gates, D flip-flops, dynamic CMOS logic issues, and voltage bootstrapping.

Uploaded by

Archana Trivedi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Seat No.

: ________

Enrolment No.______________

GUJARAT TECHNOLOGICAL UNIVERSITY


B. E. - SEMESTER VI EXAMINATION WINTER 2012

Subject code: 161004 Subject Name: VLSI Technology and Design Time: 02.30 pm - 05.00 pm

Date: 05/01/2013 Total Marks: 70

Instructions:
1. Attempt any five questions. 2. Make suitable assumptions wherever necessary. 3. Figures to the right indicate full marks.

Q.1

(a) Discuss following approaches (with examples) used to reduce 07 complexity of IC design: 1. Hierarchy, 2. Regularity, 3. Modularity, and 4. Locality. (b) Why do we need isolation between MOS transistors fabricated on a 07 single chip? Explain etched field-oxide isolation and LOCOS isolation techniques with diagrams. (a) Draw layout of CMOS Inverter and indicate minimum eight layout 07 rules of your choice in terms of . (b) Derive expression for the maximum possible depth of the depletion 07 region in two-terminal MOS structure. OR (b) Calculate the threshold voltage for a polysilicon gate nMOS transistor 07 with the following parameters: NA = 2 x 1016 cm-3, ND = 2 x 1019 cm-3, tox = 300 x 10-8 cm, and Nox = 1010 cm-2. Take kT/q = 26 mV, ni = 1.45 x 1010 cm-3, q = 1.6 x 10-19 C, ox = 3.97 x 8.85 x 10-14 F/cm, si = 11.7 x 8.85 x 10-14 F/cm. (a) What do you understand by gradual channel approximation? Derive expression for the drain current flowing through n-channel MOSFET as a function of VGS, VDS, and VBS. (b) Derive expressions for VIH and VIL for CMOS Inverter. OR (a) Explain constant field scaling device reduction strategy and show that the power density does not change in a device scaled using this technique. (b) Discuss the effect of supply voltage scaling on VTC (voltage transfer characteristic) of CMOS Inverter. What is the minimum VDD below which VTC exhibits hysteresis effect? 07

Q.2

Q.3

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Q.3

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Q.4

(a) Define propagation delay and derive expression for PHL for CMOS 07 Inverter. Assume ideal step as an input to CMOS Inverter. (b) Draw two-input CMOS NOR gate and obtain expression for switching 07 threshold voltage (vth). Assume that both NMOS transistors are identical. Similarly, PMOS transistors are also identical.
OR

Q.4

(a) Obtain expression for switching power dissipation in CMOS Inverter 07 circuit. Assume ideal step as an input to CMOS Inverter. Under what constraints, derived expression can be applied to any CMOS logic circuit?
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(b) Justify importance of transmission gate. Draw six-transistor CMOS 07 transmission gate implementation of the XOR function. Verify its functionality. Q.5 (a) Draw CMOS negative edge-triggered master-slave D flip-flop and explain its working. (b) Explain cascading problem observed in dynamic CMOS logic. What are the different approaches to solve this problem? OR (a) What is the need for voltage bootstrapping? Explain dynamic voltage bootstrapping circuit with necessary mathematical analysis. (b) List out possible electrical and logical faults observed in the circuit. Define controllability and observability.
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