Resume Text: TRIPTI YADAV M.Tech (VLSI Design) Mobile no: +**-988******* Contact job Email_id:[email protected]/[email protected] seekers m directly.

* Currently working as Member of Technical Staff in KPIT Plans start Cummins, Bangalore since 2nd NOV 2010, in Analog Layouts from for High Speed Links. Before this I have worked with HCL $24.99/month Technologies, Noida (U.P.) from July 2007 to October 2010, . in Analog circuit Design & Layout Group. CAREER OBJECTIVE A challenging and innovative career in Analog Circuit Design andLayout/Semiconductor Devices, Which will allow me to contribute for the advancement of technology for the next generation. PROFILE 4.9 years of experience in Analog domain (Analog and Standard Cell layoutdevelopment in 180nm, 130nm, 90nm, 65nm, 45nm, 40nm, 32nm, & 28nm with TSMC, Tower & ST foundries, Schematic Entries, Designing, Simulation & Analysis of Analog circuits) and Standard Cells Library Build and Validation inAnalog Domain. Layout for High speed links, serdes, transceivers. Good command on virtuoso, calibre, Laker. Strong concepts of Analog CMOS design and Digital design. TECHNICAL SKILLS Schematics design tools : Design Architect-IC, S-Edit, Virtuoso Simulation tool : Eldo, Hspice and Cadence(Analog Environment) Virtuoso, Analog Environment-ADE5141, ADE610 Waveform Viewer : Ezwave, Waveview analyzer, W-Edit Layout : Virtuoso, Laker, L-Edit Physical Verification : Calibre Synthesis Tool : Leonardo Spectrum Automation : PERL, TCL, SKILL (basic) Languages : Verilog, System Verilog, VHDL, C (basic) Target Platforms : Unix, Linux, Solaris, Windows QUALIFICATIONS Master of Technology (VLSI Design) Banasthali Vidyapith, Jaipur (Rajasthan) Year of passing: June 2008 Percentage : 73%

GATE 2006 Score 328 Bachelor of Engineering (Electronics & Communication) Gyan Vihar School of Engineering & Technology, Jaipur (Rajasthan) Year of passing: 2005 Percentage: 77% PROJECTS DETAILS: #01: Projects at ST,Microelectronics (Nov 2010 Feb 2012): Working as Full custom Layout engineer in Analog mixed signal CMOS Layouts and standard cell layouts also for High Speed Links. Executed different types of Primary responsibilities which involve Floor planning, Placement, Routing and Verification on both Block level and Chip level layout. Technology: 90nm, 65nm, 45nm, 32nm, 28nm. Tools used: Virtuoso, Virtuoso-XL, Calibre (DRC, LVS, SRD, DFM). Platform: Linux, Unix. Role: Layout development, Physical verification, EM check. Projects: USB 2.0 Rx, MPHY, DPHY & DigRF Receivers, PWM-Rx, MIPI, HDMI Description: These Projects involve the Floor planning, placement, routing and physical verification at the top chip level consisting all sub blocks, such as ESD circuits, driver, pre-driver, level shifters, differential amplifiers, Op-Amps, current Mirrors and biasing circuits etc. My Role: Layout development of Differential Amplifiers, Current Mirrors, OpAmps, Comparators, BGR, LDO, Bias blocks, Control Logic block, Offset Logic block, Standard Cells etc. Responsibilities: These layouts include highly matching devices like current mirrors and differential amplifiers, also matching nets, resistors and capacitors. Mostly common centroid technique is used to satisfy critical matching and to get more precision. Dummies prevention is done for all sensitive analog sections of the macro. Done basic floor plan of the sub-blocks and arranged them within the allotted area and successfully completed the chip level integration also. The issues like ESD, latch-up, Antenna, Density are taken care. Electro migration checks were done for all macros. Electro migration rules are met by

calculating appropriate metal widths. Also complex power routing is done to satisfy the current density requirement of the macro. Took care the Noise concepts also like Guard Ring, Shielding, Decoupling-caps etc. I have done tile generation also for taking care the metal densities. Run Physical verification checks like DRC, LVS, SRD, DFM, ERC, Soft checks, Antenna violation, PLS & EM checks. Conversion of 10M (10 metal) to 8M. #02: Designs of Low Offset Two Stage Op-Amp including Scaling and Mismatches This activity involved design and layout of single ended opamp with two stages. This block was designed by using 3.3V TSMC 130nm GP 1Pm8 CMOS technology. The Op-amp is implemented in unity gain buffer configuration. It provides open loop gain of 90db with UGB of 35 MHz. It works very well in the common mode range of 0V-2.3V and showing offset of 25uV across PVT. Tools/Environment : Virtuoso, Caliber, H-Spice, Waveform viewer/Linux Design Results : OPAMP implementation as an integrator. Characterization of op-amp for PSRR, CMRR, slew rate, gain, offset, 3db and UGB. Layout of two stage op-amp. Post layout simulation and analysis #03: Designing of High Speed & High Resolution Latched Comparator To combine the sample-and-hold function with the comparison in a quantizer, the latched-type comparator is the best choice. Latch comparator is regenerative comparator. Regenerative comparator use positive feedback to accomplish comparison of two signals. They have least propagation delay. This block was designed by using 3.3V TSMC 130nm GP 1Pm8 CMOS technology. It works very well in the common mode range of 0.8V- 3.1V and showing the offset of 18uV across PVT. It gives 1.8ns propagation delay and works till 250 MHz. Tools/Environment : Virtuoso, Caliber, H-Spice, Waveform viewer/Linux Design Results : Characterization of comparator for Resolution, offset, ICMR

and speed. Comparator is implemented for oversampling. Layout of the comaparator. Post layout simulation and analysis Application: High Speed A to D Converters (Sigma-Delta Modulator) High Speed Sampling Circuits #04: Spread Spectrum PLL (Phase Locked Loop) This project involved design of Spread Spectrum Phase Lock Loop using 1.2V & 3.3V TSMC 130nm GP 1Pm8, which consists of various blocks like High Voltage Regulator (HVR), Band gap reference circuit (BGR), Power-On-Reset Circuit (POR) and Low Voltage Differential Signalling Interface (LVDS) . The SSPLL is a normal PLL in functioning, with an additional modulator block, which modulates the output clock frequency over a desired band of frequencies. Tools/Environment : DA_IC, LAKER, Caliber, H-Spice, Tanner/Linux Design Results : Schematic entry of BGR, HVR, LVDS-Tx & Rx, SSPLL. Layout Development of Folded Cascode block & some digital blocks like Inverter, NAND, NOR etc. and physical design verification in the 0.13um TSMC GP technology. Designing of PFD Block of PLL. Simulation & Analysis of LVDS-Rx, HVR, PLL Blocks. Pre and Post Layout Characterization # 05: Developed PERL script to automate the simulation environment Developed a Perl script which aided to the automation for the output generated like power dissipation, applied inputs etc. at various PVT corners by the simulation to be available in a single output file which made it easier for the design engineer to do the comparative analysis of various parameters and outputs at different PVT corners. Tools/Environment : HSpice/Linux Design Results : Successfully developed the script. #07: Crane Aerospace, MD51-ASIC-Design-Review Project This project was to Develop, Verify and Review of the Checklists and was to document properly the schematics so that they can be used for future reference without any problem by the client.

Tools/Environment: Microsoft office/Windows XP Design Results: Developed the Checklists as well as Defect lists in proper documented form. #08: Virage-Lib Quality & Characterization (July 2008 Sept 2008) This project involved characterization, build and validation of different libraries for different foundries like TSMC, NEC, CP (Common Platform) etc. of different technologies like 130nm, 90nm, 65nm, 45nm , etc. for various purposes like High Density, High Speed and ultra high density for standard Vt (SVT), high Vt (HVT), & low Vt (LVT). Tools/Environment: Synopsys & Cadence Tools like Astro, SOCE, RIPD (Rapid IP development) Design Results: Performed Build & Validation #09: High Speed Flip flop design This activity involved design of high speed flip flop for PLLs operating in range of > 1GHz. Flip flop was made using master slave configuration of two dynamic latches. Design was done in 1.2V TSMC 130nm GP 1Pm8. Flip flop was used in post dividers of PLL to divide PLL output by factor ranging 10-125. Assuming parasitic cap of 3f on gate of mosfet, frequency of 1.6GHz was achieved at prelayout stage. Design Results : Design of Flip flop (dynamically latched) Characterization for propagation delay, setup time, hold time, duty cycle. Application: PLL edge detector TRAININGS Static Timing Analysis: This training included the basic understanding of various concepts related to static timing analysis. Low power design methodologies: This training included various methodologies used in implementing the low power specific designs. Standard cells layout design: This training included the layout design of standard cells and various concepts related to designing optimized standard cells layout. Analog circuit design and layouts: This training included the basic differential amplifier design and power amplifier design, RF concepts, Low Noise

Amplifier design and layouts of analog circuits including matching, device placement, sufficient guard ring protection of sensitive devices and proper width selection of metal wires carrying large amount of currents. ACHIEVEMENTS: Got II Rank in DRDO for the post of JRF in CFEES Delhi Certificates in French & German languages Attended workshop on Department Of Management Studies Entrepreneurship Development Cell from MNIT, Jaipur and The National Workshop on Models of Embedded Computation State-Level Table-Tennis Player and 4 times consecutive winner at district level. Other than it from 2007 to 2010 in HCL Technologies, champion in Singles, Doubles and Mixed Doubles as well. Sports council head in HCL-Tech and organized successfully Chess, Carom and Table-Tennis events. Stood first in Horse-riding in Banasthali Vidyapith. STRENGTHS: Team player Target and achievement oriented with an ability to take up challenges and perform in challenging work environments Unique blend of technical and interpersonal skills Quick Learner and Adjustable to the desired Environment. PERSONAL DETAILS: Name : Tripti Yadav Date of Birth : 04th April, 1984 Marital status : Married Languages Known : English, Hindi, Frech & German Hobbies : Gardening, playing TT, Travelling, listening music. Address : W/O Mr. Nipun Dev, PR-605, Golden Blossom Apartment, Kadugodi - 560067 - TRIPTI YADAV

Analog Design Engineer Resume Example

Katrine Howe 1372 Metz Lane Cambridge, Massachusetts 2141 Cell: (111)-963-8764 email: [email protected] Career Objective: Skilled, resourceful and dynamic individual with extensive knowledge of evaluating engineering approaches and defining electronic designs for new and existing instruments, looking for an analog design engineer in a renowned organization Professional strengths: Comprehensive knowledge of the concepts, practices and processes of analog designing Extensive knowledge of analog engineering techniques, analysis and approaches Sound knowledge of analog/mixed-signal IC development cycles Familiar with CAD tools, scripting/programming and Linux/Unix environments In-depth knowledge of analog signals ,systems and design principles Possess strong interpersonal, organizational, written and verbal skills Skilled in establishing and maintaining effective working relationships with sales, customers, marketing and field applications

Professional Experience: Organization: Kanos Duration: June Designation: Analog Design Engineer Inc, 2010 till Massachusetts date

Responsible for developing high performance circuits by using advanced deepsubmicron fabrication technologies Handle the tasks of developing analog and mixed-signal integrated circuits for various wireless products Perform responsibilities of assessing system requirements, designs, and specifications Handle the task of creating analog and mixed-signal circuits as well as provide support for circuit integration Responsible for preparing engineering documents and delivering engineering presentations Prepared transistor-level analog and mixed-signal circuit designs Handle the tasks of verifying mixed-signal analog circuit layout Perform responsibilities of providing guidance on analog circuit evaluation to junior engineers Piezotronics, to Massachusetts 2010

Organization: PLC Duration: May 2008 Designation: Junior Analog Design Engineer Handle the tasks of proprietary CAD flows developing

March

analog/mixed-signal

hard

macros by using

Responsible for creating analog design specifications Assist analog engineer in performing circuit design in 0.18um to 28nm CMOS processes technologies Perform the tasks of setting-up, running and analyzing circuit simulations Handle responsibilities of characterizing silicon and preparing silicon verification reports Responsible for creating behavioral models in verilog as well as perform IC layout and verification Performed other engineering duties as assigned by senior engineers

Objective: Looking for a challenging and responsible position in IC mask layout design. Experience: Summary - Proficient in custom analog/mixed-signal and RF layout design, particularly at 90nm and 65nm processes technologies. - Experienced in floor planning, placement and routing of macro blocks, full chip integration and tape out. - Experienced in physical verification including run file creation, job running, strong debug and problem solving skill for LVS/DRC/ERC and layout issues. - Ability to work efficiently as a part of team as well as independently with supervisory experience. Specialties - Knowledge of Cadence Virtuoso XL, Calibre, Hercules and DRACULA, ASSURA, DIVA verification tools. - Knowledge of UNIX and Linux systems, Perl and SKILL language code. - Highly motivated and able to learn and use new CAD tools and methodologies, creative and productive, able manage schedule to deliver projects on time. - Strong analytical skills and communication skills with circuit design background. Professional Experiences September 2009 C January 2010 Contractor, RF & Analog & Mixed-Signal Mask Layout Design, Qualcomm Inc. - Maintained full responsibility of mask layout design for an new high performance power detector design and an new Voltage Standing Wave Ratio (VSWR) design to monitor/protect a integrated Power Amplifier used in a Wireless LAN product using 65nm CMOS process - Chip integration and verification using Cadence and Mentor Calibre CAD tools. April 2007 C October 2009 Sr. Staff Analog Layout Design Engineer, Eastman Kodak Company, Sunnyvale, CA - Maintained full responsibility of layout design for CMOS image sensor chip including floor planning, layout creation for IOs, bandgap, PLL, ADC, regulator, charge pump, etc. using Cadence-Virtuoso, physical verification using Cadence Assura and Mentor Graphics - Calibre, 0.13um, 0.11um and 0.09um CMOS process.

- Fully responsible for full chip integration and verification for final tape out. May 2004 C September 2006 Sr. Layout Design Engineer, OmniVision Technologies, Inc. Sunnyvale, CA - Maintained full responsibility for CMOS image sensor chip mask layout design including floor planning, layout creation using Cadence-Virtuoso, physical verification using Cadence Assura and Mentor Graphics - Calibre, 0.13um, 0.11um and 0.09um CMOS process. - Fully responsible for full chip integration and verification (DRC/LVS/ERC) for final tape out. June 2003 C May 2004 Sr. Layout Design Engineer, Lattice Semiconductors, San Jose, CA Lead mask layout design for FPGA chip including floor planning, layout creation for blocks and full chip integration and tape out using Cadence-Virtuoso, physical verification (LVS/DRC) used Cadence Assura and Mentor Graphics - Calibre, 0.13um CMOS process. Sept 2001 C Nov 2002 Lead Layout Design Engineer, Spreadtrum Communications, Corp., Santa Clara, CA - Lead custom layout work of wireless communication chips using Cadences Virtuoso layout tool, 0.18um CMOS process. Custom layout includes SRAM, I/O buffers, PLL, D/A, A/D converters and other mixed-signal blocks.Responsibility includes floor planning, key block layout and top-level integration, DRC/LVS verification using Assura/DIVA, Dracula and Hercules and deliver GDSII database. - Responsible for full chip physical verification (DRC/LVS/ERC), RC extraction and tape out database. - Chip floor plan, placement and routing, clock tree synthesis, timing closure and ECO using Avant! Tools. July 1998 C Sept 2001 Sr. Staff Physical Design Engineer, Infineon Technologies Corp., San Jose, CA - Performed custom layout of standard cells, I/O buffers and SRAMs, PLL, DAC for datacom, networking and DVD chips using Cadences IC layout tool, 0.25um and 0.18um CMOS process. Also laid out seal rings, logo etc. - Creation, debugging and maintain of LVS/DRC/ERC run files and related script files. Run and debug LVS/DRC on standard cell library, I/Os, DAC, PLL, memories and all module blocks and full chip tape out. - Floor planning, placement and route module blocks using Apollo/Silicon Ensemble, including timing driven layout, clock tree synthesis and ECO, metal fix revision. - Bonding diagram layout using Infineons in-house tool. October 1994 July 1998 Cirrus Logic, Inc. Fremont, California Sr. Layout Design Engineer - Layout design for 8 bit DAC, PLL and VCO for graphics chips (135MHz 5V, 175MHz 3.3V) and LAGUNA-3D chip (250 MHz 3.3 V) using Cadences IC layout tools. - Created DRACULA LPE run file and ran layout extraction for back annotation for highspeed mixed-signal circuit design. - Floor planning, P&R of modules and full chip, running LVS/DRC/ERC for all custom macros and full chip physical verification for final tape out. Analog Mixed-Signal IC Design Engineer - Responsible for circuit simulation, design modification and silicon debugging of bandgap voltage reference circuit, which is used as on-chip bias for D/A converter.

- Circuit simulation and design modification for 8-bit DAC, PLL and VCO for graphics chips (135 MHz 5 V, 175 MHz 3.3 V) and LAGUNA-3D chip (250 MHz, 3.3v). September 1992 C October 1994 VLSI Design Engineer, Trident Microsystems, Mountain View, California - Responsible for SRAM circuit simulation and layout design for RAMDAC used in graphics chips. - Responsible for circuit simulation and layout design for CMOS standard cell library and I/O buffers. - Responsible for layout design of control logic and data path blocks of graphics chip using symbolic layout technique with Cadences EDGE. - Responsible for chip level floor planning, P&R, post-layout check (DRACULA-LVS/DRC/LPE) and full chip tape out.

Education: MSEE, major in IC design, Clarkson University, Potsdam, New York BSEE, ma