Scribd
Upload
73 views37 pages

Introduction To FPGA: Guan-Lin Wu

This document provides an introduction to field programmable gate arrays (FPGAs). It describes how FPGAs offer reconfigurability through programmable logic blocks and interconnects. The architecture of a typical FPGA is explained, including lookup tables, flip flops, block RAM, digital signal processing blocks, and input/output elements. An example FPGA, the Altera Cyclone II EP2C20, is described in detail regarding its logic elements, memory blocks, multipliers, phase locked loops, and I/O features. Major FPGA vendors are also listed.

Uploaded by

jeren1228
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
73 views37 pages

Introduction To FPGA: Guan-Lin Wu

This document provides an introduction to field programmable gate arrays (FPGAs). It describes how FPGAs offer reconfigurability through programmable logic blocks and interconnects. The architecture of a typical FPGA is explained, including lookup tables, flip flops, block RAM, digital signal processing blocks, and input/output elements. An example FPGA, the Altera Cyclone II EP2C20, is described in detail regarding its logic elements, memory blocks, multipliers, phase locked loops, and I/O features. Major FPGA vendors are also listed.

Uploaded by

jeren1228
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 37

Introduction to FPGA

Guan-Lin Wu

Outline
z z z z z

Introduction to PLD Introduction to FPGA FPGA Example Altera Cyclone II Altera Quartus II Lab

World of Integrated Circuits

Full-Custom ASICs

Semi-Custom ASICs

User Programmable

PLD

FPGA

Digital Logic
Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

Black Box

Truth Table

SUM of PRODUCTS Boolean Logic Minimisation

Connect Standard Logic Chips Very Simple Glue Logic FIXED Logic

Transistor Switches

Programmable Logic Devices PLDs


Different Types SUM of PRODUCTS Prefabricated Programmble Links Reconfigurable

Un-programmed State

Planes of ANDs, ORs

Logic Function

Inputs ANDs OR Sums

Programmed PLD Product Terms Sum of Products

How can we make a programmable logic?


z

SRAM-based
z z z z

Reconfigurable Track latest SRAM technology Volatile Generally high power One-time programmable Non-volatile security app.

Anti-fuse technique
z z

Complex PLDs
CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links

CPLD Architecture

Feedback Outputs

Field Programmable Gate Arrays FPGA


z

Field Programmable Gate Array


z z z

New Architecture Simple Programmable Logic Blocks Massive Fabric of Programmable Interconnects

Large Number of Logic Block Islands 1,000 100,000+ in a Sea of Interconnects

FPGA Architecture

Logic Blocks
z

z z

Logic Functions implemented in Lookup Table LUTs Multiplexers (select 1 of N inputs) Flip-Flops. Registers. Clocked Storage elements.
16-bit SR 16x1 RAM 4-input LUT

a b c d e clock clock enable set/reset

y mux flip-flop q

FPGA Fabric

Logic Block

Lookup Tables LUTs


z z z z

LUT contains Memory Cells to implement small logic functions Each cell holds 0 or 1 . Programmed with outputs of Truth Table Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR 16x1 RAM 4-input LUT

3 6 Inputs

a b c d e

y mux flip-flop q

clock clock enable set/reset

Multiplexer MUX

Static Random Access Memory SRAM cells

Logic Blocks
z

Larger Logic Functions built up by connecting many Logic Blocks together

Clocked Logic
z z z z

Flip Flops on outputs. CLOCKED storage elements. Sequential Logic Functions (cf Combinational Logic LUTs) Pipelines. Synchronous Logic Design FPGA Fabric driven by Global Clock (e.g. BX frequency)
16-bit SR 16x1 RAM 4-input LUT

a b c d e clock clock enable set/reset

y mux flip-flop q

FPGA Fabric

Clock

Circuit Compilation
1. Technology Mapping

LUT

2. Placement
LUT

?
3. Routing

Assign a logical LUT to a physical location.

Select wire segments And switches for Interconnection.

Routing Example
FPGA
Programmable Connections

Which Way to Go?


ASICs FPGAs Off-the-shelf High performance Low development cost Low power Short time to market Low cost in high volumes Reconfigurability

Other FPGA Advantages


z

Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower
z

Mistakes not detected at design time have large impact on development time and cost FPGAs are perfect for rapid prototyping of digital circuits

z z

Easy upgrades like in case of software Unique applications


z

reconfigurable computing

Major FPGA Vendors


SRAM-based FPGAs z Xilinx, Inc. Share over 60% of the market z Altera Corp. z Atmel z Lattice Semiconductor Flash & antifuse FPGAs z Actel Corp. z Quick Logic Corp.

FPGA Example Altera Cyclone II

Cyclone II EP2C20 Block


z z

Logic array LUTs Block memory M4K blocks Embedded Multipiers Input/output Modules (IOEs) PLLs

Cyclone II EP2C20 Block


Embedded Multipliers

Logic Array

M4K Memory Blocks

I/O Elements

Phase-Locked Loops

Cyclone II EP2C20
z z z z z z z z

18,752 LEs 52 M4K RAM blocks 240K total RAM bits 52 9x9 embedded multipliers 4 PLLs 16 Clock networks 315 user I/O pins SRAM Based volatile configuration

Logic Element
z

16 LEs forms a Logic Array Block (LAB)


z z

Normal mode Arithmetic mode

Logic Element

Logic Element
z

Normal Mode general logic operations

Logic Element
z

Arithmetic Mode adder, counter, accumulators, comparator

Logic Array Blocks Structure

Cyclone II Logic Array Block (LAB)


Fast Local Interconnect
z z z z

16 LEs Local Interconnect LE carry chains Register chains

4 4 4 4

LE1 LE2 LE3 LE4


Direct link interconnect to right

Direct link interconnect to left

4 4 4 4

LE13 LE14 LE15 LE16

Row Interconnect Connections


z

Direct link, R4, R24 interconnects

Column Interconnect Connections


z

Register chain, C4, C16

Register Chain Interconnects


z

LEs can be connected for implementing fast adder, counters, shift register

M4K RAM

Cyclone II I/O Features


z z z z z z z z z z

In/Out/Tri-state Different Voltages and I/O Standards


z

PCI, PCI-X, LVDS I/O standard

Flip-flop option Pull-up resistors DDR interface Series resistors Bus keeper Drive strength control Slew rate control Single ended/differential

Advance Architecture on Modern FPGAs

More Guts
z

Additional components
z z z

Dedicated computation units Processor cores DSP blocks

Dedicate Arithmetic Blocks

QuickLogic

Altera Xilinx

Processor Cores

Altera DE2-70

You might also like