Scribd
Upload
97 views

VHDL Quick Reference

This document provides examples of VHDL code including: 1) An RTL parameterized counter entity with a clock, reset, enable, and up/down signals. It uses a process to increment or decrement an internal counter signal. 2) A testbench entity that instantiates the counter, generates clock and reset signals, and runs assertions to test the counter output. 3) A Modelsim script example to compile the VHDL files, launch the simulation, view signals and run it.

Uploaded by

haythem_guidara3509
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
97 views

VHDL Quick Reference

This document provides examples of VHDL code including: 1) An RTL parameterized counter entity with a clock, reset, enable, and up/down signals. It uses a process to increment or decrement an internal counter signal. 2) A testbench entity that instantiates the counter, generates clock and reset signals, and runs assertions to test the counter output. 3) A Modelsim script example to compile the VHDL files, launch the simulation, view signals and run it.

Uploaded by

haythem_guidara3509
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Quick_Reference.

vhd

1 / 2

-------------------------------------------------------------------------------- Title
: VHDL Quick Reference
-------------------------------------------------------------------------------- File
: Quick_Reference.vhd
-- Author
: DOUZE Yann <[email protected]>
-- Company
: Polytech'Paris UPMC
-- Last update: 2006/09/5
-- Platform
:
-------------------------------------------------------------------------------- Description: Modles de syntaxe VHDL
----------------------------------------------------------------------------------------------------------------------------------------------Exemple typique de VHDL RTL (compteur paramtrable)
----------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use WORK.mypackage.ALL; -- si vous utilisez votre propre package
entity COUNTER is
generic(Counter_Width : positive := 8);
port( CLK
: in std_logic;
RST
: in std_logic; -- reset asynchrone
EN
: in std_logic; -- ENable
UP
: in std_logic; -- 1= counting up, 0 = down
Q
: out std_logic_vector(Counter_Width-1 downto 0)
);
end COUNTER;
architecture RTL of COUNTER is
signal iCount : unsigned(Q'range);
begin
Q <= std_logic_vector(iCount);
process(CLK,RST)
begin
if (RST='1') then
iCount <= (others => '0');
elsif rising_edge(CLK) then
if EN='1' then
if UP='1' then
iCount <= iCount + 1;
else
iCount <= iCount - 1;
end if;
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------Exemple typique de Test Bench
----------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE STD.textio.all;
USE IEEE.std_logic_textio.all;
ENTITY Counter_tb IS
END Counter_tb;
ARCHITECTURE bench OF Counter_tb IS
constant Width : positive := 8;
March 02, 2009

Crimson Editor

Quick_Reference.vhd

2 / 2

constant Period : time := 20 ns; --50 MHz system clock


signal clk,rst,en,up : std_logic := '0';
signal q : std_logic_vector(Width-1 downto 0);
begin
clk <= not CLK after (Period/2);
RST <= '1','0' after Period;
process
begin
wait for (10 * Period);
assert Q=x"00" severity error;
EN <= '1';
wait for ((2**Width -2) * Period);
assert Q=x"02" severity error;
UP <= '1';
wait for (14 * Period);
assert Q=x"10" severity error;
report "End of Simulation !" severity failure;
end process;
UUT : entity work.counter
generic map (Counter_Width => Width)
port map (clk => CLK, rst => RST, en
END bench;

=> EN, up => UP, Q => Q);

----------------------------------------------------------------- Exemple typique de script de simulation pour Modelsim


----------------------------------------------------------------#avant tout, changer de rpertoire pour se placer dans la librairie de travail
# ou alors rajouter la ligne suivante:
# cd ~/VHDL/myproject
# cration de la librairie de travail work
vlib work
#compilation des fichiers vhdl, l'ordre de compilation est important
#commencer par le package, les composants, le top-level design,
# le test-bench et enfin la config
#vcom -93 packages.vhd
#vcom -93 sources.vhd
#vcom -93 testbench.vhd
#vcom -93 config.vhd
#Exemple pour le cas du compteur
vcom -93 ../src/counter.vhd
vcom -93 counter_tb.vhd
#lancer la simulation avec le nom de la config (si elle existe)
#sinon avec le nom du testbench (si il existe)
#sinon avec le nom du top design
#pour chacun des cas precisez le nom de l'entite, pas le nom du fichier
vsim counter_tb(bench)
#pour visualiser tout les signaux du design:
view signals
#view structure
add wave *
#lance la simulation:
run -all

March 02, 2009

Crimson Editor

You might also like