Scribd
Upload
61 views5 pages

Informe 2

The document contains 5 problems describing VHDL code for counter circuits. Problem 1 describes a 4-bit counter with clock, clear and enable inputs that resets to 0 when it reaches 5. Problem 2 describes a 4-bit counter with additional output based on the counter value. Problem 3 describes a circuit to divide a clock signal based on a 2-bit selector input. Problem 4 describes an up/down 4-bit counter. Problem 5 describes cascading 3 counters to generate 3 clock signals.

Uploaded by

Marco Jara
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
61 views5 pages

Informe 2

The document contains 5 problems describing VHDL code for counter circuits. Problem 1 describes a 4-bit counter with clock, clear and enable inputs that resets to 0 when it reaches 5. Problem 2 describes a 4-bit counter with additional output based on the counter value. Problem 3 describes a circuit to divide a clock signal based on a 2-bit selector input. Problem 4 describes an up/down 4-bit counter. Problem 5 describes cascading 3 counters to generate 3 clock signals.

Uploaded by

Marco Jara
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Prolemas propuestos: PROBLEMA 1 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.

all; Entity contador is Port ( clk: in std_logic; clear: in std_logic; ena: in std_logic; q: buffer std_logic_vector (3 downto 0)); End contador; Architecture algoritmo of contador is Begin Process(clk,clear) begin if clear='1' then q<="0000"; elsif clk='1' and clk'event then if ena='1' then q<= q + 1; if q=5 then q<="0000"; end if; end if; end if; end Process; end algoritmo;

PROBL EMA 2 Library ieee; Use ieee.std _logic_ 1164.all ; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Entity contador_cl_ena_2 is Port ( clk: in std_logic; clear: in std_logic; ena: in std_logic; salida: out std_logic_vector (3 downto 0)); --q: buffer std_logic_vector (3 downto 0)); End contador_cl_ena_2; Architecture algoritmo of contador_cl_ena_2 is signal q : std_logic_vector(3 downto 0); Begin Process(clk,clear) begin if clear='1' then q<="0000"; elsif clk='1' and clk'event then if ena='1' then q<= q + 1; if q="0100" then q<="0000"; end if; case q is when "0000"=>salida<="0100"; when "0001"=>salida<="0111"; when "0010"=>salida<="0000"; when "0011"=>salida<="0001"; when others=>salida<="0101"; end case;end if;end if; end Process;end algoritmo;

PROBLEMA 3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DIV_nHZ is Port ( clk : in std_logic; selector: in std_logic_vector(1 downto 0); reloj : buffer std_logic); end DIV_nHZ; architecture Behavioral of DIV_nHZ is --signal cnt: std_logic_vector(4 downto 0); begin process(clk) variable cuenta: std_logic_vector(4 downto 0); variable cnt: std_logic_vector(4 downto 0); begin if clk='1' and clk'event then cuenta:= cuenta+1; case selector is when "00"=> cnt:= "00001" ; when "01"=> cnt := "00010" ; when "10"=> cnt := "00100" ; when others => cnt:= "10000" ; end case; if cuenta = cnt then cuenta:= (others=>'0'); reloj <= not reloj; end if; end if; end process; end Behavioral;

PROBLEMA 4 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity contador_cl_ena is Port ( clk: in std_logic; clear: in std_logic; ena: in std_logic; q: buffer std_logic_vector (3 downto 0); up_down: in std_logic); End contador_cl_ena; Architecture algoritmo of contador_cl_ena is Begin Process(clk,clear) begin if clear='1' then q<="0000"; elsif clk='1' and clk'event then if ena='1' then if up_down = '1' then q<= q + 1; if q= 7 then q<="0000"; end if; else q<= q-1; if q= 0 then q<="0111"; end if; end if; end if;end if; end Process;end algoritmo;

PROBLEMA 5 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity contd_12 is port( clk1 : in std_logic; clk2: buffer std_logic; clk3: buffer std_logic; q2,q3: buffer std_logic_vector(22 downto 0); q1: buffer std_logic_vector(22 downto 0)); end contd_12; architecture solu of contd_12 is begin process(clk1) begin if clk1='1' and clk1'event then q1<= q1 + 1; if q1= 4999999 then q1<=(others=>'0'); clk2<=not clk2; end if;

if clk2 = '1' then q2<=q2+1; if q2=249 then q2<=(others=>'0'); clk3<=not clk3; end if; else q3<=q3+1; if q3=82 then q3<=(others=>'0'); clk3<= not clk3; end if; end if; end if; end process;end solu;

nota: a manera de ejemplo se simulo con las siguiente moficaciones: if q1= 34 then . if q2=3 then . if q3=1 then .

You might also like