Submitted to : Sir Israr Submitted by:

Safeer Ansar Subject: Computer Organization Assignment No: 1st Titile of Assignment: Introduction to Verilog

Introduction to Verilog
There are two Hardware Descriptive Languages used by integrated circuit(IC) designers.

VHDL Verilog HDl HDLs allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. Now I am starting an introduction to Verilog.

1.Levels of abstraction:Verilog can be used to describe designs at four levels of abstraction: (i) Algorithmic level (much like c code with if, case and loop statements). (ii) Register transfer level (RTL uses registers connected by Boolean equations). (iii) Gate level (interconnected AND, NOR etc.). (iv)Switch level (the switches are MOS transistors inside gates). More recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a netlist) for the circuit. Some Verilog constructs are not synthesizable. Also the way the code is written will greatly affect the size and speed of the synthesized

circuit. Most readers will want to synthesize their circuits, so nonsynthesizable constructs should be used only for test benches. These are program modules used to generate I/O needed to simulate the rest of the design. The words not synthesizable will be used for examples and constructs as needed that do not synthesize.

2.Lexical Token
Verilog source text files consist of the following lexical tokens: 1. White Space White spaces separate words and can contain spaces, tabs, new-lines and form feeds. Thus a statement can extend over multiple lines without special continuation characters. 2. Comments Comments can be specified in two ways (exactly the same way as in C/C++): Begin the comment with double slashes (//). All text between these characters and the end of the line will be ignored by the Verilog compiler. Enclose comments between the characters /* and */. Using this method allows you to continue comments on more than one line. This is good for commenting out many lines code, or for very brief in-line comments. For example Example a = c + d; // this is a simple comment assign x=ABC /* plus its compliment*/ + ABC_

3. Numbers Number storage is defined as a number of bits, but values can be specified in binary, octal, decimal or hexadecimal Examples are 3b001, a 3-bit number, 5d30, (=5b11110), and 16h5ED4, (=16d24276) 4. Identifiers Identifiers are user-defined words for variables, function names, module names, block names and instance names. Identifiers begin with a letter or underscore (Not with a number or $) and can include any number of letters, digits and Underscores. Identifiers in Verilog are case-sensitive. 5. Operators Operators are one, two and sometimes three characters used to perform operations on variables. Arithmetic The list of arithmetic operators supported by Verilog are listed below: + (addition) (subtraction) * (multiplication) / (division) % (modulus) Relational Relational operators compare two operands and return a single bit.

 < (less than) (l h l )<= (less than or equal to) > (greater than) >= (greater than or equal to) == (equal to) != (not equal to) Bitwise Bitwise operators carry out a bit by bit comparison of two operands. ~ (bitwise NOT) & (bitwise AND) | (bitwise OR) | (bit wise OR) ^ (bitwise XOR) Logical Logical operators return a single bit. They can work on expressions, Integers, and groups of bits. If any of the bits in the operand are non zero then it is treated as a logic 1. Logic operators are typically used with if else statements. ! (Logical NOT) && (Logical AND) || (Logical OR) Reduction Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the unary (one argument) form of the bit-wise Operators

 & (reduction AND) | (reduction OR) ~& (reduction NAND) ~| (reduction NOR) ^ (reduction XOR) ~^ or ^~ (reduction XNOR) Shift Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension). << (shift left) >> (shift right) concatenation operator The concatenation operator combines two or more operands to form a larger vector. { }(concatenation) Replication Operator The replication operator makes multiple copies of an item. {n{item}} (n fold replication of an item) Conditional Operator Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a condition. It will synthesize to a multiplexer (MUX). (Condition)? (result if condition true): (result if condition false)

6. Verilog Keywords These are words that have special meaning in Verilog. Some examples are assign, case, while, wire, reg, and, or, nand, and module. They should not be used as identifiers. A number of them will be introduced in this manual. Verilog keywords also include Compiler Directives and System Tasks and Functions.

3.Gate Level Modeling

Primitive logic gates are part of the Verilog language. Two properties can be specified, drive strength and delay.Drive_strength specifies the strength at the gate outputs. The strongest output is a direct connection to a source, next comes a connection through a conducting transistor, then a resistive pull-up/down. The drive strength is usually not specified, in which case the strengths defaults to strong1 and strong0. Refer to Cadence Verilog-XL Reference Manual for more details on strengths. Delays: If no delay is specified, then the gate has no propagation delay; if two delays are specified, the first represent the rise delay, the second the fall delay; if only one delay is specified, then rise and fall are equal.

Delays are ignored in synthesis. The parameters for the primitive gates have been predefined as delays. Basic Gates These implement the basic logic gates. They have one output and one or more inputs. In the gate instantiation syntax shown below, GATE stands for one of the keywords and, nand, or, nor, xor, xnor. Syntax GATE (drive_strength) # (delays) instance_name1(output, input_1, input_2,..., input_N), instance_name2 (output, in1, in2... inN); Delays is # (rise, fall) or # rise_and_fall # (rise_and_fall)
Example

or

and c1 (o, a, b, c, d); // 4-input AND called c1 and

c2 (p, f g); // a 2-input AND called c2.

or #(4, 3) ig (o, a, b); /* or gate called ig (instance name); rise time = 4, fall time = 3 */ xor #(5) xor1 (a, b, c); // a = b XOR c after 5 time units xor (pull1, strong0) #5 (a,b,c); /* Identical gate with pull-up

 Buffer, not Gates These implement buffers and inverters, respectively. They have one input and one or more outputs. In the gate instan-tiation syntax shown below, GATE stands for either the keyword buf or not Syntax GATE (drive_strength) # (delays) instance_name1(output_1, output_2, ..., output_n, input), instance_name2 (out1, out2, ..., outN, in);
Example not #(5) not_1 (a, c); // a = NOT c after 5 time units buf c1 (o, p, q, r, in); // 5-output and 2-output buffers c2 (p, f g);

Three-State Gates; bufif1, bufif0, notif1, notif0 These implement 3-state buffers and inverters. They propagate z (3state or high-impedance) if their control signal is deasserted. These can have three delay specifications: a rise time, a fall time, and a time to go into 3-state.

4.Data Types
1. Value Set

Verilog consists of only four basic values. Almost all Verilog data types store all these values: 0 (logic zero, or false condition) 1 (logic one, or true condition) x (unknown logic value) z (high impedance state) 2.Wire A wire represents a physical wire in a circuit and is used to connect gates or modules. The value of a wire can be read, but not assigned to, in a function or block. A wire does not store its value but must be driven by a continuous assignment statement or by connecting it to the output of a gate or module. Other specific types of wires include: wand (wired-AND;):the value of a wand depend on logical AND of all the drivers connected to it. wor (wired-OR ;): the value of a wor depend on logical OR of all the drivers connected to it. tri (three-state;): all drivers connected to a tri must be z, except one (which determines the value of the tri) Syntax wire [msb:lsb] wire_variable_list; wand [msb:lsb] wand_variable_list; wor [msb:lsb] wor_variable_list; x and z have limited use for synthesis.

tri [msb:lsb] tri_variable_list; 3.Reg A reg (register) is a data object that holds its value from one procedural assignment to the next. They are used only in functions and procedural blocks. See Wire on p. 4 above. A reg is a Verilog variable type and does not necessarily imply a physical register. In multi-bit registers, data is stored as unsigned numbers and no sign extension is done for what the user might have thought were twos complement numbers. Syntax reg [msb:lsb] reg_variable_list; 4.Input, Output, Inout These keywords declare input, output and bidirectional ports of a module or task. Input and inout ports are of type wire. An output port can be configured to be of type wire, reg, wand, wor or tri. The default is wire. Syntax input [msb:lsb] input_port_list; output [msb:lsb] output_port_list; inout [msb:lsb] inout_port_list; 5.Integer Integers are general-purpose variables. For synthesois they are used mainly loops-indicies, parameters, and con-stants. They are of implicitly of type reg. However they store data as signed numbers

whereas explicitly declared reg types store them as unsigned. If they hold numbers which are not defined at compile time, their size will default to 32-bits. If they hold constants, the synthesizer adjusts them to the minimum width needed at compilation. Syntax integer integer_variable_list; ... integer_constant ... ; 6.Parameters A parameter defines a constant that can be set when you instantiate a module. This allows customization of a module during instantiation. Syntax parameter par_1 = value, par_2 = value, .....; parameter [range] parm_3 = value

5.Behavioral Modeling
Verilog has four levels of modelling: 1) The switch level which includes MOS transistors modelled as switches. 2) The gate level. 3) The Data-Flow level. 4) The Behavioral or procedural level described below.

Verilog procedural statements are used to model a design at a higher level of abstraction than the other levels. They provide powerful ways of doing complex designs. However small changes n coding methods can cause large changes in the hardware generated. Procedural statements can only be used in procedures. 1.Procedural Assignments Procedural assignments are assignment statements used within Verilog procedures (always and initial blocks). Only reg variables and integers (and their bit/part-selects and concatenations) can be placed left of the = in procedures.The right hand side of the assignment is an expression which may use any of the operator types. 2.Delay in Assignment (not for synthesis) In a delayed assignment Dt time units pass before the statement is executed and the left-hand assignment is made.With intra-assignment delay, the right side is evaluated immediately but there is a delay of Dt before the result is place in the left hand assignment. If another procedure changes a right-hand side signal during Dt, it does not effect the output. Delays are not supported by synthesis tools. Syntax for Procedural Assignment variable = expression Delayed assignment #Dt variable = expression; Intra-assignment delay variable = #Dt expression;

3.Blocking Assignments Procedural (blocking) assignments (=) are done sequentially in the order the statements are written. A second assignment is not started until the preceding one is complete. Syntax Blocking variable = expression; variable = #Dt expression; grab inputs now, deliver ans later. #Dt variable = expression; grab inputs later, deliver ans later 4.Nonblocking (RTL) Assignments RTL (nonblocking) assignments (<=), which follow each other in the code, are done in parallel. The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure. The transfer to the left hand side is made according to the delays. A delay in a nonblocking statement will not delay the start of any subsequent statement blocking or non-blocking. A good habit is to use <= if the same variable appears on both sides of the equal sign .

5. begin ... end Begin ... end block statements are used to group several statements for use where one statement is syntactically allowed. Such places include functions, always and initial blocks, if, case and for statements. Blocks can optionally be named. One must not mix <= or = in the same procedure. <= best mimics what physical flip-flops do; use it for always @ (posedge clk ..) type procedures. = best corresponds to what c/c++ code would do; use it for combinational procedures Syntax begin : block_name reg [msb:lsb] reg_variable_list; integer [msb:lsb] integer_list; parameter [msb:lsb] parameter_list; ... statements ... end

6.For loops Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of statements. If the loop con-tains only one statement, the begin ... end statements may be omitted. Syntax for (count = value1; count </<=/>/>= value2; count = count +/- step) begin ... statements ... End 7.While Loops The while loop repeatedly executes a statement or block of statements until the expression in the while statement evaluates to false. To avoid combinational feedback during synthesis, a while loop must be broken with an @(posedge/negedge clock) statement . For simulation a delay inside the loop will suffice. If the loop contains only one statement, the begin ... end statements may be omitted. Syntax while (expression) begin ... statements ...end

8.Forever Loops The forever statement executes an infinite loop of a statement or block of statements. To avoid combinational feedback during synthesis, a forever loop must be broken with an @(posedge/negedge clock) statement . For simulation a delay inside the loop will suffice. If the loop contains only one statement, the begin ... end statements may be omitted. It is Syntax forever begin ... statements . end 9.Repeat The repeat statement executes a statement or block of statements a fixed number of times. Syntax repeat (number_of_times) begin ... statements ... end

10.Case statement The case statement allows a multipath branch based on comparing the expression with a list of case choices.Statements in the default block executes when none of the case choice comparisons are true (similar to the else block in the if ... else if ... else). If no comparisons , including delault, are true, synthesizers will generate unwanted latches Good practice says to make a habit of puting in a default whether you need it or not. If the defaults are dont cares, define them as x and the logic minimizer will treat them as dont cares.Case choices may be a simple constant or expression, or a comma-separated list of same. Syntax case (expression) case_choice1: begin ... statements ... end case_choice2: begin ... statements ... end ... more case choices blocks ...

default: begin ... statements ... end endcase