//////////////////////////////////////////////////////////////////////////////////

//SQUARE ROOT CALCULATIONG PROGRAM

//combinational circuit of square root
module SQUAREROOTLELO(outsquare,insquare
);
input [0:5] insquare;
output [0:2] outsquare;
assign outsquare[0]=(insquare[2] & insquare[3]) | insquare[1];
assign outsquare[1]=((~insquare[1]) & (insquare[2] ^ insquare[3]));
assign outsquare[2]=(insquare[5] | insquare[4]) & (((~insquare[1]) & (~(insquare[1]^insquare[3]))) |
(insquare[2] & insquare[1]));
endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////////
//p encoder
//8bit p encoder
module p_encoder8to3(outp,eout,inp,ein
);
input [0:7] inp;
input ein;
output [0:2] outp;
output eout;
assign outp[0]=ein & (inp[3] | inp[2] | inp[1] | inp[0]);
assign outp[1]=ein & ((inp[5] & (~inp[3]) & (~inp[2])) | (inp[4] & (~inp[3]) & (~inp[2])) |inp[1] | inp[0]);
assign outp[2]=ein & ((inp[6] & ~inp[5] & ~inp[3] & ~inp[1]) | (inp[4] & ~inp[3] & ~inp[1]) | (inp[2] &
~inp[1]) | inp[0] );
assign eout=ein & ~inp[0] & ~inp[1] & ~inp[2] & ~inp[3] & ~inp[4] & ~inp[5] & ~inp[6] & ~inp[7];
endmodule

//32 BIT P_ENCODER USING 4 8BIT P_ENCODER

////////////////////////////////////////////////////////////////////////////////////////////////////////
module p_encoder32to5(outpt,inpt);
input [0:31] inpt;
output [0:4] outpt;
wire [0:2] peo1,peo2,peo3,peo4;
wire eout1,eout2,eout3,eout4;
assign eout4=1;
p_encoder8to3 pe1 (peo1,,inpt[24:31],eout1);
p_encoder8to3 pe2 (peo2,eout1,inpt[16:23],eout2);
p_encoder8to3 pe3 (peo3,eout2,inpt[8:15],eout3);
p_encoder8to3 pe4 (peo4,eout3,inpt[0:7],eout4);
assign outpt[4]=peo1[2] | peo2[2] | peo3[2] | peo4[2];
assign outpt[3]=peo1[1] | peo2[1] | peo3[1] | peo4[1];
assign outpt[2]=peo1[0] | peo2[0] | peo3[0] | peo4[0];
assign outpt[1]= (~eout1) & ~(eout2 ^ eout3);
assign outpt[0]= (~eout1) & (~eout2);
endmodule

/////////////////////////////////////////////////////////////////////////////////////////////////////////////
//APPROX LOG CALCULATING ALGO USING P_ENCODER
//LOG CALCULATING PROGRAM
module LOGLELO(outlog,inlog
);
input [0:31] inlog;
output [0:5] outlog;
wire [0:4] outpet;
p_encoder32to5 pe32 (outpet,inlog);
assign outlog=44-7*outpet/5;

endmodule

//////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////
//SINE WAVE GENERATOR
module SINELELO(outs,signs,ins);
input [0:31] ins;
output [0:31] outs;
output signs;
//wire declaration
wire [0:32] tmp;
wire [0:31] twos1,twos2,ready;
wire [0:31] outs,ins;
wire [0:34] tmp1,ans;
wire [0:67] tmp2;
wire p;
assign tmp[0]=(ins[0] & ins[1]);
assign tmp[1]=((~ins[0]) | ins[1]);
assign tmp[2:32] =0;
assign signs=((ins[0] & ins[1]) |(ins[0] & (~ins[1])));
twocmp tws1 (twos1,ins,((ins[0] & ins[1])|((~ins[0]) & ins[1])));
assign twos2[0]=(((~ins[0])| (ins[1])) & twos1[0]);
assign twos2[1:31]=twos1[1:31];
assign ready=tmp+twos2;
assign tmp1=7*ready;
assign tmp2=12*ready*ready;
assign ans=tmp1-tmp2[1:35];
assign p=ready[0]| ready[2]| ready[3]| ready[4]| ready[5]| ready[6]| ready[7]| ready[8]|
ready[9]|ready[10]|ready[11]|ready[12]|ready[13]|ready[14]|ready[15]|ready[16]|ready[17];

assign outs[1:31]=ans[2:33];
assign outs[0]=((~p)& ready[1]);
//first bit of out put id integer and other 31 bit if float
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
COS
//COS CALCULATING PROGRAM , USING POLYNOMIAL METHOD
module COSLELO(cosout,sign,in
);
input [0:31] in;
output [0:31] cosout;
output sign;
wire [0:32] q;
wire [0:31] in1,in2;
wire [0:31] cosout;
wire [0:63] a;
wire [0:127] b;
wire [0:191] c;
wire [0:255] d;
assign sign=in[0];
assign in2[0]=in[0];
assign in2[1]=in[0];
assign in2[2]=in[0];
assign in2[3]=in[0];
assign in2[4]=in[0];
assign in2[5]=in[0];
assign in2[6]=in[0];
assign in2[7]=in[0];
assign in2[8]=in[0];

assign in2[9]=in[0];
assign in2[10]=in[0];
assign in2[11]=in[0];
assign in2[12]=in[0];
assign in2[13]=in[0];
assign in2[14]=in[0];
assign in2[15]=in[0];
assign in2[16]=in[0];
assign in2[17]=in[0];
assign in2[18]=in[0];
assign in2[19]=in[0];
assign in2[20]=in[0];
assign in2[21]=in[0];
assign in2[22]=in[0];
assign in2[23]=in[0];
assign in2[24]=in[0];
assign in2[25]=in[0];
assign in2[26]=in[0];
assign in2[27]=in[0];
assign in2[28]=in[0];
assign in2[29]=in[0];
assign in2[30]=in[0];
assign in2[31]=in[0];
assign in1[0:31]=(32'h80000000 & in2)+((in[0:31] & 32'h7fffffff)^in2)+in[0];
assign a=in1*in1*5;
assign b=in1*in1*in1*in1*4;
assign c=in1*in1*in1*in1*in1*in1*4/3;
assign d=in1*in1*in1*in1*in1*in1*in1*in1/4;
assign q=33'h100000000;

assign cosout=q-a[0:31]+b[0:31]-c[0:31]+d[0:31];
endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////
//2X1 MUX
module mux2x1(outm,in1m,in2m,sm);
output [0:31] outm;
input sm;
input [0:31] in1m,in2m;
wire [0:31] in1m,in2m,outm;
wire sm,smb;
assign smb=~sm;
assign outm[0]= (in1m[0] & smb )|(in2m[0] & sm);
assign outm[1]= (in1m[1] & smb )|(in2m[1] & sm);
assign outm[2]= (in1m[2] & smb )|(in2m[2] & sm);
assign outm[3]= (in1m[3] & smb )|(in2m[3] & sm);
assign outm[4]= (in1m[4] & smb )|(in2m[4] & sm);
assign outm[5]= (in1m[5] & smb )|(in2m[5] & sm);
assign outm[6]= (in1m[6] & smb )|(in2m[6] & sm);
assign outm[7]= (in1m[7] & smb )|(in2m[7] & sm);
assign outm[8]= (in1m[8] & smb )|(in2m[8] & sm);
assign outm[9]= (in1m[9] & smb )|(in2m[9] & sm);
assign outm[10]= (in1m[10] & smb )|(in2m[10] & sm);
assign outm[11]= (in1m[11] & smb )|(in2m[11] & sm);
assign outm[12]= (in1m[12] & smb )|(in2m[12] & sm);
assign outm[13]= (in1m[13] & smb )|(in2m[13] & sm);
assign outm[14]= (in1m[14] & smb )|(in2m[14] & sm);
assign outm[15]= (in1m[15] & smb )|(in2m[15] & sm);
assign outm[16]= (in1m[16] & smb )|(in2m[16] & sm);

assign outm[17]= (in1m[17] & smb )|(in2m[17] & sm);

assign outm[18]= (in1m[18] & smb )|(in2m[18] & sm);
assign outm[19]= (in1m[19] & smb )|(in2m[19] & sm);
assign outm[20]= (in1m[20] & smb )|(in2m[20] & sm);
assign outm[21]= (in1m[21] & smb )|(in2m[21] & sm);
assign outm[22]= (in1m[22] & smb )|(in2m[22] & sm);
assign outm[23]= (in1m[23] & smb )|(in2m[23] & sm);
assign outm[24]= (in1m[24] & smb )|(in2m[24] & sm);
assign outm[25]= (in1m[25] & smb )|(in2m[25] & sm);
assign outm[26]= (in1m[26] & smb )|(in2m[26] & sm);
assign outm[27]= (in1m[27] & smb )|(in2m[27] & sm);
assign outm[28]= (in1m[28] & smb )|(in2m[28] & sm);
assign outm[29]= (in1m[29] & smb )|(in2m[29] & sm);
assign outm[30]= (in1m[30] & smb )|(in2m[30] & sm);
assign outm[31]= (in1m[31] & smb )|(in2m[31] & sm);
endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////
//SIMPLE D FLIP FLOP WITH INITIAL CONDITION 1
module flipflop1(qff,dff,resetff,setff,clkff);
input clkff,dff,resetff,setff;
output qff;
reg qff;
initial
begin
qff=1;
end
always @(posedge clkff or posedge resetff or posedge setff)

begin
if (setff)
qff=1;
else if(resetff)
qff=0;
else
qff=dff;
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////
///SIMPLE D FLIP FLOP WITH INITIAL CONDITION 0
module flipflop0(qff,dff,resetff,setff,clkff);
input clkff,dff,resetff,setff;
output qff;
reg qff;
initial
begin
qff=0;
end
always @(posedge clkff or posedge resetff or posedge setff)
begin
if (setff)
qff=1;
else if(resetff)
qff=0;
else
qff=dff;
end
endmodule

// FIRST LSFR
///////////////////////////////////////////////////////////////////////////////////////////////////////
//USING 43 FF,AND SELECT 32 BIT IN 43
module LSFRone(outlsfr,resetlsfr,clklsfr);
input clklsfr,resetlsfr;
output [0:31] outlsfr;
wire [0:31] outlsfr;
wire [0:5] uga;
wire setlsfr;
assign setlsfr=0;
xor (uga[0],outlsfr[0],outlsfr[31]);
xor (uga[1],outlsfr[0],outlsfr[30]);
xor (uga[2],outlsfr[0],outlsfr[29]);
xor (uga[3],outlsfr[0],outlsfr[28]);
xor (uga[4],outlsfr[0],outlsfr[27]);
xor (uga[5],outlsfr[0],outlsfr[26]);
flipflop0 ff1 (outlsfr[0],outlsfr[1],resetlsfr,setlsfr,clklsfr);
flipflop0 ff2 (outlsfr[1],outlsfr[2],resetlsfr,setlsfr,clklsfr);
flipflop0 ff3 (outlsfr[2],outlsfr[3],resetlsfr,setlsfr,clklsfr);
flipflop0 ff4 (outlsfr[3],outlsfr[4],resetlsfr,setlsfr,clklsfr);
flipflop0 ff5 (outlsfr[4],outlsfr[5],resetlsfr,setlsfr,clklsfr);
flipflop0 ff6 (outlsfr[5],outlsfr[6],resetlsfr,setlsfr,clklsfr);
flipflop1 ff7 (outlsfr[6],outlsfr[7],setlsfr,resetlsfr,clklsfr);
flipflop0 ff8 (outlsfr[7],outlsfr[8],resetlsfr,resetlsfr,clklsfr);
flipflop0 ff9 (outlsfr[8],outlsfr[9],resetlsfr,resetlsfr,clklsfr);
flipflop0 ff10 (outlsfr[9],outlsfr[10],resetlsfr,resetlsfr,clklsfr);
flipflop0 ff11 (outlsfr[10],outlsfr[11],resetlsfr,setlsfr,clklsfr);
flipflop0 ff12 (outlsfr[11],outlsfr[12],resetlsfr,setlsfr,clklsfr);
flipflop0 ff13 (outlsfr[12],outlsfr[13],resetlsfr,setlsfr,clklsfr);

flipflop1 ff14 (outlsfr[13],outlsfr[14],setlsfr,resetlsfr,clklsfr);

flipflop0 ff15 (outlsfr[14],outlsfr[15],resetlsfr,setlsfr,clklsfr);
flipflop0 ff16 (outlsfr[15],outlsfr[16],resetlsfr,setlsfr,clklsfr);
flipflop0 ff17 (outlsfr[16],outlsfr[17],resetlsfr,setlsfr,clklsfr);
flipflop0 ff18 (outlsfr[17],outlsfr[18],resetlsfr,setlsfr,clklsfr);
flipflop0 ff19 (outlsfr[18],outlsfr[19],resetlsfr,setlsfr,clklsfr);
flipflop1 ff20 (outlsfr[19],outlsfr[20],setlsfr,resetlsfr,clklsfr);
flipflop0 ff21 (outlsfr[20],outlsfr[21],resetlsfr,setlsfr,clklsfr);
flipflop0 ff22 (outlsfr[21],outlsfr[22],resetlsfr,setlsfr,clklsfr);
flipflop0 ff23 (outlsfr[22],outlsfr[23],resetlsfr,setlsfr,clklsfr);
flipflop0 ff24 (outlsfr[23],outlsfr[24],resetlsfr,setlsfr,clklsfr);
flipflop0 ff25 (outlsfr[24],outlsfr[25],resetlsfr,setlsfr,clklsfr);
flipflop0 ff26 (outlsfr[25],outlsfr[26],resetlsfr,setlsfr,clklsfr);
flipflop0 ff27 (outlsfr[26],outlsfr[27],resetlsfr,setlsfr,clklsfr);
flipflop0 ff28 (outlsfr[27],uga[3],resetlsfr,setlsfr,clklsfr);
flipflop0 ff29 (outlsfr[28],uga[2],resetlsfr,setlsfr,clklsfr);
flipflop0 ff30 (outlsfr[29],uga[1],resetlsfr,setlsfr,clklsfr);
flipflop1 ff31 (outlsfr[30],uga[0],resetlsfr,setlsfr,clklsfr);
flipflop0 ff32 (outlsfr[31],outlsfr[0],resetlsfr,setlsfr,clklsfr);

endmodule

//////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////
// SECOND LSFR
///////////////////////////////////////////////////////////////////////////////////////////////////////
//USING 43 FF, SELECT 32 BIT IN 43;
module LSFRtwo(outlsfr,resetlsfr,clklsfr);
input clklsfr,resetlsfr;

output [0:31] outlsfr;

wire [0:31] outlsfr;
wire [0:5] uga2;
wire setlsfr;
assign setlsfr=0;
xor (uga2[0],outlsfr[0],outlsfr[31]);
xor (uga2[1],outlsfr[0],outlsfr[30]);
xor (uga2[2],outlsfr[0],outlsfr[29]);
xor (uga2[3],outlsfr[0],outlsfr[28]);
xor (uga2[4],outlsfr[0],outlsfr[27]);
xor (uga2[5],outlsfr[0],outlsfr[26]);
flipflop0 ff1 (outlsfr[0],outlsfr[1],resetlsfr,setlsfr,clklsfr);
flipflop0 ff2 (outlsfr[1],outlsfr[2],resetlsfr,setlsfr,clklsfr);
flipflop0 ff3 (outlsfr[2],outlsfr[3],resetlsfr,setlsfr,clklsfr);
flipflop0 ff4 (outlsfr[3],outlsfr[4],resetlsfr,setlsfr,clklsfr);
flipflop0 ff5 (outlsfr[4],outlsfr[5],resetlsfr,setlsfr,clklsfr);
flipflop1 ff6 (outlsfr[5],outlsfr[6],resetlsfr,setlsfr,clklsfr);
flipflop0 ff7 (outlsfr[6],outlsfr[7],setlsfr,resetlsfr,clklsfr);
flipflop0 ff8 (outlsfr[7],outlsfr[8],resetlsfr,resetlsfr,clklsfr);
flipflop0 ff9 (outlsfr[8],outlsfr[9],resetlsfr,resetlsfr,clklsfr);
flipflop0 ff10 (outlsfr[9],outlsfr[10],resetlsfr,resetlsfr,clklsfr);
flipflop0 ff11 (outlsfr[10],outlsfr[11],resetlsfr,setlsfr,clklsfr);
flipflop0 ff12 (outlsfr[11],outlsfr[12],resetlsfr,setlsfr,clklsfr);
flipflop0 ff13 (outlsfr[12],outlsfr[13],resetlsfr,setlsfr,clklsfr);
flipflop1 ff14 (outlsfr[13],outlsfr[14],setlsfr,resetlsfr,clklsfr);
flipflop0 ff15 (outlsfr[14],outlsfr[15],resetlsfr,setlsfr,clklsfr);
flipflop0 ff16 (outlsfr[15],outlsfr[16],resetlsfr,setlsfr,clklsfr);
flipflop0 ff17 (outlsfr[16],outlsfr[17],resetlsfr,setlsfr,clklsfr);
flipflop0 ff18 (outlsfr[17],outlsfr[18],resetlsfr,setlsfr,clklsfr);

flipflop0 ff19 (outlsfr[18],outlsfr[19],resetlsfr,setlsfr,clklsfr);

flipflop0 ff20 (outlsfr[19],outlsfr[20],setlsfr,resetlsfr,clklsfr);
flipflop0 ff21 (outlsfr[20],outlsfr[21],resetlsfr,setlsfr,clklsfr);
flipflop0 ff22 (outlsfr[21],outlsfr[22],resetlsfr,setlsfr,clklsfr);
flipflop0 ff23 (outlsfr[22],outlsfr[23],resetlsfr,setlsfr,clklsfr);
flipflop0 ff24 (outlsfr[23],outlsfr[24],resetlsfr,setlsfr,clklsfr);
flipflop1 ff25 (outlsfr[24],outlsfr[25],resetlsfr,setlsfr,clklsfr);
flipflop0 ff26 (outlsfr[25],outlsfr[26],resetlsfr,setlsfr,clklsfr);
flipflop0 ff27 (outlsfr[26],outlsfr[27],resetlsfr,setlsfr,clklsfr);
flipflop0 ff28 (outlsfr[27],uga2[3],resetlsfr,setlsfr,clklsfr);
flipflop0 ff29 (outlsfr[28],uga2[2],resetlsfr,setlsfr,clklsfr);
flipflop0 ff30 (outlsfr[29],uga2[1],resetlsfr,setlsfr,clklsfr);
flipflop1 ff31 (outlsfr[30],uga2[0],resetlsfr,setlsfr,clklsfr);
flipflop0 ff32 (outlsfr[31],outlsfr[0],resetlsfr,setlsfr,clklsfr);

endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
//2'S COMPLEMENT GENERATOR;
module twocmp(outad,inad,scmp);
output [0:31] outad;
input scmp;
input [0:31] inad;
wire [0:31] tmp3;
assign tmp3[0]=scmp ^ inad[0];
assign tmp3[1]=scmp ^ inad[1];
assign tmp3[2]=scmp ^ inad[2];

assign tmp3[3]=scmp ^ inad[3];

assign tmp3[4]=scmp ^ inad[4];
assign tmp3[5]=scmp ^ inad[5];
assign tmp3[6]=scmp ^ inad[6];
assign tmp3[7]=scmp ^ inad[7];
assign tmp3[8]=scmp ^ inad[8];
assign tmp3[9]=scmp ^ inad[9];
assign tmp3[10]=scmp ^ inad[10];
assign tmp3[11]=scmp ^ inad[11];
assign tmp3[12]=scmp ^ inad[12];
assign tmp3[13]=scmp ^ inad[13];
assign tmp3[14]=scmp ^ inad[14];
assign tmp3[15]=scmp ^ inad[15];
assign tmp3[16]=scmp ^ inad[16];
assign tmp3[17]=scmp ^ inad[17];
assign tmp3[18]=scmp ^ inad[18];
assign tmp3[19]=scmp ^ inad[19];
assign tmp3[20]=scmp ^ inad[20];
assign tmp3[21]=scmp ^ inad[21];
assign tmp3[22]=scmp ^ inad[22];
assign tmp3[23]=scmp ^ inad[23];
assign tmp3[24]=scmp ^ inad[24];
assign tmp3[25]=scmp ^ inad[25];
assign tmp3[26]=scmp ^ inad[26];
assign tmp3[27]=scmp ^ inad[27];
assign tmp3[28]=scmp ^ inad[28];
assign tmp3[29]=scmp ^ inad[29];
assign tmp3[30]=scmp ^ inad[30];
assign tmp3[31]=scmp ^ inad[31];

assign outad=tmp3+scmp;
endmodule

////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////
//REGISTERS USER IN PIPELINE STRUCTURE
////////////////////////////////////////////////////////////////////////////////////////////////////////////
//1st PART REGISTERS
module part1reg(lsfrout1,lsfrout2,resetr1,clkr1);
output [0:31] lsfrout1,lsfrout2;
input clkr1,resetr1;
reg [0:31] lsfrout1,lsfrout2;
wire [0:31] lsfrr1,lsfrr2;
wire clkh;
initial
begin
lsfrout1=0;
lsfrout2=0;
end
assign # 0.008 clkh=clkr1;
LSFRone L1 (lsfrr1,resetr1,clkr1);
LSFRtwo L2 (lsfrr2,resetr1,clkr1);
always @ (posedge clkh)
begin
lsfrout1<=lsfrr1;
lsfrout2<=lsfrr2;
end
endmodule
////////////////////////////////////////

//2nd PART PEGISTERS

module part2reg(sqwout,cosout,sinout,csign,ssign,lsfrr21,lsfrr22,clkr2);
input [0:31] lsfrr22,lsfrr21;
output [0:31] cosout;
output [0:31] sinout;
output csign,ssign;
output [0:2] sqwout;
input clkr2;
reg [0:31] cosout;
reg [0:31] sinout;
reg [0:2] sqwout;
reg csign,ssign;
wire [0:2] sqw;
wire [0:5] logw;
wire [0:31] cosr,lsfrr22,lsfrr21;
wire [0:31] sinr;
wire csign1,ssign1,clkh2;
initial
begin
csign=0;
ssign=0;
sqwout=0;
cosout=0;
sinout=0;
end
COSLELO C1 (cosr,csign1,lsfrr21);
SINELELO S1 (sinr,ssign1,lsfrr21);
LOGLELO LO1 (logw,lsfrr22);
SQUAREROOTLELO SQ1 (sqw,logw);

assign # 0.004 clkh2=clkr2;

always @ (posedge clkh2)
begin
sqwout<=sqw;
cosout<=cosr;
sinout<=sinr;
csign<=csign1;
ssign<=ssign1;
end
endmodule
///////////////////////////////////////////////////////////////////////////////
//3rd PART REGISTERS
module part3reg(grngc,csign,grngs,ssign,sd,cosinr3,sininr3,csignr3,ssignr3,sqwr3,clkr3);
input [0:31] cosinr3,sd;
input [0:31] sininr3;
input [0:2] sqwr3;
input clkr3,csignr3,ssignr3;
output [0:31] grngc,grngs;
output csign,ssign;
reg [0:31] grngc,grngs;
reg csign,ssign;
wire [0:34] multi;
wire [0:34] multis;
wire [0:14] multi2,multis2;
wire [0:66] xsd,xsds;
wire [0:31] xsd32,xsd32s;
wire clkh3;
initial
begin

grngc=0;
grngs=0;
csign=0;
ssign=0;
end
assign # 0.002 clkh3=clkr3;
assign multi=sqwr3*cosinr3;
assign multis=sqwr3*sininr3;
assign multi2=multi[1:15];
assign multis2=multis[2:16];
assign xsd=multi2*sd;
assign xsds=multis2*sd;
assign xsd32=xsd[22:53];
assign xsd32s=xsds[22:53];
always @ (posedge clkh3)
begin
grngc<=xsd32;
grngs<=xsd32s;
csign<=csignr3;
ssign<=ssignr3;
end
endmodule
///////////////////////////////////////////////////////////////////////
//4th part of pipeline
module part4reg (grnga1,g1sign,grnga2,g2sign,mean,xsdrc,xsdrs,csign,ssign,clkr4);
input [0:31] xsdrc,xsdrs,mean;
input clkr4,csign,ssign;
output [0:31] grnga1,grnga2;
output g1sign,g2sign;

reg [0:31] grnga1,grnga2;

reg g1sign,g2sign;
wire [0:34] cmp,cmps;
wire [0:31] mean2,mean2s,xsd2,xsd2s,outgc,outgs;
wire clkh4;
initial
begin
grnga1=0;
grnga2=0;
g1sign=0;
g2sign=0;
end
assign # 0.001 clkh4=clkr4;
assign cmp=mean-xsdrc;
assign cmps=mean-xsdrs;
assign signgc=(csign & cmp[0]);
assign signgs=(ssign & cmps[0]);
twocmp tw1 (mean2,mean,signgc);
twocmp tw2 (xsd2,xsdrc,(csign & (~cmp[0])));
twocmp tw3 (mean2s,mean,signgs);
twocmp tw4 (xsd2s,xsdrs,(ssign & (~cmps[0])));
assign outgc=mean2+xsd2;
assign outgs=mean2s+xsd2s;
always @ (posedge clkh4)
begin

grnga1<=outgc;
grnga2<=outgs;
g1sign<=signgc;

g2sign<=signgs;
end
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////
///////
//5th part of pipeline
module part5reg (grngoutr5,gsign,g1rng,g2rng,g1sign,g2sign,mean,clkr5);
input [0:31] g1rng,g2rng,mean;
input g1sign,g2sign,clkr5;
output [0:31] grngoutr5;
output gsign;
wire [0:32] cmp1;//cmp2;
wire tmpsign;
wire [0:31] tmp;
reg [0:31] grngoutr5;
reg gsign;
initial
begin
gsign=0;
grngoutr5=0;
end
assign cmp1=g1rng-g2rng;
//assign cmp2=g2rng-mean;
mux2x1 m1 (tmp,g1rng,g2rng,(~cmp1[0]));
assign tmpsign=((~cmp1[0]) & g2sign) | (cmp1[0] & g1sign);
always @ (posedge clkr5)
begin
grngoutr5<=tmp;
gsign<=tmpsign;

end
endmodule
//GAUSSION RANDOM NUMBER
GENERATOR////////////////////////////////////////////////////////////////////////
/////////////////////USING BOX MULLER METHOD
/////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
module NEWGRNG(/*g1rng,g2rng,g1sign,g2sign,*/grngoutq,gsignq,numberofterm,mean,sd,resetg,clkg);
//output [0:31] g1rng,g2rng;
//output g1sign,g2sign;
//if g1sign=0 => number is +ve,
//if g2sign=1 => number is -ve,
//sd=standard deviation
output [0:31] grngoutq;
output gsignq;
input clkg,resetg;
input [0:31] mean,sd,numberofterm;
integer fp;
reg [0:31] number;
wire [0:31] lsfrp1,lsfrp2,cosh,grngch,grngsh;
wire [0:31] sinh;
wire [0:2] sqwh;
wire csignh,ssignh,signch,signsh,g1sign,g2sign,gsignq;
wire [0:31] g1rng,g2rng,grngoutq;
initial
begin
fp=$fopen("getval.txt","w");
number=0;
end

//First Stage of pipeline

//Generation of uniform random numbers
part1reg pr1 (lsfrp1,lsfrp2,resetg,clkg);
//Second stage of pipeline
//Apply BOX MULLER TRANSFORMATION calculate cos,sin,log,squarw root
part2reg pr2 (sqwh,cosh,sinh,csignh,ssignh,lsfrp1,lsfrp2,clkg);
//third stage of pipeline
//Multiplication of cos,sin unit to square root unit, and change sd
part3reg pr3 (grngch,signch,grngsh,signsh,sd,cosh,sinh,csignh,ssignh,sqwh,clkg);
//fourth stage of pipeline
//Change mean of the system
part4reg pr4 (g1rng,g1sign,g2rng,g2sign,mean,grngch,grngsh,signch,signsh,clkg);
//fifth stage of pipeline
//selection of best GRN
part5reg pr5 (grngoutq,gsignq,g1rng,g2rng,g1sign,g2sign,mean,clkg);
always @ (posedge clkg)
begin
if((numberofterm+3) ==number)
begin
$fclose(fp);
$finish;
end
if (number==0)
begin
$fwrite(fp,"%x\n%x\n",mean,sd);
end
if(number > 2)
begin
$fwrite(fp,"%x\n%x\n",gsignq,grngoutq);

//$fwrite(fp,"%x\n%x\n",g1sign,g1rng);
//$fwrite(fp,"%x\n%x\n",g2sign,g2rng);
end
number=number+1;
end
endmodule