CHAPTER 3

T 17 TRANSMISSION MODES
3.1 Asynchronous Transmission:
This method of transmission is primarily used when the data to be transmitted are generated at random intervals e.g., by a user at a VDU communicating with a computer. Clearly, with this type of communication, the user keys in each character at an indeterminate rate, with possibly long random time intervals between each successive typed character. This means that the Signal on the transmission line will be in the idle (off) state for long time intervals. With this type of communication, therefore, it is necessary for the receiver to be able to resynchronize at the start of each new character received. To accomplish this, each transmitted character, or more generally, item of user data, is encapsulated, or framed between an additional start bit and one or more stop bits. As can be seen, the polarity of start and stop bits are different. This ensures that there is always a minimum of one transition (1-0-1) between each successive character, irrespective of the bit sequences in the characters being transmitted. The first 1-0 transition after an idle period is then used by the receiving device to determine the start or each new character. In addition, by utilizing a clock whose frequency is N times higher than the transmitted bit rate frequency (N=16 is typical) the receiving device can reliably determine the state of each transmitted bit in the character by sampling the receiving signal approx. at the centre of each bit cell period. It can be deduced from the foregoing that to transmit each item of user data, 10(one start bit and one stop bit) or possibly 11 (one start bit and two stop bits) bits are utilized. Thus assuming a single start bit and two stop bits per 8 bit item and a data transmission rate of, say 1200 Bps, the data rate is 1200/11 or approx 110 bytes/Sec. The useful data rate is, in fact, less that this for reason better described later. When defining the transmission rate of a line, the term baud is often used. When correctly used, however, the term baud indicates the number of line signal transitions per second. Thus, if each transmitted signal can be in one of the two states, the term baud and bps are equivalent. But, in some instances the line signal can take on more than two states, and hence each transmitted cell can be used to convey more than a single binary digit information. To avoid confusion therefore, the term signalling rate is used to define the number of line signal transitions per second (in band) while the data or information transfer rate represents the number of information bits/sec(bps). For example, a 300 baud signal with four bits per signalling element would yield an information rate of 1200 bps. The most common information rates in use on asynchronous lines are 110, 300, 1200, 2400, 4800, 9600 and 19200 bps.

3.2

Synchronous Transmission:

Asynchronous transmission is normally used when the rate at which characters are generated is indeterminate, and hence the transmission line can be idle for long

periods between each transmitted character. The use of additional bits per character for framing purposes is therefore not important. In many applications, however, - for example, for computer to computer communication therefore is often need to transmit a large block of data that has already been preassembled ready for transmission-the contents of a disk file, for example. Clearly, the use of additional framing bits per character then becomes wasteful. Also, because of the clock synchronization mechanism used with an synchronous scheme, that type of transmission can only be used reliably at upto 19200 bps. An alternative and indeed a more efficient approach for the transmission of complete blocks of data is to transmit each complete block (or frame) as a single entity. Using synchronous transmission, the complete block or frame of data is transmitted as a single bit stream with no delay between each 8-bit element. To enable the receiving device to achieve the various levels of synchronization. 1) The transmitted bit stream is suitably encoded so that the receiver can be kept in bit synchronism. 2) All frames are preceded by one or more reserved bytes or characters to ensure the receiver reliably interprets the received bit stream on the correct byte or character boundaries (byte/character synchronization; and 3) The contents of each frame are encapsulated between a pair of reserved bytes or characters. The latter ensures that the receiver, on receipt of the opening byte or character after an idle period, can determine that a new frame is being transmitted and, on receipt of the closing byte or character, that this signals the end of the frame. During the period between the transmission of successive frames, either idle (Sync) bytes or characters are continuously transmitted to allow the received to retain bit and byte synchronism, or each frame is preceded by one or more special synchronizing bytes or characters to allow the receiver to regain synchronism. 3.2.1 Transmission Control Circuits:

Data are normally transmitted between two DTEs bit serially in multiple 8-bit elements using either asynchronous or synchronous transmission. Within the DTEs, however, each element is normally manipulated and stored in a parallel form consequently, the transmission control circuits within each DTE, which form the interface between the device and the Serial data link, must perform the following functions: a) Parallel-to-serial conversion of each element in preparation for transmission of the element on the data link. b) Serial-to-parallel conversion of each received element in preparation for storage and processing of the element in the device. c) A means for the receiver to achieve bit, character and, for synchronous transmission, frame synchronization. d) The generation of suitable error check digits for error detection purposes and the correction of such errors should they occur. 3.3 Universal Asynchronous Receiver and Transmitter (UART):

The interface of user to support asynchronous transmission is known as UART. It is termed universal since it is normally a programmable device and the user can, by simply loading a predefined control word (bit pattern) into the device, specify the required operating characteristics. To use such a device, the mode(control) register is first loaded with the required bit pattern to define the required operating characteristics, this is known as initialization. Typically, the user may select 5,6,7 or 8 bits/character, odd, even or zero parity, one of more stop bits and a range of transmit and receive bit rates. The later are selected from a standard range of 50 bps to 19.2 kbps by connecting a clock source of the appropriate frequency to the transmit and receive clock inputs of the UART and defining the ratio of this clock to the required bit rate (X1, X16, X32 or X64) in the control word. The controlling device within a DTE determines the current state of the UART by reading the contents of the status register and testing specific bits within it. These are often referred to as flag bits. To use this circuit to transmit a new character, the controlling device first reads the status byte to determine the state of the transmit buffer empty (T X BE) bit. Then, assuming this is logical 1 (true), this signals that the previous character has been transferred from the transmit buffer to the transmit register, from where it is shifted bit serially on to the data link. The buffer is now ready for a new character to be loaded. The controlling device thus loads the character, and in turn, the control logic within the UART transfers it to the transmit register as soon as the final stop bit for the previous character has been transmitted. Each time a new character is loaded into the transmit buffer, the T X BE bit is reset to logical 0 (false). Similarly, when the internal control logic transfers a character from the transmit buffer to the transmit register, the T X BE bit is set, thus allowing the control logic to load a new character, if one is available. In addition, when each character is loaded into the transmit buffer, the control logic automatically compute, the appropriate parity bit, if this has been selected. Then, when the complete character (data plus parity) is transferred to the transfer register, a start bit and the specified number of stop bits are inserted and the complete envelope is transmitted bit serially on to the line at a bit rate determined by externally supplied clock and the ratio setting. For reception, the receiving UART must be programmed to operate with the same characteristics as the transmitting DART. When the control logic detects the first transition on the receive data line after are idle period (1---0), due to the possible random intervals between successive characters, the receive timing logic must be resynchronized. This is accomplished by the control logic presetting the contents of a bit rate counter to one-half of the clock rate ratio setting. Thus, if the UART has been programmed to operate with a X16-external clock rate a module 16 counter would be used, present initially to 8 on receipt of the first transition. The timing logic then decrements the counter content after each cycle of the external clock. Since there are 16 clock cycles to each bit cell (X 16 bit rate), the counter will reach zero approximately at the centre of the start bit. The bit rate counter is then present to 16 and hence will reach zero, at the centre of each bit cell period. Each time the counter reaches zero, this triggers the control circuit to determine the current state (logical 1 or 0) of the receive dataline and the appropriate bit is then shifted into the receive register. This process continues until the defined number of data and parity bits have been shifted into the receive register. At this point, the complete character is parallel loaded into the receive buffer. The receive parity bit is then compared with the parity

bit recomputed from the received data bits and, if these are different, the parity error (PE) flag bit is set in the status register at the same time as the receive buffer full (R X BF) flag is set. The controlling device can thus determine the following from these bits:a) b) When a new character has been received, and whether any transmission errors have been detected.

The status register contains two additional error flags namely, the framing and overrun flags. The framing error (FE) flag is set if the control logic determines that a logical 0 (or a valid stop bit) is not present on the receive data line when the last stop bit is expected at the end of a received character. Similarly the overrun error(OE) flag is set if the controlling device has not read the previously received character from the receive buffer before the next character is received and transferred to the buffer. Normally, the setting of these flags does not inhibit the operation of UART but rather signals to the controlling device that in error condition has occurred. It is then up to the controlling device to initiate any corrective action should it deem this to be necessary. As a UART contains both a transmit and receive section, operating in an independent way, it is possible with a single UART to control a full duplex data link. 3.4 Synchronous Transmission: Although the type of framing (character or block) is often used to discriminate between asynchronous and synchronous transmission, the fundamental difference between the two methods is that with asynchronous transmission, the transmitter and receiver clocks are unsynchronized while with synchronous transmission, both clocks are synchronized. Clearly, the latter may be accomplished by having an additional line linking the two equipments, to carry the transmit clock, so that the receiving device, can reliably determine when each new bit is being sent. In practice, however, it is more common to use a single data line with the clock (timing) information embedded, with in the transmitted waveform. With this method, the receiver sampling clock must be extracted from the incoming data stream using a suitable clock extraction circuit. There are two alternative ways of organizing a synchronous data link, character (or byte) oriented and bit oriented. The essential difference between these two methods is in the way the start and end of a frame is determined. With a bit oriented system, it is possible for the receiver to detect the end of a frame at any bit instant and not just on an 8-bit (byte) boundary. This implies that a frame may be N bits in length where N is an arbitrary number. In practice, however, this feature is not often used, since the majority of applications tend to use frames that are multiples of 8-bit bytes. Nevertheless, a bit-oriented system offers the potential of upto two times increase in throughput over a character-oriented system. 3.5 (a) Character Oriented Transmission: With a character oriented scheme, each frame to be transmitted is made up of a variable number of 7 8-bit characters which are transmitted as a continuous string of binary bits with no delay between them. The receiving device, therefore, having achieved clock (bit) synchronism must be able to: a) Detect the start and end of each character-character synchronism

b) Detect the start and end or each complete frame to frame synchronization. A number of schemes have been devised to achieve this, the main aim of which is to make the synchronization process independent of the actual frame contents. This type of synchronization scheme is said to be transparent to the frame contents or simply data transparent. The most common character oriented scheme is that used in the binary synchronous protocol known as Basic Mode: One frame format is shown in Fig. 3.6.(a). The format selected is the one normally used to transmit a block of data as information frame. When using Basic Mode, character synchronization is achieved by the transmitting device sending two or more special synchronizing characters (known as SYN) immediately before each transmitted frame. The receiver at start-up after an idle period, then scans (hunts) the received bit stream one bit at a time until it detects the known pattern of the SYN character. This results in the receiver achieving character synchronism and the subsequent string of binary bits is then treated as a contiguous sequence of 7 or 8 bit characters as defined at set-up time. With the Basic Mode protocol, the SYN character (00010110) is one of the reserved characters from the ISO defined set of character codes. Similarly, the characters used to Signal X the start and end of each frame are from this set as in Fig. 3.6(c). In the example, the start-of-text (STX) character is used to signal the start of a frame and the end-of-text (ETX) character is used to signal the end of a frame. Thus, as each character in the frame is received, following the STX character it is compared with the ETX character. If the character is not an ETX character it is simply stored. If it is an ETX character, however, the frame contents are processed. This scheme is satisfactory provided the data (information) transmitted are made up of strings of printable character entered at a keyboard, for example, since then there is no possibility of an ETX control character being present within the frame contents. Clearly, if the latter did occur, this would cause the receiver to terminate the reception process abnormally. In some applications, however, the frame contents may not be character strings but rather the binary contents of a file, for example. For this type of application, it is necessary to take additional steps to ensure that the end-of-frame termination character is not present within the frame contents; that is, it must be data transparent. To achieve this with a character oriented transmission control scheme, a pair of characters is used both to signal the start of frame and also the end of a frame. A pair of characters is necessary to achieve data transparency; to avoid the abnormal containing the end-of-frame character. Sequence, the transmitter inserts a second datalink escape (DLE) character into the transmitted data stream whenever, it detects a DLE character in the frame contents. This is often referred to as character (or byte) stuffing. The receiver can thus detect the end of a frame by the unique DLE-ETX sequence, and whenever, it receives a DLE character followed by a second DLE, it discards the second character. As has been mentioned, with a frame oriented scheme, transmission errors are normally detected by the use of additional error-detection digits computed from the contents of the frame and transmitted at the end of the frame. To maintain transparency, therefore, the error check characters are transmitted after the closing frame sequence.

3.5 (b) Bit Oriented Transmission: With this scheme, each transmitted frame may contain an arbitrary number of bits which is not necessarily a multiple of 8. As can be seen, the opening and closing flag fields indicating the start and end of the frame are the same (0111 1110). Thus, to achieve data transparency with this scheme, it is necessary to ensure that the flag sequence is not present in the frame contents. This is accomplished by the use of a technique known as Zero-bit insertion or bit stuffing. As the frame contents are transmitted to line, the transmitter detects whenever there is a sequence of five contiguous binary 1 digits and automatically inserts an additional binary 0. Thus, the flag sequence 0111 1110 can never be transmitted between the opening and closing flags. Similarly the receiver, after detecting the opening flag of a frame, monitors the incoming bit stream and, whenever, it detects a binary 0 after five contiguous binary 1s, removes (deletes) it from the frame contents. As with a byte oriented scheme, each frame will normally contain additional error-detection digits at the end of the frame, but the inserted and deleted 0s are not included in the error-detection processing. 3.6 Clock (Bit Synchronization): With asynchronous transmission, a separate clock is utilized at the receiver whose frequency is typically several times higher than the transmitted bit rate. Then on receipt of the leading edge of the start bit of each character envelope, the receiver uses this, together with its local clock, to estimate the centre of each bit cell period. This approach is acceptable for asynchronous transmission since. a) The maximum bit rate used with an asynchronous scheme is relatively low (19.2 Kbps) b) The encoding method ensures that there is a guaranteed synchronizing edge at the start of each character. With synchronous transmission however, start and stop bits are not used. Instead, each frame is transmitted as a contiguous stream of binary digits. It is necessary, therefore, to utilize a different clock (bit) synchronization method. One approach, is of-course is to have two pairs of lines between the TX and RX. One to carry the transmitted bit stream and the other to carry the associated clock(timing) signal. The RX could then utilize the latter to clock the incoming bit stream, into, say, the receiver register within the USRT. In practice, however, this is very rarely possible, since, if a switched telephone network is used, for example, only a single pair of lines is normally available. Two alternative methods are used to overcome this dilemma: either the clocking information (signal) in embedded into the transmitted bit stream and subsequently extracted by the receiver, or the information to be transmitted is encoded in such a way that there are sufficient guaranteed transition in the transmitted bit stream to synchronize a separate clock held at the receiver. 3.7 Clock encoding and extraction: Two alternative methods of embedding timing (clock) information into a transmitted bit stream. The bit stream to be transmitted is encoded so that a binary 1 is represented by a positive pulse and a binary 0 as a negative pulse. The encoding method is thus known as bipolar encoding. Clearly, each bit cell contains clocking

information and, by means of a simple rectifier and delay circuit, the clock can readily be extracted from the received waveform. Since the waveform returns to zero after each encoded bit (positive or negative) with this method, the encoded signal is referred to as a Return-to-Zero or RZ waveform to represent the transmitted bit stream. The resulting waveform is referred to as a non-return-to-zero (NRZ) waveform and the method phase or Manchester encoding (PE). Although the associated clock extraction circuitry required for use with this method is a little more complicated than with bipolar encoding, the presence of a + ve or ve transition at the centre of each bit cell period, means that the extraction of the clock can be readily accomplished. Thus, with bipolar encoding the extracted clock is used to sample (clock) the incoming bit stream at the centre of each bit cell while with phase encoding the bit stream is sampled during the second half of each bit cell. 3.8 Data Encoding and clock synchronization: An alternative approach to encoding the clock in the transmitted bit stream is to utilize a stable clock source at the receiver which is kept in time synchronizm with the incoming bit stream. However, as there is no start and stop bit stream. However, as there is no start and stop bit with a synchronous transmission scheme, it is necessary to encode the information in such a way that there are always sufficient bit transitions (1-0, 0-1) in the transmitted waveform to enable the receiver clock to be resynchronized at frequent intervals. One approach is to pass the data to be transmitted through a scrambler which has the effect of randomizing the transmitted bit stream and hence remaining contiguous string of 0s or 1s. Alternatively, the data may be encoded in such a way that suitable transitions are always naturally present. The bit pattern to be transmitted is first encoded as follows, the resulting encoded signal being referred to as a non-return-to zero-inverted(NRZI) waveform. With NRZI encoding (also known as differential encoding), THE SIGNAL (1 OR 0) does not change for the transmission OF A BINARY 1, WHEREAS A BINARY 0 DOES CAUSE A CHANGE. This means that there will always be bit transition in the incoming signal of an NRZI waveform, providing there are no contiguous streams of binary 1s. On the surface, this may seen no different from the normal NRZ waveform but, if a bit oriented scheme with zero bit insertion is adopted, an active line will always have binary 0 in the transmitted bit stream at least every five bit cells. Consequently, the resulting waveform will contain a guaranteed number of transitions, since long strings of 0s cause a transition every bit cell, and thus enables the receiver to adjust its clock so that it is in synchronism with the incoming bit stream. The circuit used to maintain bit synchronism is known as digital phase locked loop (DPLL). To utilize DPLL, a crystal controlled OSC. (clock source), which can hold its frequency sufficiently constant, (require only very small adjustments at irregular intervals) is connected to the DPLL. Typically, the frequency of the clock is 32 times the bit rate used on the data link and this in turn is used by the DPLL to derive the timing interval between successive samples of the received bit stream. Hence, assuming the incoming bit stream and the local clock are in synchronism, the state (1 or 0) of the incoming signals on the line will be sampled (clocked) at the centre of each bit cell with exactly 32 clock periods between each sample. Now assume that the incoming bit stream and local clock drift out of synchronism. The adjustment of the sampling instant is carried out in discrete.

If there are no transitions on the line, the DPLL simply generates a sampling pulse every 32 clock periods after the previous one. Whenever a transition (1-0 or 0-1) is detected, however, the time interval between the previously generated sampling pulse and the next is determined to the position of the transition relative to where the DPLL thought it should occur. To achieve this, each bit period is divided into four quadrants shown as A,B,C and D in the figure. Each quadrant is equal to 8 clock periods and if for example, a transition occurs during quadrant A, this indicates that the last sampling pulse was in fact too close and hence late. The time period to the next pulse in therefore shortened to 30 clock pulses. Similarly, if a transition occurs in quadrant D, this indicates that the previous sampling pulse was too early. The time period to the next pulse is therefore, lengthened to 34 clock periods. Transitions in quadrant B and C are clearly nearer to the assumed transition and hence the relative adjustments are less (-1 and +1 respectively). Clearly, a transition at the assumed transition will result in the adjustment. Thus, successive adjustments keep the generated sampling pulses close to the centre of each bit cell. It can be readily deduced that in the worst case, the DPLL will require 12 bit transition to converge to the nominal bit centre of a waveform; four bit periods of coarse adjustments ( 2) and eight bit periods of fine adjustments ( 1). Hence, when using DPLL, it is usual before transmitting the first frame on a line, or following an idle period between frames, to transmit a number of characters to provide a minimum of 12 bit transitions. Two characters each composed of all OS, for example, will provide 16 transitions with NRZI encoding; this ensures that the DPLL will generate sampling pulses at the nominal centre of each bit cell by the time the opening flag of a frame is received. Once in synchronism, only minor adjustments take place.

3.9 Serial and Parallel Transmission: Within a piece of equipment, the distance and hence lengths of wire used to connect each subunit together are short. Thus, it is normal practice to transfer the data between subunits by using a separate piece of wire to carry each bit of the data. This means there are multiple wires connecting each submit together and data are said to be exchanged using a parallel transfer mode. This mode of operation results in minimal delays in transferring each word. When transferring information between two physically separate piece of equipment, especially if the separation is more than several metres, for reasons of cost and varying transmission delays in the individual, it is more usual to use just single pair lines, and transmit each octet making up the data a single bit at a time using a fixed time interval for each bit. This mode of operation is known as Bit Serial Transmission. ***