33 Days Just an analysis about

MICROPROCESSORS AND MICROCONTROLLERS

(Designed as per Anna University Syllabus) B.E. IV Semester CSE

MODULE I
By

Y. SYED SHA MUHAMED M.E., Ph.D*. Associate Professor

Department of Computer Science and Engineering, National College of Engineering, Maruthakulam Tirunelveli.

PREFACE
Dear Reader,
This book is designed for IV Sem B.E. CSE of Anna University Syllabus. It has 5 module. Every module is one unit. It is also helpful for MCA Students (Module 2, 3, 4) for Unit 1, 2 & 3. It is also designed for dedication purpose to help the student community. If a student (especially college first rank) who is not affordable to pay (or) a student who makes the laudable comment for the improvement of this book. He will be given book for free of cost. Hope you might be one among them with regards.

Author.

This book is dedicated especially for student community who are my jewels By Y. SYED SHA MUHAMED

SYLLABUS UNIT I

THE 8085 AND 8086 MICROPROCESSORS:

8085 Microprocessors Architecture addressing modes instruction set programming it 8085.

DAY I

p Day - I

Hello ! if you want to become tyro to adept in Microprocessor you probe this book.

DAY 1
MICROPROCESSOR: Single Chip CPU. Processors has two giants (i) (II) Intel (8085, 8086 etc) Motorola (6800, 68000 etc)

Evolution:
1. 2. 3. 4. Intel 4004 (4 bit p) Intel 8085 and 8080 (8 bit p) Intel 8086 (16 bit p) SX Intel (802686) DX

SX 5. Intel (80386) DX 6. 7. 8. i) Intel (80486) Pentium III, IV etc Core Processor 8087, 808107 etc.

For fast computation numeric coprocessor are used

About 8085:
8 bit p NMOS device. 6200 transistor, IC has 40 pins. 8085 can accept process 8 bit data simultaneously. That is why it is called 8 bit processor. 5 V power supply needed. It can operates on 3MHz clock free 8085A on 5MHz
6

It has 16 Address lines.

A0 A15 2 16 = 2 6 210 = 2 6 1 kb

= 64 kb 8 bit I/O addresses

2 8 256 I/O Ports.

AD0 AD7

It has the following addresses modes i) ii) iii) iv) v) Immediate Register Direct Indirect Implied

It can perform Arithmetic and Logical Operations.

Arithmetic:
i) ii) iii) iv) 8 bit binary addition (with carry) 16 bit binary addition 8 bit binary subtraction (with borrow) AND, OR, X-OR, Complement (NOT) and Shift operation

Shift left Multiply by 2 Shift right divided by 2

QUESTION ANSWERS I) TWO MARKS QUESTIONS

1) What is Microprocessor? Give example. Ans: Single Chip CPU 8085 etc. 2) What is Numeric coprocessor? Ans: For CPUs fast computation it needs numeric coprocessor Eg. 8087 etc. 3) Why 8085 is called 8 bit processor? Ans: It can accept, process 8 bit data simultaneously. 4) What are the addressing modes in 8085? Ans: i) Immediate ii) Register iii) Direct iv) Indirect v)Implied

II) ESSAY QUESTION

1. Explain evolution of Microprocessor. Ans:From Intel 4004 to core processor.

III) OBJECTIVE QUESTIONS:

1. Who are the two giants in Microprocessor family? a) Motorola, Apple 2. Which is 4 bit processor? a) 4004 a) 80. a) 6800 a) NMOS a) 6100 a) 3 MHz a) 8 address lines a) 8 a) Multiply by 2 b)8087 b) CMOS b) 6200 b) 5 MHz b) 16 address lines b) 256 b) divided by 2. b) 8085 A b) 68 3. What is bit number Motorola chip starts with? 4. Which is called Numeric coprocessor? 5. 8085 is _________________ devices 6. 8085 has _____________________ transistors 7. 8085 A needs _______________ clock frequency 8. 8085 maps how many address lines 9. 8085 has _____________ I/O ports. 10. What mechanism happens in shift left? b) Intel, Motorola

RESULT ANALYSIS
III) Objectives question carries / mark for every questions 8 10 Marks Excellent < 8 Poor If your score less than 8 repeat day 1. Otherwise go to Day 2.

Answer:
1) b 2) a 3) b 4) b 5) a 6) b 7) b 8) a 9) b 10) a.

10

DAY II

p Day - II

If you want to become meticulous with acumen in Microprocessor read Day II.

11

DAY II (INTROD)
8085 has i) ii) iii) Accumulator (8 bit) 6 GPR (8 bit each, BC, DE, HL) Two 16 bit register SP Stack Pointer PC Program counter 8085 has software and hardware interrupts. The hardware interrupts are TRAP RST 7.5 RST 6.5 RST 5.5 and INTR. It has Opcode 1) 2) 3) Operand

Opcode Fetch cycle ( 4 T) Memory Read Cycle (3 T) Memory Write Cycle (3 T)

(i.e. 4 time cycles)

It has DMA (Direct Memory Access) facilities.

Architecture of 8085:
8085 has following a functional blocks. 1) Registers. 2) ALU 3) Instruction decoded and machine cycle encoded 4) Address buffer 5) Address / Data buffer 6) Increment / Decrement Address latch 7) Interrupt control 8) Serial I/O control
12

9) Timing and Control circuitry.

QUESTIONS AND ANSWERS I) Two marks questions:

1) What are 6 GPRegisters in 8085? Ans: BC, DE, HL 2) What are 2 16 bit register in 8085? Ans: i) PC ii) SP 3) What are the interrupts in 8085? Ans: *TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR 4) What is DMA? Ans: Direct Memory Access

OBJECTIVE QUESTIONS
1) Accumulator in 8085 has ___________? a) 8 bits a) 8 bits a) TRAP a) 003 C x a) 3 T a) 3 T a) 3 T b) 16 bits b) 16 bits b) RST 7.5 b) 0042 x b) 4 T b) 4 T b) 4 T
13

2) GPR B&D register are ___________? 3) Who is the brightest priority interrupt? 4) What is the address location of RST 6.5? 5) How many time cycles for OFC? 6) How many time cycle for memory read? 7) How many time cycle for memory write? 8) DMA has _________________ ?

a) Cycle stealing a) 9 10) What is buffer?

b) Page replacements b) 10 b) RAM and ROM

9) How many functional blocks in 8085?

a) Temporary storage

Answers:
1) a 2) a 3) a 4) a 5) b 6) a 7) a 8) a 9) a 10) a

RESULT ANALYSIS

8 10 Marks Excellent < 8 Poor If your score less than 8 repeat day 1. Otherwise go to Day 3

14

DAY III

p Day - III

If you want to bag with accolades in Microprocessor you better read day III.

15

INTA INTR
RST 5.5

RST 6.5

RST 7.5

TRAP STD SIO

Interrupt & High priority interrupt Serial I/O Control

Interrupt Control

8 Bit Internal Data Bus

Accumulator

Temporary register

Flag Register

Instruction Reg.

W B D

Z
C E L SP PC

ALU

Instruction decoder and m/c cycle encoder

Data bus X1
Clk In

Increment/ Decrement Counter

Timing and Control Control Status DMA Reset Address Buffer

HOLD HOLD A Reset In Reset Out

X2

Address / Data Buffer AD0 AD7 Lower bit

16

Clk Out

READY RD W

ALE

So S1 I/M

A8 A15 Higher bit

8085 Architecture has 9 functional block. 1) Registers: a) General Purpose registers B, C, D, E, H, L b) Temporary Register w, z c) Special purpose registers Accumulator, Flag, Instruction register. Flag D7 S D6 Z Zero d) Sixteen Bit registers SP, PC II) ALU: (8 Bit) i) Arithmetic Unit +, - (Add, Sub) ii) Logical Unit AND, OR, XOR, ROTATE, CLEAR III) Instruction Decoder: Fetches by opcode fetch cycle. IV) Address Buffer: 8 bit unidirectional buffer (A8 A15) V) Address / Data Buffer: 8 bit bidirectional buffer (ALE) D5 X D4 AC Auxillary Carry D3 X D2 P Parity D1 X D0 Cy Carry

17

QUESTION AND ANSWERS:

Two mark questions
1) What are the GPR? Ans: B, C, D, E, H, L registers 2) What are the special purpose registers? Ans: Accumulator, Flag, Instruction register. 3) Draw the flag register?

D7 S

D6 Z

D5 X

D4 AC

D3 X

D2 P

D1 X

D0 Cy

Auxillary Carry 4) What are the functions performed by ALU? i) Add ii) Sub iii) AND iv) OR v) X-OR vi) ROTATE vii)

CLEAR 5) What is ALE? Address Latch Enable

18

OBJECTIVES QUESTIONS
1) HL is what type register? a) GPR a) GPR b) Special purpose register b) Temporary register b) w, z b) 16 bit b) AND, X-OR 2) w, z is what type register? 3) Following is Special purpose register? a) Accumulator a) 8 bit a) ADD 4) SP, PC are what type register? 5) Following are the logical operations? 6) What are the address lines for address buffer? a) AD0 AD7 (bidirectional)ii) A8 A15 (Unidirectional) 7) What is the Flip Flop used in ALE? a) DEF b) JK

Answer:
1) a 2) b 3) c 4) b 5) b 6) b 7) a

If your score is 6 (or) more excellent. You can go to Day 4. Otherwise repeat Day 3

19

DAY IV

p Day - IV

To become unconquerable in Microprocessor read day IV

20

DAY 4
vi) Incrementer / Decrementer Address Latch 16 bit register vii) Interrupt Control: RST 5.5, 6.5, 7.5, TRAP & INTA viii) Serial I/O control: STD, SOD ix) Timing and Control: i) ii) iii) STATUS DMA RESET

The pin diagram (8085A):

X1 X2 Reset SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INR INTA AD0

1 2 3 4 5 6 7 8 9 10 11 12

8085 A

40 39 38 37 36 35 34 33 32 31 30 29 28

Vcc Hold Hold A Clk Reset IN Rec 4 IO/M S RP WR ALE S0 A15

19 20 AD7 VSS

21 A0

21

QUESTION AND ANSWERS

Two Marks question:
1) What is the mechanism of incrementer / Decrementer Address Latch? Increment (or) Decrement the contains of program counter or stack pointer. 2) What is Interrupt? Say priority? Temporary stop Tray RST 7.5 RST 6.5 RST 5.5

Essay Questions:
Explain the architecture of 8085? Answer: Say the functional blocks with diagram.

22

DAY V

p Day - V

To become primitive to sophisticated in microprocessor read day V.

23

DAY 5
Instruction formats:
i) One Byte:

OPCODE ii) Two Byte:

PUSH

OPCODE

Operand

ADD B

iii)

Three byte OPCODE Operand 1 Operand 2 MOV A, B

Addressing Modes

Immediate

Register

Direct

Indirect

Implied

i)

Immediate: MVI A , 10 H data

I Must Coon

Destination

24

ii)

Register Addressing Mode:

MOV

A, B

Source

Destination

- (GPR is used) iii) Direct addresses mode: LDA 1000 A (1000)

iv)

Indirect Addresses Mode: Contend of conforms. LDAX A ( (BC) ) B

v)

Implied Addressing Mode: CMA A Complement A

25

QUESTION AND ANSWERS

1) What is one address instruction? Answer: OPCODE Operand

Opcode Operand Ex: 7 ADD B SUB B

Instruction address

2) What is two address instructions? Answer: OPCODE Operand1 Operand2

MOV A, B 3) What is zero address instruction? Answer: OPCODE

PUSH POP

ESSAY QUESTIONS:
1) Discuss the different addressing modes in 8085? Answer: i) Immediate ii) Register iii) Direct iv) Indirect v) Implied

26

OBJECTIVES QUESTIONS
i) ii) iii) iv) v) vi) PUSH is ___________ Address instruction a) Zero a) Zero a) One a) Register a) Register Register b) One b) One b) Two b) Data b) Register Memory SUB A is ___________ Address instruction ADD A, B is _______ Address instruction In immediate address mode contains register and ___________ (source) MOV B, C is ___________ addressing mode The difference between direct and indirect is ___________ a) Direct is content of indirect is content of content b) Indirect is content of direct is content of content

RESULT ANALYSIS
Answer:
1) a 2) b 3) b 4) b 5) a 6) a

If your score is greater than 5 go to day 6 otherwise repeat day 5.

27

p Day - VI

If you want to bombard in microprocessor read this day VI.

28

DAY - 6
Instruction Set

Data Transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 MVI r, data MVI M, data MOV rd, rs MOV M, rs MOV rd, M LXI rp, data STA addr LDA addr SHLD addr LHLD addr STAX rp LDAX rp XCHL 1 2 3 4 5 6 7 8 9 10 11 12 13

Arithmetic ADD r ADD M ADI data ADC r ADC M ACI data DAD rp SUB r SUB M SUI data SOB r SOB M SOI data 1 2 3 4 5 6

Increment / Decrement INR r INR M INX rp DCR r DCR M DCX rp

Branch Group 1 2 3 JMP addr

J condn addr

Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ANA r ANA M ANI data XRA r XRA M XRI data ORA r ORA M ORI data CMP r CMP M CPI data STC CMC CMA

Rotate 1 2 3 4 RLC RRC RAC RAR 1 2

Stack PUS POF

PCHL

29

Stack of I/O and M/C control group

PORT (I/O) PUSH POP CALL RET IN addr OUT addr

Interrupt EI DT

I Data Transfer:
1) MVI A, 08 2 byte instruction 4T 3T 7 Time cycles. Immediate addressing mode. 2) MVI M, 4OH (H L Pair) H F 20 2010 L = 10 Note: (Within GPR no need of MR, MW 3 time cycles) H or OF (opcode fetch) MR (data)

40

OF MR MW

4T 3T (data read) 3T (write) 10 T

3) MOV A,B Register (B) Register (A)

30

(within GPR so no need of MR, MV)

OFC 4) MOV M, B

4T 4T

TOTAL -

(H = 20)

(L) = 50

2050

10

OF 4T 5) MOV C,M

+ +

MW 3T

= = 7T

H = 20 L = 50 2050 15

15

OF 4T

+ +

MR 3T = 7T

6) L X I B, 1020 H X - for register pair I for I monodial

10

20

OF

4T

Data read 3 T (10) & 4 T (10)

31

= 10 T 7) STA 2000 H

10

A (10) OF 8) LDA 2000 H

2000 4T MW 30 (3T) MW 00 (3T)

2000

15

15

OF 4T + MR 20 (2T) + MR 00 (3T) + (2000) MR 3T = 13 T 9) SHLD 2500 H (L) (H) H = 30 (2500) (2501) L = 20

2500 2501

20 30

MR

MR

MW

MW
32

OF (4T) 10) LHLD 2500 H

(H) 3T

(L) 3T

2500 3T

2501 3T

= 16 T

(2500) (H) OF (4T)

= +

20 MW 3T

+ +

(2501 ) (H) MW 3T

= 30 + MR 3T + MR 3T

= 16 T

11) STAX B

A = 10

1020 BC OF = = 1020 4T 7T Register pair so 3T

10

12) LDAX B

1030 BC = = 13) XCHG H D L E 4T 1030 7T

15

Small Program:
1) Store 16 bin in location 3000 is Answer: MVI A, 16 H,
33

STA HLT (example for direct address) Another method: LXI MVI HLT

3000 H

H, 3000 H M, 16 H

(example for indirect addressing)

34

QUESTION AND ANSWERS

Two Mark Questions:
1) How many time cycles for OF, MR, MW? Answer: OF 4T Answer: MVI STA HLT A, 20 H 5000 H MR 3T MW 3T 2) Write a program to store 20 in location 5000 H

Essay Questions:
1) Write all data transfer instruction? (1 to 13) instructions. 2) Swap the content of location 2000 and 5000? Answer: LDA 2000 H MOV B,A LDA 5000 H STA STA HLT 3) Swap the content of location 2000 and 5000 in indirect address? 2000 H 5000 H MOV A,B

35

p Day - VII

Now introduction anchors.

36

DAY VII
Arithmetic Group:
In 8085 it has only ADD & SUBTRACT. 1) ADD B A (A) + (B) OF 4T 2) ADD M A (A) + (M) OF 4T MR 3T = 7T M=H H (20) L Pair L (10) (B) source destination A is implied

2010

15

10

A 25

3) ADI

08H

A (A) + 08 OF MR = 7T 4T 3T 4) ADC B A (A) + (cy) + (B) OF 4T 5) ADC M A (A) + (cy) + (M) HL OF 4T MR 3T = 7T 6) ACI 20 H
37

A (A) + (cy) + 20 HL = OF + data read = 4T + 3T = 7 T 7) DAD B Double Add (HL) (H) (L) + (B) (C) Result H L +

Similarly Subtract:
1) SUB A (A) (B) OF 4 T 2) SUB M A (A) (M) OF 4T MR 3T = 3) SUI A (A) 08 OF / 4T + Data Read (3T) 4) SBB OF = 4T 5) SBB M A (A) (M) cy OF 4T 6) SBI data read 3T = 7T 08
38

7T

08H = 7T

A (A) (B) cy

A (A) 08 cy OF + data read 4T + 3T = 7T 7) DAA (Decimal Adjust Accumulator) A = 0100 DAA 0100 1010 0000 0110 0101 0000 AD = 50 (BCD) 1010 = 4 A

Increment (or) Decrement

1) INR (B) 2) INR (H L) 20 50 2050 10 2 11 OF = 4T M B (B) + 1

OF + MR + MW 4T + 3T + 3T 3) INX rp INX if H H = 20 HL L = 10 rp register pair

= 10 T

20

11

= 6T 4) DCR B
39

(B) 4T

(B) 1

5) DCR M H L 10 T 6) DCX B B = 20 20 C = 10 9 2050 10 2 9

6T

40

QUESTION AND ANSWERS

Two Marks questions:
1) B = FF INR B= FF 01 00 INX B= FF 01 00 B FF 01 00 C B = 00 C = FF C = FF What is the value of INRB & INX B?

41

Essay Questions
1) Explain Arithmetic operations is 8085? Answer: ADD and Subtract discuss 6 + 6 instructions. 2) Discuss the different increment and decrement operator? Answer: 3 Increment location 5002. Answer: LXI INX INX HLT 4) Write a program to subtract two 8 bit numbers? Answer: LXI INX SUB INX HLT 5) Add two 16 bit numbers? Answer: LHLD 5000 XCHG LHLD 5002 DAD D
42

3 Decrement

3) Write a program Add two 8 Bit numbers? 5000 Location 5001 Location Add shot in

H, H H

5000 H

MOV A, M ADD M MOV M, A

OH H M H

5000

MOV A, M

MOV M, A

SHLD 5004 HLT 6) Sub two 16 bit numbers? Answer: LHLD 5000 XCHG LHLD 5002 MOV A, E SUB L MOV L, A MOV A, D SBB H MOV H,A LHLD 5004 HLT

43

p Day - VIII

To become no to know in microprocessors read day VIII

44

DAY 8
IV Branch Group
(i) JMP 2000 OF + MR + MR 4T + 3T + 3T ii) a) JC 2000 b) JNC c) JP d)JM e) JPE f) JZ g) JNZ iii) PCHL PC HL 6T A B 2000 2000 2000 2000 2000 2000 PC 2000 is assigned to PC (Program Counter) = 10 T

jump if carry = 1 at loc 2000 jump if carry = 0 at loc 2000 jump on possible at loc 2000 jump on Minus at loc 2000 jump on parity odd at loc 2000 jump on zero at loc 2000 jump on not zero at loc 2000

AND

Clamp

45

Logical Group: (i) 4T ANA AA ^ B B 11110000 B A 10101111

Application: Maskid (ii) 7T (iii) 7T (iv) 4T Clear Accumulator Or gate: B XRA AAXA A ANI A A X 60 60 ANA O A X (M) M

10100000

46

(v)

XRA AA +M 7T

(vi)

XRI A A + 40 7T

40

(vii) ORA A AAVA 4T (viii) AAVM 7T (ix) ORI 7T A A V 10 V (x) CMP AAB 4T (xi) 7T A A (HL) (xii) CPI 7T (xiii) STC Set carry = 1 Cy 1 (4T) (xiv) (xv) CMC Complement Carry (4 T) CMA Complement Accumulator (4 T) 10 (Compare immedial with data 10) A A 10 CMP M B (Compare B) 10 ORA M

47

QUESTIONS
Essay Questions:
1) Discuss Branch group instructions? Answer: i) JMP ii) Conditional Group iii) PCHL 2) Discuss logical group instruction? Answer: AND, OR, XOR, Compare, Complement etc.

OBJECTIVE TYPE QUESTIONS

1) What is the mechanism of JMP 2000? i) PC 2000 ii) HL 2000 2) JC _________ i) Jump on carry ii) jump on carry = 1 ii) Jump on carry = 0 3) JNC ________ i) Jump no carry 4) JP _____________ i) Jump on positive i) Jump on HL ii) Jump zero ii) Jump on negative ii) Jump on HL ii) Jump on HL ii) Adds accumulator ii) Adds accumulator ii) 2s Complement 5) JM ______________ 6) JZ _______________ i) Jump on zero 7) JNZ _____________ Jump no zero 8) What is XRA A? i) Clears accumulators 9) CMP A ___________ i) Clear Accumulator 10) CMA _____________ i) 1s Complement Accumulator

48

RESULT ANALYSIS 1) i 2) ii 3) ii 4) i 5) ii 6) i 7) i 8) i 9) i 10) i

If your score is 8 (or) more you are excellent. If less than 8 please repeat Day 8.

49

p Day - IX

Now it is day IX.

50

DAY 9
V) Rotate group i) R L C Rotate Accumulator left where B7 goes to carry and B0

B7

B0

cy

4T ii) R R C: Rotate Accumulator right. B0 goes to cy and B7 Reverse of RLC

B7

B0 cy

51

iii) R A L: Rotate Accumulator left through carry.

B7 cy

B0

iv) R A R: B7 4T B0 cy

4T

Programs:
i) Computer 1s complement of 54 in 1000 left loc? Answer: LDA 1000 CMA STA HLT 1000

52

VI) Stack Operations:

i) L X I (or) SPHL SP HL 6T i) PUSH rp eg. PUSH D sp, data sp data

10

20

Sp - 2 Sp - 1 Sp

20 10

ii)

P O P rp POP D 20 SP 1000 1000 10

E D iii) CALL pc

2000 H 2000 H

20 10

53

RET iv) v) CC 2000 to 2000

Call on carry = 1 C N C 2000 call on no carry similarly return v) vi ) vii) RC RST RST RST RST RST viii) I/O: a) b) ix) IN OUT 80 H return on carry r 0 5.5 6.5 7.5

R N C return on no carry (restart o to n) = = = = 0 x 8 = 0000 5x8+5x8=2 CH 3 C H (Address) 4 C H (Address)

80 H (device no) to Accumulator 50 H Acc 50 H (device) X T H L: Change top of stack with H L L <sp> H <sp + 1> x) i) E I: F F: ii) iii) iv) Hales
54

(Enable interrupt) (flip flop enabled)

FF1 D I (Disable) FF0 N O P (No operation) HLT

v)

S I M: Set interrupt mask interrupts R S T 7.5, 6.5, 5.5 are masked

1 7.5 1 Mask O - Unmask

1 6.5 R S T 5.5

Read Interrupt Mask: (R I M)

It display left status of interrupt

55

QUESTION ANSWERS
Two marks:
1) What is R L C? Answer: B7 B0

cy

2)

What R A L? B7 cy B0

3) 4)

STACK definition? Stores left data and retriew left data by PUSH and POP operation. Explain Restart n ? Answer: RST n R S T 5.5 R S T 6.5 R S T 7.5 = = = 5.5 x 8 6.5 x 8 7.5 x 8 = = = 2 CH 3 CH 4 CH

56

5)

What are the port operation? Answer: Port mean carry a) b) IN 50H Acc 50 H OUT 50 H 50 H Acc

6)

Define E I and DI? Answer: i) ii) EI: Enable Interrupt FF 1 DI: Disable Interrupt FF 0

2) 3) 4) 5) 6) 7) 8) 9)

How initialize SP? i) LXI SP i) CALL What is CNC 2000? i) Call on carry a) 2 CH What is in port? a) (device no to accumulator) b) (Accumulator to device number) What is EI? i) FF 1 What is DI? i) FF 0 What is S I M? i) Set interrupt mask ii) Reset interrupt mask
57

ii) LDAX ii) PUSH, POP ii) Call no carry

What are the operation in stack?

What is the vector address of RST 5.5? b) 3 CH

ii) FF - 1 ii) ALE 0

Essay Questions:
I. Explain rotate group instruction? Answer: R L C, R R C, R A L, R A R II. Explain Stack, call sub routine, I/O, Interrupt masking instruction? Answer: Condition PUSH, POP, Call Uncondition , EI, DT, STM, etc.

OBJECTIVE QUESTIONS
i) R A L is _________________ a) Rotate accumulator through carry b) Without carry rotation.

RESULT ANALYSIS
1) a 2) a 3) ii 4) ii 5) a 6) a 7) 1 8) 1 9) i

If your score is 8 or more you can go to Day 10. Otherwise repeat day 9.

58

p Day - X

The laudable module finishes.

59

DAY 10
Programs:
1) Shift right 8 bit data? Answer: MOV A,C RAR RAR RAR RAR MOV C, A HLT 2) Shift left 16 bit data? Answer: MOV A,B RAL MOV B,A MOV A,C RAL MOV C,A HLT 3) Sum of series of number? LDA 3000 H MOV C, A XRA A LXI H, 3000 H Loop ADD INX DCR JNZ STA HLT M H C Loop 3004

60

4)

Data Transfer (Block) MVI LXI LXI STA INX INX JNZ HLT C, H D X, D H D Loop 05H 2200 2300

Loop MOV A, M

DCR C

4)

Find number of negative numbers in block? Answer: MSB is 1 then negative LDA 3000 MOV C, A MVI LXI ANI JZ INR Ship INX JNZ STA HLT B, 00 H 3001 80 H Ship B H Loop 4000

Loop MOV A, M

DCR C MOV A,B

61

QUESTION AND ANSWERS (ESSAY)

1) Find the largest of given number? Answer: CMP M 2) Calculate the sum of odd number Answer: ANI JZ 01, H

62

Annexure

63

PROGRAMS FOR 8085 MICROPROCESSOR LEARNERS 1. Store 8-bit data in memory of 8085 microprocessor 2. Exchange the contents of memory locations in a 8085 microprocessor 3. Add two 8-bit numbers in a 8085 microprocessor 4. Subtract two 8-bit numbers in a 8085 microprocessor 5. Add two 16-bit numbers in a 8085 microprocessor 6. Add contents of two memory locations in a 8085 microprocessor 7. Subtract two 16-bit numbers in a 8085 microprocessor. 8. Finding one's complement of a number 9. Finding Two's complement of a number 10. Pack the unpacked BCD numbers 11. Unpack a BCD number 12. Execution format of instructions 13. Right shift bit of data 14. Left Shifting of a 16-bit data 15. Alter the contents of flag register in 8085 1. Store 8-bit data in memory of 8085 microprocessor MVI A, 52H : Store 32H in the accumulator STA 4000H : Copy accumulator contents at address 4000H HLT : Terminate program execution 2. Exchange the contents of memory locations in a 8085 microprocessor LDA 2000H : Get the contents of memory location 2000H into accumulator MOV B, A : Save the contents into B register LDA 4000H : Get the contents of memory location 4000Hinto accumulator STA 2000H : Store the contents of accumulator at address 2000H MOV A, B : Get the saved contents back into A register STA 4000H : Store the contents of accumulator at address 4000H 3. Add two 8-bit numbers in a 8085 microprocessor Sample problem (4000H) = 14H
64

(4001H) = 89H Result = 14H + 89H = 9DH Source program LXI H 4000H : HL points 4000H MOV A, M : Get first operand INX H : HL points 4001H ADD M : Add second operand INX H : HL points 4002H MOV M, A : Store result at 4002H HLT : Terminate program execution Flowchart

65

Program - 4: Subtract two 8-bit numbers Sample problem: (4000H) = 51H (4001H) = 19H Result = 51H - 19H = 38H

Source program: LXI H, 4000H : HL points 4000H MOV A, M : Get first operand INX H : HL points 4001H SUB M : Subtract second operand INX H : HL points 4002H MOV M, A : Store result at 4002H. HLT : Terminate program execution Flowchart

66

Program - 5.a: Add two 16-bit numbers - Source Program 1 Sample problem: (4000H) = 15H (4001H) = 1CH (4002H) = B7H (4003H) = 5AH Result = 1C15 + 5AB7H = 76CCH (4004H) = CCH (4005H) = 76H Source Program 1: LHLD 4000H : Get first I6-bit number in HL XCHG : Save first I6-bit number in DE LHLD 4002H : Get second I6-bit number in HL MOV A, E : Get lower byte of the first number ADD L : Add lower byte of the second number MOV L, A : Store result in L register MOV A, D : Get higher byte of the first number ADC H : Add higher byte of the second number with CARRY MOV H, A : Store result in H register SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H. HLT : Terminate program execution

67

Flowchart

6.Sample problem: (4000H) = 7FH (400lH) = 89H Result = 7FH + 89H = lO8H (4002H) = 08H (4003H) = 0lH Source program: LXI H, 4000H :HL Points 4000H MOV A, M :Get first operand INX H :HL Points 4001H ADD M :Add second operand
68

INX H :HL Points 4002H MOV M, A :Store the lower byte of result at 4002H MVIA, 00 :Initialize higher byte result with 00H ADC A :Add carry in the high byte result INX H :HL Points 4003H MOV M, A :Store the higher byte of result at 4003H HLT :Terminate program execution Flowchart

69

7. Sample problem: (4000H) = 19H (400IH) = 6AH (4004H) = I5H (4003H) = 5CH Result = 6A19H - 5C15H = OE04H (4004H) = 04H (4005H) = OEH

70

Source program: LHLD 4000H : Get first 16-bit number in HL XCHG : Save first 16-bit number in DE LHLD 4002H : Get second 16-bit number in HL MOV A, E : Get lower byte of the first number SUB L : Subtract lower byte of the second number MOV L, A : Store the result in L register MOV A, D : Get higher byte of the first number SBB H : Subtract higher byte of second number with borrow MOV H, A : Store l6-bit result in memory locations 4004H and 4005H. SHLD 4004H : Store l6-bit result in memory locations 4004H and 4005H. HLT : Terminate program execution. Flowchart

71

72

8.Sample problem: (4400H) = 55H Result = (4300B) = AAB Source program: LDA 4400B : Get the number CMA : Complement number STA 4300H : Store the result HLT : Terminate program execution Flowchart

9. Sample problem: (4200H) = 55H Result = (4300H) = AAH + 1 = ABH Source program: LDA 4200H : Get the number CMA : Complement the number ADI, 01 H : Add one in the number
73

STA 4300H : Store the result HLT : Terminate program execution Flowchart

10. Sample problem: (4200H) = 04 (4201H) = 09 Result = (4300H) = 94 Source program:

LDA 4201H : Get the Most significant BCD digit RLC RLC RLC RLC : Adjust the position of the second digit (09 is changed to 90) ANI FOH : Make least significant BCD digit zero MOV C, A : store the partial result LDA 4200H : Get the lower BCD digit ADD C : Add lower BCD digit STA 4300H : Store the result
74

HLT : Terminate program execution

Flowchart

11. Sample problem: (4200H) = 58 Result = (4300H) = 08 and (4301H) = 05 Source program: LDA 4200H : Get the packed BCD number ANI FOH : Mask lower nibble RRC RRC RRC RRC : Adjust higher BCD digit as a lower digit
75

STA 4301H : Store the partial result LDA 4200H : .Get the original BCD number ANI OFH : Mask higher nibble STA 4201H : Store the result HLT : Terminate program execution Flowchart

12. Main program: 4000H 4003H 4006H 4009H 400CH LXI SP, 27FFH LXI H, 2000H LXI B, 1020H CALL SUB HLT

76

Subroutine program: 4100H 4101H 4102H 4105H 4108H 4109H 410CH 410DH 410EH C. Sample problem: (4200H) = 58 Result = (4300H) = 08 and (4301H) = 05 Source program 1:

SUB: PUSH B PUSH H LXI B, 4080H LXI H, 4090H SHLD 2200H DAD B POP H POP B RET

13. Statement: Write a program to shift an eight bit data four bits right. Assume data is in register

Flowchart for Source program1

MOV A, C RAR RAR RAR RAR MOV C, A HLT

77

14. Statement: Write a program to shift a 16 bit data, 1 bit right. Assume that data is in BC register pair. Source program 2

Flowchart for Source program1

MOV A, B RAR MOV B, A MOV A, C RAR MOV C, A HLT

15. PUSH PSW: Save flags on stack

POP H: Retrieve flags in 'L' MOV A, L :Flags in accumulator CMA:Complement accumulator MOV L, A:Accumulator in 'L' PUSH H:Save on stack POP PSW:Back to flag register HLT:Terminate program execution

78

16. 8085 Program to calculate GCD of two numbers. OBJECTIVE :To Determine GCD of two numbers. The Two Numbers are stored at consecutive memory locations :8000H and 8001H. The GCD of two numbers is stored at memory location 8003H. LOGIC:STEP 1:-Compare number 1(no1) with number 2(no2).If no1==no2,go to step 3. Else if no1<no2 ,then exchange no1 and no2. STEP 2:-no1=no1-no2; go to step 1 STEP 3:-Display result as no1. STEP 4:-Stop. ASSEMBLY PROGRAM:LXI H,8000H MOV A,M INX H MOV B,M L1: CMP B JZ OUT JC L2 SUB B JMP L1 L2 : MOV C,B MOV B,A MOV A,C JMP L1 OUT: STA 8003H HLT

79

29

80

81

82

MODULE II

83

SYLLABUS UNIT II
8086 SOFTWARE ASPECT:
Intel 8086 Microprocessor - Architecture

84

Day XI in Microprocessor

Slowly you are mincing towards exemplary in microprocessor

85

Day 11
Introduction to 8086 Microprocessor Year 1978, HMOS Flavors: ALU, internal registers all are 16 bit. So it is called 16 bit microprocessor. Reads or writes data to port in 16 bit It has 20 address lines, so it can map 220 1 mb 216 I/O devices (port) i) ii) iii) 10 MHz 8 MHz 8 MHz 8086 1 8086 2 8086

It functions in MIN & MAX mode. In micro computer only one 8086 microprocessor is available then it is min mode. If multiprocessor max mode.

86

Architecture of 8086
Memory Interface C - Bus

B - bus BIU ES CS SS DS IP

6 5 4 3 2 1 Instruction stream byte queue

Control systems Eu A - Bus

AX BX CX DX

AH BH CH DH
SP BP SI DI

AL BL CL DL

ALU

Operands Flags

87

Register organization:
(i) GPR

AX BX CX DX

AH BH CH DH

AL BL CL DL

All are 16 bit register. Accumulator AX is 16 bit. AL can be 8 bit.

(ii)

Segment Registers:

ES Base address (or) segment base

64 K

1 Mb Physical Memory

SS

64 K

DS

64 K

CS (iii) Pointers and Index Registers: IP points code segment BP points data segment SP Points stock segment

64 K

88

SI, DI used in addressing. SI Source Index DI Destination Index iv) 15 X 14 X Flag register: 13 X 12 X 11 O 10 D 9 I 8 T 7 S 6 Z 5 X 4
AC

3 X

2 P

1 X

0 cy

O Overflow flag D Direction I Interrupt T Trap Cy Carry

S Sign Z Zero AC Auxillary carry P Parity

Questions and Answers

Two Marks:
1) How many address and data line in 8086? Answer: Address Data 20 16

2) What is the clock frequency of 8086 -1 , 8086 2? Answer: 8086 1 8086 2 3) What is MIN Mode? Answer: In micro computer if only one 8086 microprocessor is there than min mode.
89

10 MHz 8 MHz

4) How many GPR define in 8086? Answer: 4 GPR AX, BX, CX, DX

90

5) IP, BP and SP points to which segment? Answer: IP BP SP points to code segment points to data segment points to stock segment

Objective Question
1) Which MOS technology in 8086? i) HMOS ii) CMOS

2) 8086 Maps ____________ i) 1 Mb ii) 64 K

3) The clock frequency of 8086 _________________ i) 8 MHz ii) 5 MHz

4) Min mode 8086 microprocessor is _______________ i) Many ii) One

5) Multiprocessor functions in __________________ i) Min mode ii) Max mode

6) What is AX and AL? i) AX 16 bit AL 8 bit ii) AX 16 bit AL 16 bit 7) BP points __________ segment i) Code segment ii) Data segment
91

8) SI, DI used in _________________ i) Interrupt ii) Addressing

Result analysis
Answers:
1) i 2) i 3) ii 4) ii 5) ii 6) i 7) ii 8) ii

If your score is more than 7 go to day 12 otherwise repeat day 11.

92

Day XII

It is ineffable to say about 8086 microprocessor please go to Day XII

93

DAY 12
Architecture continuation:
In 8086 it has two units i) Bus interface unit i) BIU: Interface with outer world The jobs of BIU is 1) Sends address of I/O and memory 2) Fetches instruction from memory 3) Reads data 4) Writes data 5) Executes instruction queue 6) Address relocation Hence when you pass the light on BIU it has i) segment register ii) IP iii) summer iv) instruction queue Instruction queue: BIU fetches six instruction bytes. Feature of fetching the next instruction. While the current instruction execution is called pipelines. F + U + X + ST ii) Execution unit

BU

F1

F2

F3

U1

U2

etc

94

Describe about segmentation

ADDRESSING MODES (8086)

Direct

Register Indirect Addressing mode

Based Addressing Mode

Indexed Addressing Mode

Based Indexed Addressing Mode

String Addressing Mode

i) Direct Addressing: IP

2000

10

MOV AL,

[ 2000 H] 10,000

DS/Ppr

1000

10

2000

ii)

Register Indirect: (IP) MOV BX, (CX)

12,000

10

Content of content

DS

1000

10

10,000 BX 16 / 15

16 + CX 3000 H 13,000 15

95

iii)

Base plus index ( BP ) MOV CX, (BX + DI) X 10 12,000 +

DS

1000

BX

2000 13,500 + CX

20 10 2 0 2 0

CX

3000 H

1 0 1 0

Question and Answers

Essay Question: 1) Explain the architecture of 8086? 2) Discuss the functioning mechanism of BIU and EU?

96

Microprocessor Day XIII

It is ineffable to say microprocessor now please read day XIII.

97

Day 13
Addressing Mode 8086 4) Register relative addressing: MOV CX, [BX + 003 H]

51,004 DS 5000 50,000 51,003

10 20

51,003 BX 1000 + 3

SP / CX

10

20

5) Base relative plus index address MOV AL, [BX + SI + 10H] 22,010 BX 1000 2000 + SI 1000 AL 10 + 22,010 10

DS

2000

98

6) String Addresses mode: MOV S BYTE 7) I/O Ports accessing by address modes: i) Direct IN ii) Indirect IN AL, DX AX, 80 H

8) STACK Memory addressing mode: PUSH & POP Instruction set Here it is like 8086 by multiplication and division also instruction are available.

99

Instruction Set

Data Movement Instruction MOV PUSH POP XCHG XLOT

Add Sub Compare ADD ADC INC SUB SBB DEC NEG CMP

MVL DIV MVL IMUL DIV

BCD &ASCII Arithmetic DAA DAS

Logic Instruction NOT AND OR XOR TEST

Shift and Rotate

SAL/SHL

String Compare
REP

Jump CALL RET JMP JCON

M/C Control
STC

Interrupt instruction INT INTO RET

SHR SAR

MOVS CMPS

CLC CMC STD CLD

100

Data Transfer (8086) Day 17 i) ii) iii) iv) MOV BX, AX ( 5 addresses modes) implement it PUSH BX ( POP Copy BX to Stack)

CX (top of stock to CX)

XCHG BX, CX

I) Arithmetic instruction: i) ii) iii) iv) v) ADD AX, BX [ AX AX + BX ] ADC DX, BX, DX DX + BX + Cy INC BX

ADD AL, BL DAA

II) Subtract Instruction: i) ii) iii) iv) v) vi) SUB SBB DEC AX, BX [ AX AX BX] DX, BX [ DX DX BX Cy] BX

NEG AL ( zs complements) CMP BX (AX BX) SUB AL, BL

DAS (Decimal After Sub) AL = 0010 0011 CL = 0101 1000 1100 1011
101

Decimal After Sub

1100 0110 1100 01 01 Sub 0110 0001 0110 01 01 - (65)

III) Multiplication: i) MUL BX AX AX, BX ii) IMUL (signed byte) IMUL CX IV) DIVISION: i) DIV BX

AX AX / BX Quotient in AX remainder in BX IV ) Logical Instruction: (Prefer 8 bit data) i) NOT NOT ii) AND CX CL BX

AND AL, BL iii) OR iv) AL OR CL XOR: CX

XOR AL, BL

102

v) i) Cy 0 1 ii) SAL / SHL: B7 1 0 B1 1 1 B0 0 0

SHR:

0 1

. .... .

SHR destination, count 1 0 iii) 0 1 RCL: RCL destination, count Cy 0 0 . 0 ..... 1 0 Cy 0 1

iv)

RCR: B Cy

Question Answers
Essay:
i) Explain the addressing modes in 8086?
103

ii) iii) iv)

Discuss Data Transfer instruction in 8086? Discuss Arithmetic and Logic instruction in 8086? Discuss about shift and rotate in 8086?

104

Microprocessor Day XIV

The laudable man is reading the laudable microprocessor

105

Day 14
Near i) CALL : Far CALL PRO ii) iii) Res return JMP: (Unconditional) JMP iv) NEXT Inter segment Intra segment

Name of the procedure

J (Condition)

VI) Processor control instruction:

i) ii) iii) iv) v) STC CLC Set carry Reset the carry flag to zero Complements the carry flag Set direction flag Reset the direction flag to zero

CMC STD CLD -

VII) Interrupt instruction

1) INT Type Far (0 255 type)

2) INT

O Over Flow flag is set

3) RET
106

VIII) String instructions:

1) REP CX = BX, 0 CX

2) MOV S

3) CMP BX, CX

Essay questions
1) Discuss about Jump, processor instruction, interrupt instruction and string instruction?

107

DAY XV

This book makes you as Man with meticulous awards (accolades) in microprocessor

108

DAY 15
Assembler Directives (Pseudo operations) 1) ALIGN 2) ASSUME ASSUME CS: Code Segment; 3) CODE 4) DATA DB BW DD DQ DT Eg: COST DB 10,20,30 Define byte Define word Define double word Define qued word Define Ten Bytes 8 (numbers)

Cost

10 20 50

5) DUP: Initialize TABLE 6) END 7) EQU 8) EXTRN 9) Groups: All segment of same data byte
109

BW

10

DUP

(0)

10) Label 11) MACRO END M 12) Name: Name of each module 13) OFF set: Displacement 14) ORG: ORG 15) PTR 16) PAGE [ length] [ width ] 17) Proc and End P 18) Public 19) Segment and End S 20) Short: Short address 21) STACK 22) TITLE: TITLE rent ALP : (Assembly Language Programs) Addition of two numbers NAME PAGE TITLE Model Small Stack 100 Data
110

1000

Start with 1000

STACK [ SIZE]

addition 52, 80 Add of two numbers

N1 N2 Code START MOV MOV ADD ADC MOV END

DB DB

42H 43H ? @data (Initialize data segment)

Result DW

MOV AX, DS, AX AL, N1 AL, N2 AH, 00 Result, AX Stack

Question and Answers

Essay question:
1) Discuss the different assembler directives?

Objective Type question

i) Assembler directives are also called _____________________ a) Pseudo operations ii) b) conditional operation

Four physical segments are a) Code b) data c) stack iv) ?

iii)

DB is in ________________in assembler directive a) Data buffer b) Define byte

iv)

DT ___________ a) Define Terminals ii) Define Ten bytes

v)

DUP ___________
111

a) Initialize b) duplicate vi) EQU is __________ a) Equate numeric b) Equate numeric and string

vii)

MACRO means ____________ subroutine a) Null sub routine b) Open subroutine

Result Analysis
1) a 2) b 3) b 4) b 5) a 6) b 7) b

If your score is greater than 6 go to day 16 otherwise repeat day 15.

112

DAY XVI

The erudite lured by this microprocessor

113

DAY 16
Open (Macro) 1. Procedures: Closed Near 2. Procedure Far But for far procedures CALL instruction pushes lot IP and CS on the stack. Parameter passing mechanism in procedure i) ii) iii) iv) i) Using registers Using general memory Using pointers Using stack

Parameter passing using register: Main Prog CS MOV AL, d1; : CALL PRO 1 : ; procedure PRO 1 MOV : RET
114

PROC INPUT ,

NEAR AL;

PRO 1 CODE Main Program DS BCD _ INPUT

END P END

ii) Parameter passing using memory:

DB 42; storage DB 2; storage

HEX _ VALUE DATA CS CALL Procedure PRO 1 MOV AL, PROC BCD, INPUT 42; PRO 1 END,

NEAR

iii) Passing parameter using pointers: BCD_INPUT DB : MOV SI, BCD _ INPUT MOV AL, [SI] iv) Passing parameters using array: BCD _ INPUT MOV AX, [BTR] DW 4209; MOV AX, OFFSET BCD_INPUT

115

ii) Reentrant Procedure MAIN LINE PROC 1 Cal PL PROC 2

RET

RET main prog PROC 2 re enters PROC 1

iii) Recursive procedure Call pro

Call

Call

Cc

RET

Macros: INI T MACRO @ data MOV AX, MOV DS : END M

Important

116

i) Passing parameters in Macro: INT LEA ii) Local iii) Global T HEY MACRO HEY

Question and Answers

Two mark question:
i) What are the two types of procedure? Answer: i) Open Answer: i) Using registers ii) iii) iv) Using general memory Using pointers Using stack ii) Closed ii) What are the parameter passing mechanism in procedures?

Essay questions:
1) Describe about procedure and parameter passing mechanism? 2) Describe about Macros and Parameter passing in macros?

117

Day XVII

You are reaching to the apex of 8086 microprocessor

118

Day 17
Please probe about 8086 expeditely

119

Day 17
Assembly language prog:
i) . IF . IF _ . . ELSE (Optional) : . END IF ii) WHILE _ END W . WHILE . END W iii) REPEAT E iv) WHILE v) FOR Interrupts Normal program can be interrupted by three ways An interrupt caused by an external signal is referred as a hardware interrupts. Conditional interrupts (or) interrupts cased by special instructions are called software interrupt. i) By external signal ii) iii) By a special instruction in the program By the occurrence of some condition ELSE END IF (Condn)

i) External Signal: (Hardware signals) i) NMI input pin ii) INTR input pin ii) Special instruction: It (8086) supports a special instruction, INT to execute special program.

120

iii) Condition produced by instruction: DIV by zero

MAIN prog PUSH FLAG PUSH CS PUSH IP

ISR Push register

POP POP POP

IP CS FLAG Pop register INT

Type 255 points

. . . Type 2 NMI Type 1 Single - step DIV by zero Type 0

121

Interrupt (Vector) Pointer tabe. Type 0 : Type 1: Divide by zero interrupt Single step interrupt The single step mode, systems will execute one instruction and wait for further direction from user. Type 2 : Type 3 : Type 4 : NMI Break point Over flow

Software interrupts: TYPE 0 255 ; INT 2 instruction from NMI ISR With the software interrupts you can call the desired routines from many different programs in a system by BIOS. Priorities: Div error Int A, Int 0 NMI INTR SINGLE STEP High

Lower

Question and Answers

Two mark questions:
1) What are the ways the normal program was interrupted? Answer: 3 ways 2) What is hardware interrupt? Answer: By external signal 3) What is software interrupt?
122

Answer: Special instruction 4) What are the hardware signal interrupt pin? Answer: i) ii) NMI INTR

5) Write the priority of interrupt?

Essay question:
1) Discuss about the interrupts and its priorites?

123

Day - 18

The second unit concludes

124

Day 18
MODES (8086)

Minimum

Maximum

I. 8086 Minimum mode: ((i) to (ii) Common Signals for Min and Max) i) AD0 AD15 ii) A16 / S3 A19 / S4 S3 0 0 1 1 S4 0 1 0 1 Register ES SS CS DS

iii)

B HE / S7 : (Bus High Enable) BHE 0 0 1 1 A0 0 1 0 1 Data accesses Word Upper byte from odd address Lower byte from even address NON

iv)

NMI

v)INTN vi) Clock 8086 vii) Reset

125

5Mhz

viii) Read ix) TEST: wait signal x) RD (o/p) xi) MN / MX (input) For min mode only xii) INTA (Min mode only) xiii) ALE: AD0 AD15 xiv) D EN : This signal informs the transceivers that the CPU is ready to send or receive data. xv) DR / R (Data transmit / receive) xvi) M / I O xvii) W R xviii)HOLD:

126

MAXIMUM MODE ONLY: 1) QS1 0 0 1 2 QS0 0 1 0 2 Status No operation First byte of an opcode Queue is empty Subsequent byte of an opcode

2)
S2 S1
S0

M/c Cycle Interrupt Ack I/O read I/O unit Halt Instruction fetch Memory read Memory unit inactive

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

3) LO CK : Bus not for another processor 4) RQ

GT 1

and RQ

GT 0

127

Question and Answers

Essay question
1) Explain common in Min and Max mode? 2) Explain pin only in Min mode? 3) Explain pin only in Max mode?

128

ANNEXURE FOR 8086 DIAGRAM

129

130

131

132

133

134

135

136

137

138

139

140

ANNEXURE FOR 8086 MICROPROCESSOR

141

PROGRAMMING

142

Ex. No: 1
AIM:

32 BIT ADDITION AND SUBTRACTON

To write an assembly language program to add and subtract two 32-bit numbers using 8086 microprocessor kit. APPARATUS REQUIRED: 8086 Microprocessor Kit Power Chord Key Board

33 - BIT ADDITION: ALGORITHM: Step1: Start the program. Step2: Move immediately the number 0000H to CX register. Step3: Copy the contents of the memory 3000 to AX register. Step4: Add the content of the memory 3004 with the content of AX register. Step5: Copy the content to AX register to two memories from 2000. Step6: Copy the contents of the memory 3002 to AX register. Step7: Add the content of the memory 3006 with the content of AX register. Step8: Jump to specified memory location if there is no carry i.e. CF=0. Step9: Increment the content of CX register once. Step10: Copy the content to AX register to two memories from 2002. Step11: Copy the content to CX register to two memories from 2004. Step12: End.

MNEMONICS:
143

MOV CX, 0000 MOV AX, [3000] ADD AX, [3004] MOV [2000], AX MOV AX, [3002] ADC AX, [3006] JNC INC loop1 CX

Loop1 MOV [2002], AX MOV [2004], CX HLT TABLE: 1 Memory Label Mnemonics
Instruction Operand

Description Move immediately 0000H to CX register Copy contents of 3000 to AX register Add content of memory 3004 with content of AX register Copy content to AX register to two memories from 2000 Copy contents of memory 3002 to AX register Add content of memory 3006 with content of AX register Jump to specified memory CF=0 Increment content of CX register once Copy content to AX register to two memories from 2002 Copy content to CX register to two memories from 2004
144

1000 1004 1008 100C 1010 1014 1018 101A 101B

MOV MOV ADD MOV MOV ADC JNC INC Loop1 MOV

CX,0000 AX, [3000] AX, [3004] [2000], AX AX, [3002] AX, [3006] loop1 CX [2002], AX

101F

MOV

[2004], CX

1023

HLT

Halt

OUTPUT: INPUT DATA: 3000: 3002: 3004: 3006: 9999 9999 9999 9999 OUTPUT DATA: 2000: 3332 2002: 3333 2004: 1

32 - BIT SUBTRACTION: ALGORITHM:

145

Step1: Start the program. Step2: Move immediately the number 0000H to CX register. Step3: Copy the contents of the memory 3000 to AX register. Step4: Add the content of the memory 3004 with the content of AX register. Step5: Copy the content to AX register to two memories from 2000. Step6: Copy the contents of the memory 3002 to AX register. Step7: Subtract the content of the memory 3006 from AX register. Step8: Jump to specified memory location if there is no carry i.e. CF=0. Step9: Increment the content of CX register once. Step10: Copy the content to AX register to two memories from 2002. Step11: Copy the content to CX register to two memories from 2004. Step12: End. MNEMONICS: MOV CX, 0000 MOV AX, [3000] ADD AX, [3004] MOV [2000], AX MOV AX, [3002] SBB AX, [3006] JNC INC loop1 CX

Loop1 MOV [2002], AX MOV [2004], CX HLT

146

TABLE: 2 Memory Label Mnemonics

Instruction Operand

Description Move immediately 0000H to CX register Copy contents of 3000 to AX register Add content of memory 3004 with content of AX register Copy content to AX register to two memories from 2000 Copy contents of memory 3002 to AX register Subtract content of memory 3006 from content of AX register Jump to specified memory CF=0 Increment content of CX register once Copy content to AX register to two memories from 2002 Copy content to CX register to two memories from 2004 Halt

1000 1004 1008 100C 1010 1014 1018 101A 101B 101F 1023 OUTPUT: INPUT DATA: 3000: 9999 3002: 9799 3004: 9999 3006: 9999

MOV MOV ADD MOV MOV SBB JNC INC Loop1 MOV MOV HLT

CX,0000 AX, [3000] AX, [3004] [2000], AX AX, [3002] AX, [3006] loop1 CX [2002], AX [2004], CX

OUTPUT DATA: 2000: 0000 2002: FE00

147

RESULT: Thus an assembly language program to add and subtract two 32-bit numbers was written and executed using 8086 microprocessor kit.

148

Ex. No: 2
AIM:

16 BIT MULTIPLICATION AND DIVISION

To write an assembly language program to multiply and divide two unsigned 16-bit numbers using 8086 microprocessor kit. APPARATUS REQUIRED: 8086 Microprocessor Kit Power Chord Key Board

MULTIPLICATION: ALGORITHM: Step 1: Start the program. Step2: Copy the contents of the memory 3000 to AX register. Step3: Copy the contents of the memory 3002 to CX register. Step4: Multiply the content of the CX register with the content of accumulator. Step5: Copy the content to AX register to the memory 2000. Step6: Copy the contents of DX register to the memory 2002. Step7: End. MNEMONICS: MOV AX, [3000] MOV CX, [3002] MUL CX MOV [2000], AX MOV [2002], DX HLT
149

TABLE: 1 Memory Label 1000 1004 1008 MOV MOV MUL Mnemonics
Instruction Operand

Description Copy contents of 3000 to AX register Copy contents of 3002 to CX register Multiply the content of the CX register with the content of accumulator Copy content to AX register to the memory 2000 Copy content to DX register to the memory 2002 Halt

AX, [3000] CX, [3002] CX

100A 100E 1012

MOV MOV HLT

[2000], AX [2004], DX

OUTPUT: INPUT DATA: 3000: 3002: 1234 5678 OUTPUT DATA: 2000: 2002: 0060 0626

DIVISION:
150

ALGORITHM: Step 1: Start the program. Step2: Copy the contents of the memory 3000 to AX register. Step3: Copy the contents of the memory 3002 to CX register.
Step4: Divide the content of the CX register from the content of accumulator. Step5: Copy the content to AX register to the memory 2000.

Step6: Copy the contents of DX register to the memory 2002. Step7: End. MNEMONICS: MOV AX, [3000] MOV CX, [3002] DIV CX MOV [2000], AX MOV [2002], DX HLT TABLE: 2 Memory Label 1000 1004 1008 MOV MOV DIV Mnemonics
Instruction Operand

Description Copy contents of 3000 to AX register Copy contents of 3002 to CX register Divide the content of the CX register with the content of accumulator Copy content to AX register to the memory 2000 Copy content to DX register to the memory 2002 Halt

AX, [3000] CX, [3002] CX

100A 100E 1012

MOV MOV HLT

[2000], AX [2004], DX

151

OUTPUT: INPUT DATA: 3000: 3002: 1234 5678 OUTPUT DATA: 2000: 2002: 0000 4444

RESULT:

Thus an assembly language program to multiply and divide two unsigned 16-bit numbers was written and executed using 8086 microprocessor kit.

152

Ex. No: 3
AIM:

FACTORIAL

To write an assembly language program to calculate factorial of nnumbers using 8086 microprocessor kit. APPARATUS REQUIRED: 8086 Microprocessor Kit Power Chord Key Board

ALGORITHM: Step 1: Start the program. Step2: Move immediately the number 0000H to AX register. Step3: Copy the contents of the memory 3000 to CX register. Step4: Move immediately the number 0001H to AX register. Step5: Multiply the content of the CX register with the content of accumulator. Step6: Decrement the content of CX register once. Step7: Jump to specified memory location if there is no zero in CX register. Step8: Copy the content to AX register to two memories from 2000. Step10: End.

MNEMONICS:
153

MOV AX, 0001 MOV CX, [3000] MOV AX, 0001 Loop1 MUL CX DEC CX JNZ HLT TABLE: 1 Mnemonics
Instruction Operand

loop1

MOV [2000], AX

Memory Label 1000 1004 1006 MOV MOV MOV

Description Move immediately the number

AX, 0001 CX, [3000] AX, 0001

0001H to AX register Copy the contents of memory 3000 to CX register Move immediately the number 0000H to AX register Multiply content of CX register with content of accumulator Decrement content of CX register once Jump to specified memory location if there is no zero in CX register Copy content to AX register to memory 2000 Halt

100A

loop1

MUL

CX

100B 100C 100E 1012

DEC JNZ MOV HLT

CX loop1 [2000], AX

154

OUTPUT:
INPUT DATA: OUTPUT DATA:

3000: 0008

2000: 9d80

RESULT:

Thus an assembly language program to calculate factorial of nnumbers was written and executed using 8086 microprocessor kit.

Ex. No: 4

SORTING IN ASCENDING ORDER

155

AIM: To write an assembly language program to sort n-numbers in ascending order using 8086 microprocessor kit. APPARATUS REQUIRED: 8086 Microprocessor Kit Power Chord Key Board

ALGORITHM: Step 1: Start the program. Step2: Load datas into the memory. Step3: Set the conditions to sort n-numbers in ascending order. Step4: Sort the n given numbers in ascending order. Step5: Store the result in the memory. Step6: Display the sorted result from memory. Step7: End.

MNEMONICS: MOV BX, 2000

156

MOV CX, [BX] MOV CH, CL Loop2 INC INC INC INC JC BX BX BX BX loop1

MOV AX, [BX]

CMP AX, [BX] MOV DX, [BX] MOV [BX], AX DEC BX DEC BX MOV [BX], DX INC INC BX BX

Loop1 DEC BX DEC BX DEC CL JNZ loop2 MOV BX, 2000 MOV CH, CL DEC CH JNZ HLT loop2

157

TABLE: 1 Memory Label 1000 1004 1006 1008 1009 100A 100C 100D 100E 1011 1013 1015 1017 1018 1019 101B 101C 101D 101E 101F 1020 MOV MOV MOV Loop2 INC INC MOV INC INC CMP JC MOV MOV DEC DEC MOV INC INC Loop1 DEC DEC DEC JNZ Mnemonics
Instruction Operand

Description Move2000 to BX register Move BX memory data to CX register Move data from CL to CH Increment BX register content once Increment BX register content once Move BX memory data to AX register Increment BX register content once Increment BX register content once Compare AX register content and BX memory Jump to specified memory location if carry is 1 Move BX memory data to DX register Move data from AX register to BX memory data Decrement BX register content once Decrement BX register content once Move data from DX register to BX memory data Increment BX register content once Increment BX register content once Decrement BX register content once Decrement BX register content once Decrement CL register content once Jump to specified memory location if there is no zero in CX register

BX, 2000 CX, [BX] CH, CL BX BX AX, [BX] BX BX AX, [BX] loop1 DX, [BX] [BX], AX BX BX [BX], DX BX BX BX BX CL loop2

158

1022 1026 1028 1029 102B

MOV MOV DEC JNZ HLT

BX, 2000 CH, CL CH loop2

Move2000 to BX register Copy CL register data to CH register Decrement CH register content once Jump to specified memory location if there is no zero in CX register Halt

OUTPUT: INPUT DATA: 2000: 2002: 2004: 2006: 2008: 0004 0003 0005 0004 0002 OUTPUT DATA: 2002: 2004: 2006: 2008: 0001 0002 0003 0004

200A: 0005

200A: 0001

RESULT:

Thus an assembly language program to sort n-numbers in ascending order was written and executed using 8086 microprocessor kit.

Ex. No: 5

SOLVING AN EXPRESSION
159

AIM: To write an assembly language program for solving an expression using 8086 microprocessor kit. APPARATUS REQUIRED: 8086 Microprocessor Kit Power Chord Key Board

ALGORITHM: Step 1: Start the program. Step2: Load datas from memory to AX register. Step3: Set the conditions to solve an expression. Step4: Solve the expression given below using the conditions assumed. Step5: Store the result in the memory. Step6: Display the sorted result from memory. Step7: End.

MNEMONICS:
160

MOV BX, [2000] MUL AX MOV BX, [2002] MUL BX MOV [3000], AX MOV AX, [2000] MOV BX, [2004] MUL BX ADD AX, [3000] ADD AX, 0001 MOV [2006], AX HLT

TABLE: 1
161

Memory Label 1000 MOV

Mnemonics
Instruction Operand

Description Move data from memory 2000 to AX register Multiply content of AX register with content of AX register Move data from memory 2002 to BX register Multiply content of BX register with content of AX register Copy content to AX register to memory 3000 Move data from memory 2000 to AX register Move data from memory 2004 to BX register Multiply content of BX register with content of AX register Add content of memory 3000 with content of AX register Add the number 0001 to AX register Copy content to AX register to memory 2006 Halt

AX, [2000]

1004 1005

MUL MOV

AX BX, [2002]

1009 100A 100E 1012

MUL MOV MOV MOV

BX [3000], AX AX, [2000] BX, [2004]

1016 1017 101B 101F 1023

MUL ADD ADD MOV HLT

BX AX, [3000] AX, 0001 [2006], AX

OUTPUT:
162

INPUT DATA: 2000: 2002: 2004: 0002 0004 0007

OUTPUT DATA: 2006: 1F

RESULT:

Thus an assembly language program for solving an expression was written and executed using 8086 microprocessor kit.

Ex No: 6

SUM OF N NUMBERS IN AN ARRAY

163

AIM: To write a program to find sum of n numbers in an array.

APPARATUS REQUIRED: 8085 Microprocessor Kit Power Chord

ALGORITHM: Step1: Start the program. Step2: Initialize the counter. Step3: Get the first number. Step4: Decrement the counter. Step5: Load the base address of an array in to BX Step6: By using the loop get the next number in to DX and add it with AX. Step7: Increment the pointer and decrement the counter. Step8: If the counter value is not equal to zero then go to step6 Step9: Else store the result. Step10:Stop the program.

164

MNEMONICS: MOV CL,[2000] MOV AX,[2002] DEC CL XOR D1,D1 LEA BX,[2004] LOOP1 MOV DX,[BX+D1] ADD AX,BX INC D1 INC D1 DEC CL JNZ LOOP1 MOV [3000],AX HLT

165

TABLE: LABEL OPCODE MOV MOV DEC XOR LEA MOV ADD INC INC DEC LOOP 1 JNZ MOV HLT OPERAND CL,[2000] AX,[2002] CL D1,D1 BX,[2004] DX,[BX+DI] AX,BX DI DI CL LOOP 1 [3000],AX DESCRIPTION Move the memory content to CL. Move the memory content to AX Decrement the CL register. XOR,D1 registers Move the content of 2004 to BX Move the content of BX+D1 to DX Add AX with DX content. Increment D1 Increment D1 Decrement CL If zero flag is reseted go to loop1 Move the content to memory location Halt

166

OUTPUT: INPUT DATA: 2000:0003 2002:0002 2004:0003 2006:0001 OUTPUT DATA: 3000:0006

RESULT: Thus the sum of n numbers in an array has been done using 8086 microprocessor and the output is verified.

167

MODULE III

168

Unit III
Multiprocessor configurations
Coprocessor configuration closely coupled configuration Loosely coupled configuration 8087 Numeric data processor Data types Architecture 8089 I/O processor Architecture Communication between CPU and IOP.

169

Day 19th Microprocessor

Leaping as well as engrossing microprocessor

170

Day 19
a) Bus contension: More than one processor shares the system memory and I/O devices through a common system bus. b) IPC: Interprocessor communication c) Resource sharing: Deadlock may occur. If two processors unknowingly waiting for other processors. Coprocessor configuration Both the CPU and external (Coprocessor) Share entire memory and the I/O subsystem 8086/88 Call the 8087

COP ESCAP E

Monitor 8086

Execute the 8086 instruction

Deactivate TEST exec

Wait

Activate TEST COP

171

CPU

Check S6 if S6 = 0 then it is main processor. S6 = 1 then it is 8089 (I/O processor) BHC/ S7 is zero then COP i) Closely coupled configuration

8086

Clock

Bus control

log.c

System

8087

I/O

ii)

Loosely coupled configuration: It contains different modules. Each mode may consists of an 8086.

172

Local I/O devices

Local Memory

System Memory

System bus

Local Bus

Local bus control log

Clock

8086 + 8087

System bus control log

MODULE 1

System I/O device

Similarly Module 2

173

QUESTION AND ANSWERS

2 Mark Questions
1) What is bus contension? Ans: More than one processor shares the system memory and I/O devices through a common system bus.

Essay Questions:
1) Explain about mechanism of coprocessor and its configurations.

174

Day 20 in Microprocessor

Just a jaunt into multiprocessor

175

Day 20
In loosely coupled system each processor runs independently. If more than one processor by to access these common resources at same time there is problem of bus contention. To set out of this head ache. There are i) ii) iii) Daisy chaining Polling method Independent request.

i) Daily chaining:
Bus was requested. If bus is granted bus busy will be set. So other masters have to wait Module 1
Bus access

Module 2
Bus access

Module m .
Bus access

log c

log c

log c

ii) Polling method: Controller Bus request

Bus busy

Bus grant

Controller with generate the address for master. If 4 markers are there then 2 address lines 00 01 10 11 Master 0 Master 1 Master 2 Master 3

176

M0
Module Address

M1

M2

M3

0 Controller 0
Bus request Bus busy

0 1

1 1

iii) Independent priority method:

Master 1
Bus access

Master 2
Bus access

Master 3 .
Bus access

log c
Bus grant 1 Bus request 1 Bus grant 2 Bus request 2

log c

log c

Controller

177

Architecture of 8087

Reg 0 1 Clk INT AD0-AD15 BHE 2 3 4 5 6 Reg 7

8 Register Stack

TAG reg TAG (0) (1) (2) (3) (4) (5) (6) (7)

U S0, Q S1

Bus tracks it contain instruction queue

Floating point arithmetic module

Status register Busy Ready Next Instruction pointer Control register

Operand pointer

178

Control Register:
DIV by zero, interrupt TAG Data is there or not Data formats and conversion * * * * * * * Word integer 2 byte Shot integer 4 byte Long integer 8 byte Packed DCD 10 byte Short read Long read 4 byte 8 byte

Temporal read 10 byte

Stock contains data

179

QUESTION AND ANSWERS

2 Marks
i) What are the methods in remedy for bus contention? Answers: i) ii) iii) Essay Question: 1) What is bus contention explain the methods to get rid of bus contention? 2) Explain 8087? Daisy chaining Polling Independent

180

Day 21 in Microprocessor

Just passing the light about IOP

181

DAY 21
I/O Processor:
I/O is the mechanism of transferring data with I/O ports. The execution of I/O handled by microprocessor.

Memory

8251 USAR T

Command & Status

Data and Instruction

Floppy 8272 Command & Status Hand shet

CPU

8255 PPI

Command & Status

Command & Status

8237 DMA Controller

During if I/O is handled by IOP microprocessor can do other job.

182

For the reason intel launches IOP (8089)

Memory
8272 Data and Intn Data 8089 IOP

Command & Status Data 82

8086 p

Channel attention Interrupt

Data 8255

Finally

8089

Memory

8086

183

Architecture of 8089 (IOP)

DRQ2

EXT2 GA GB GC TP PP

STNTRL

RESET

SET Control Logic

CA
TA G

Channel 1

GA GB GC

CCP

TP PP

IX BC MC CC

AL U

IX BC MC CC

PSW

Bus Control and Interface

PSW

CLK

Ready
184

DMA Just recall then

Regarding IOP channel A:

The channel has i) ii) Register - IX, BC, MC, CC Pointers - GA, GB, GC, TP, PP

Pointers points address. Tag says the pointer has got info or not. But GA, GB, GC, IX, MC can be used as GPR to do arithmetic and logic operation and also it does DMA.

The DMA Mechanism:

1) GA and GB as for source and destination 2) GC stores base address 3) MC Mask compare

TP: Task Pointer

Address of the next instruction

PP: Parameter Printer:

PP says address of parameter module

PSO:
Current status of the channel

185

QUESTION AND ANSWERS

2 Mark Questions
1) Difference between I/O Channel and I/O bus? Ans: I/O Channel comes with I/O processor I/O bus Data lines 2) What is 8272? Ans: 3) What is DMA? Ans: Direct Memory Access

Essay Questions
I. II. Explain completely above I/O processor? Explain completely about IOP communication mechanism?

OBJECTIVE TYPE QUESTIONS

1. What is 8251? i) USART ii) DMA

2. 8255 is ____________ i) Programmable peripheral interface ii) DMA

3. 8237 ___________ i) USART ii) DMA

4. 8089 _______ i) USART ii) I/O Processor

186

5. How many channels in IOP? i) 3 ii) 2

187

6. GA and GB are used for _____________ i) General purpose register ii) Interrupts

7) MC is _______________ i) Compiler i) 8251 ii) mask comperator ii) 8237 8) DMA number is __________ 9) Task pointer contains address of __________________ i) Current instruction ii) next instruction 10) PP is _____________ i) address of parameter block ii) Address of ISR 11) PSW says ________________ i) Interrupt status ii) Current status of channel

RESULT ANALYSIS ANSWERS:

1) 1 7) ii 8) ii 2) I 9) ii 3) ii 10) i 4) ii 11) ii 5) ii 6) ii

If your is more than 8 go to next day otherwise repeat.

188

MODULE IV

189

UNIT - IV I/O INTERFACING

Memory interfacing and I/O interfacing with 8085 Parallel communication interface serial communication interface timer keyboard / display controller - interrupt controller DMA controller (8237) applications stepper motor temperature control.

190

Day 22 in Microprocessor

If you want to explore the nexus with microprocessor you read and complete module

191

Day 22
Memory & I/O interfacing Port means carry
Trans means across by coining the above two words transport word was created. Similarly in computer from one microprocessor to I/O or memory to interconnect we should have port. Using the port pins we can transmits (or) receive data from one microprocessor to another I/O (or) memory. So the concept of port is happening through transmit and receive data by the port command out (port) and in (port). The interfacing mechanism is i) ii) Serial communication interface Parallel communication interface

First I will just pass the light on memory interface. From memory we can read and write into the memory. Memory is combination of registers which were selected by addressing. Memory is bifurcated into RAM & ROM.

i)

ROM: eg EPROM
Consider 2 K EPROM: Here only we can read to. O/P data

O/P Buffer

CS RD

A10

Internal Decode

2 K EPROM

A0

192

A10.A0 = 11 address lines 10 address line will map 210 = 1 K EPROM 11 address line map 211 = 210 x 2 = 2 K EPROM

ii)

FOR RAM:

O/P Buffer

CS RD

Internal Decode

A0

1 K EPROM

A9

I/P Buffer

WR
I/P data A0 A9 = 1 K RAM For write (or) Read memory interfacing. So we need address decoding technique (i) (ii) Absolute decoding Linear decoding

i) Absolute decoding:
After addressing remaining address line is meant for chip select. Eg: Interface 1 K RAM, 2 K EPROM with 8085: For 2 K EPROM and 1 K RAM

193

We need i) 2 K EPROM ii) 1K RAM

A0 A10 A0 A9

Now while interfacing

Vcc

D0-D7 A0-A7 A8A15

RD WR

74S138

IO / M

I OR I OW MR MW

Vcc

D0-D7 A8-A10 A0-A7 2K EPROM

D0-D7 A9-A8 A0A7 2K EPROM

CS
A13 A14 A15 74LS138 is low power shottkey 74LS138 Decoder n input 2n O/P

CS

G2
A12

G2
A11

194

Linear decoding:
Higher address line only used for addressing (A15) For 1K EPROM and 4K RAN interface with 8085 by linear decoding. L A T C H

AD0 AD7 ALE A8-A3 8085 RD

WR

AD0 AD7 D0 D7

IO/M A B C
G1 G2

MR MW IOR RO W D0-D7 A0-A9 RD Lk EPROM D0-D7 WR A11-A0 4K RAM CS CS RD

A15 So address mapping for 1k EPROM A15 Starting Ending Address 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 0000 0 X X X 0 0 1 1 1 1 1 1 1 1 1 1 03FF Similarly 4k RAM
195

Starting Ending Address

0 8000

1 9 F F FH

QUESTION AND ANSWERS 2 Mark questions

i) ii) Ans: i) ii) Absolute decoding Linear decoding Draw structure of 2k x 8 RAM? Where the address decoding technique?

Essay questions
I) Interface 8085 p with 4k RAM using linear decoding technique.

196

Day 23
I/O Interfacing

Day 23rd in Microprocessor

The scintillating concept on silver jubilee day

197

I/O interfacing
Actually for I/O is the communication between p and I/O. For the input keyboard to port to Data lines. Similarly for output, data lines to port than port to display devices The mechanism of read is kbd Similarly the O/P port is latch I/P port Tri-state buffer to 8085 p

I/O interfacing technique:

I/O devices can be rescued to 8085 A in following two ways. I. Memory mapped I/O II. I/O mapped I/O

198

i) I/O Mapped I/O: It uses IO/M pins the mechanism of input port it,

5V Switches S0 S1 S2 S3 S4 S5 S6 S 6 S7 D0-D7 Read Tristate buffer 8085

A0 A1 A2 A4 A6 A3

138 Decoder I/OM RD

IOR

A7

199

Similarly the mechanism is O/P port

D0 From 8085
D0 . D7

O/P port

A0 A1 A2 A4 A6 A3

Y1

A7 Now we will see If IOR, IOW is selected. It is I/O we can mapped with I/O port. If MEMR, MEW is selected.

IO/M WR IO/ W

It is memory we can mapped with I/O port. The first one we say I/O mapped I/O. The Second one is memory mapped I/O.

200

5V I/O Mapped I/O

R 8085 P D0 I0 . . .

I/P Port To 8085

IOR RD IOW 5V W R D7 I7

IO/M

A0 A1 A2 A4 A6 A3 D E C O D E R Y0 O/P Port O0 . . .

Y1 O7

A7

Similarly memory mapped I/O.

201

5V In memory mapped I/O Address lines are A0 A15 Memory Mapped I/O

R 8085 P D0 I0 . . .

I7

I/P Port To P 8085

MEMR RD MEM W 5V W R D7

IO/M

A0 A1 A2 A3 A6 138 Y0 O/P Port O0 . . .

Y1 O7

A8 . . . . A15
202

Question and Answers

2 Mark questions:
i) What is the mechanism of Tri-state buffer port? Ans: Input Port

kbd

I/P port Tri-state buffer

to 8085 p

ii)

What is the mechanism of I/P Port?

Ans: Watch Essay questions i) Explain I/O mapped I/O in interfacing of 8085? ii) iii) Explain memory mapped I/O in interfacing of 8085? Explain the mechanism of Input port and output port?

Ans: Individually explain

203

Day 24th in Microprocessor

Yes! It is a (long) obyssee in interfacing.

204

Day 24
Parallel communication interface:
8255 (Programmable peripheral Interface) Designed by intel. It has i) ii) iii) iv) Port A Port B Port C (Upper) Port C (Lower)

TTL Combatable (Just like junction box) It has i) ii) iii) iv) v) vi) vii) viii) ix) D0 D7 Data bus PA0 PA7 (Port A) PB0 PB7 (Port B) PC0 PC7 (Port C)
RD
WR CS

Reset A0,A1 ( R D , W R control inputs)

205

The pin Diagram of 8255

A3 A2 A1 PA
0

A4 A5 A6 PA
7

RD C S GND A1 A0 PC
7

W R

D0

Rese t
D1 D2

D3 D4 D5 D6 D7 Vcc B7 B6 B5 PB PB
3 4

PC
6

C5 C4

PC
0

PC
1

PC
2

PC PB
0 3

B1 B2

A1 & A0 for port selection

206

A1 0 0 1 0 0 1 1

A0 0 1 0 0 1 0 1

RD

WR

CS

0 0 0 1 1 1 1

1 1 1 0 0 0 0

0 0 0 0 0 0 0

RD

Functions = 0 to 1

Port A to bus Port B to bus Port C to bus Bus to Port A Bus to Port B Bus to Port C Bus to CWR (Control Word Register)

So the block diagram is FABULOUS BLOCK DIAGRAM OF 8255 Group A Control PA0-A7 Group A PCU Data Bus Buffer PC7PC4 PC0PC3 PB0PB7

Port A

PCL

Group B

Group B Control RD WR A0 A1
Reset

PBL

R/W Control log 2

The group A and Group B control blocks receives control words from CPU and issues appropriate commands to the ports associated with it.

Question and Answers

2 Marks:
207

1) What are the ports in 8255? Ans: i) ii) iii) iv) Port A Port B Port C upper Port C lower

2) What is the use of A0 and A1 in 8255? Ans: RD, write control inputs

Essay questions:
1) Explain the pin and block diagram of 8255?

208

Day 25th in Microprocessor

209

Day 25
Operation Modes
I) BSR Mode:
Set and reset port C by the mode. II) I/O Modes: i) ii) iii) Mode 0 : Simple I/O: Port A, Port B, Simple 8 bit I/O port Mode 1 : I/O will hand shake Mode 2 : Bidirectional I/O data transfer

Control Word Formats

BSR

For I/O

i) BSR: CWF 0 D6 X X Here port C will be activated D5 X D4 D3 D2 D1 D0 Bit set = 1 Reset = 0 Bit select

210

ii) I/O Mode:

D6

D5

D4

D3

D2

D1

D0

Group B PCL PB Mode Selection 0 = Mode 0 1 = Mode 1

PC0 P1

Mode Selection 00 = Mode 0 01 = Mode 1 1X = Mode 2

1 = Input 0 = Output

Interfacing 8255 in I/O mapped I/O with 8085: CWR has A1 0 0 1 1 A0 0 1 0 1 Port A Port B Port C Control register

211

D0-D7 A0 A1 IO R IO W Reset A7 A6 A5 A4 A3 A2 Interfacing 8255 in memory mapped I/O with 8085: D0-D7 A0 A1 MR M W Reset A7 . . . . . . A2 8255 8255

PA

PB

PC

CS

PA

PB

PC

CS

212

Question and Answers

Two mark questions: i) ii) Draw the BSR of control word format? Write a program of initializing 8255 configuration i) ii) iii) iv) Port A : Port B : PCL PCU : : Simple output Simple input Input Output

Solution: D6 1 So MVI OUT Essay questions: 1) Discuss I/O interfacing 8255 with 8085? Ans: I/O mapped I/O Memory mapped I/O A, 0 D5 0 83 H 83 H 83 D4 0 D3 0 D2 0 D1 1 D0 1

Load CWR Out & Execute CWR

213

Day 26 & 27th in Microprocessor

214

Day 26 & 27

The timer 8253 / 54 The generation of accurate time delays under software control. The timer will count the delay and interrupt CPU when the task was completed. 8253 8254 ( 0 to 2.6 MHz) (N Mos) (0 to 10 MHz) (H Mos)

Block diagram:

D0-D7

Data bus buffer

Counter 0

Clk 0 GATE 0 OUT 0 Clk 1 GATE 1 OUT 1 Clk 2 GATE 2 OUT 2

RD W A0 A1 C

R/W Control log 2

Counter 1

Counter 2 CWR

215

80 Pin diagram is
D7 D6 D5 D4 D3 D2 D1 D0 Clk 0 OUT 1 GATE 0 GND Vcc WR

8254

RD CS A1 A0 Clk GATE 2 OUT 2 Clk 1 GATE 1 OUT 1

Using the address lines A1 0 0 1 1 Operation modes: Note will be in annexure Interfacing 8254 with 8085 I/O Mapped I/O A0 0 1 0 1 Counter 0 Counter 1 Counter 2 CWR

216

D0 D7

Clk 0 GATE 0

8085 A0 A1

8254

OUT 0 Clk 1 GATE 1 OUT 1

IOR

RD WR

Clk 2 GATE 2 OUT 2 CS

IOW

A2 A3 A4 A5 A6 A7

217

Memory Mapped I/O:

D0 D7

Clk 0 GATE 0 8254 A0 A1 OUT 0 Clk 1 GATE 1 OUT 1

8085

MR

RD WR

Clk 2 GATE 2 OUT 2

MW A2
. . . . .

CS

A15 Interfacing 8254 with 8086 I/O Mapped I/O: Similarly 8085 interfacing Interfacing 8254 with 8086 Memory Mapped I/O: Address lines for chip select A3 to A19

218

Essay questions:
1) Draw and explain the block diagram of 8254? 2) Explain interfacing of 8254 with 8085 in I/O mapped I/O and memory mapped I/O? 3) Explain interfacing of 8254 with 8086 in I/O Mapped I/O and memory mapped I/O?

Objective questions:
1) The following is programmable interval times i) 555 ii) 8254 ii) DMA ii) 0 to 10 MHz ii) 0 to 10 MHz ii) NMOS ii) HMOS ii) A1A0 = 1 1 2) 8254 does ________ i) Accurate time delays 3) Clock frequency of 8253 ________ i) 0 to 2.6 MHz i) 0 to 2.6 MHz 5) 8253 is _______ i) CMOS 6) 8254 is _________ i) CMOS i) A1 A0 = 0 0 7) Address lines to select CWR 4) Clock frequency of 8254 __________

RESULT ANALYSIS
Answer: 1) ii 2) i 3) i 4) ii 5) ii 6) ii 7) ii

If you score is 6 or greater you can walk to day 30.

219

Day 28th in Microprocessor

The robustic walk towards keyboard / display controller

220

Day 28
Keyboard
When key is pressed 5 +v

Log <1

Log <1

Log <0 O/P

Simple keyboard interface Keyboard is input device K1 K2 K3 Input port D0-D7 K4 K5 K6 K7 K8

221

K1 is pressed D0 0 other are 1 Matrix keyboard I/P is . 5V

C3

C2

C1

C0

R3 I/P Port A R2 R1 R0

Display interfacing 7 Segment display a

f g

e d

They are two types i) Common Anode type ii) Common Cathode type

222

Common Anode:
Vcc

Common Cathode:
A B C D E F G

Multiplexed Display:
We need port A and Port B also

223

Vcc R a b Output Port A A B C D c d e f g

abcdefg abcdefg abcdefg abcdefg

a b c d e f g Segment Bus

Q4 Output Port B

Q3

Q2

Q1 5V

224

Interfacing 8279 in I/O mapped I/O with 8085

D0 D7 A0 IOR IOW 8085 Microprocesso r Reset out Clk out

SHIFT CNTL RL0-L7 RD 8279 WR S0S5 A0A5 INT B0B5 CS Return lines

Seen lines GATE 1 OUT 1 Display Clklines 2 GATE 2 OUT 2

A7 . . . . A1 Interfacing 8279 in I/O Mapped I/O with 8086: A2.A15 Address lines

225

IC 8279: Functional Diagram

Vcc

IRQ Data bus RD CPU interface WR CS A0 Reset CLK

RL0-L7 SHIFT 8279 CNTL SL0-3 Seen lines Key data

Out A0-3 Display data Out B0-3

Vss Major functional groups are CPU interface Key data Display data Seen

226

8085 interfacing 8279 in Memory Mapped I/O:

D0 D7 A0 MR MN 8085 Reset Clk INT

SHIFT CNTL 8279

SHIFT CNTL RL0-L7 S0S5 A0A7 B0B5

CS

A1 . . . . A15 8086 Interfacing 8279 in Memory Mapped I/O: A2.A19 Address lines Similarly like 8085 interfacing

227

Question and Answers

Essay questions:
1) 2) 3) a. Give instruction about keyboard / display input and output device b. Explain 8279 a. Explain the interfacing of 8279 in I/O mapped I/O with 8085? b. Explain the interfacing of 8279 in memory mapped I/O with 8085? a. Explain the interfacing of 8279 in I/O Mapped I/O with 8086? b. Explain the interfacing of 8279 in memory Mapped I/O with 8086?

228

Day 29th in Microprocessor

Try to be affluent in microprocessor on your memory bank.

229

Day 29
Interrupt Controller (8259 A)
By connecting such a device it is possible to increase the interrupt handling capacity of the microprocessor. AD0 Microprocessor 8085 D0 8259 A IR0 1 2 3 4 5 6 7

AD7
INTA INTA

D7
INTA

Eight Priority Interrupts

Block Diagram:
It has eight blocks i) ii) iii) iv) v) vi) Data bus buffer R/W logic Control logic IRR, ISR and IMR Priority resolver Cascade buffer

230

INT A CONTROL LOGIC D0-D7 Data bus buffer

INT

INTERNAL

RD WR A0

R/W Logic

CS CAS0 CAS1 CAS2 SP / CS

Cascade buffer comparator

Interrupt service reg (ISR)

Priority Resolver

Interrupt request reg (IRR)

BUS

Interrupt Mask Reg (IMR)

IRR:
To store all the interrupt levels which are requesting the service.

ISR:
Store all the levels that are currently being serviced. ii) 8259 interfacing with 8086: same as 8086. Address line A4A15

231

Cascading: A7 . . A4 A3 A2 A1 8085 IO/M CS 8255 D0 . . . . D7 74LS130

y0 y1 y2

8259

D7 . . D0

Priority Resolver:
Highest priority interrupt is set in ISR during the INTA input cascade buffer. Cascading 8259 A interfacing

232

i) Interfacing with 8085: A7 . . A4 A3 A2 A1 IO/M 8085 Contro l bus RD WR INTR INTE D0 D1 Data bus D2 D3 D4 D5 D6 D7 CAS
2

5V 74LS138

Address bus

8259 A

IR0 . . IR7

CAS
0

CAS
1

233

8259 A IR0 8259A 8085

IR00
. . . . .

IR1

8259 A

IR07 IR11
. . . . .

IR IR22
. .

8259 A

IR17 IR20
. . . .

. . . .

IR27

IR7

234

Question and Answers

Two mark question
1) What is 8259 A? Ans: (Priority) Interrupt controller

Essay questions
1) Explain about 8259? 2) Explain 8259 interfaces with 8085? 3) Cascade 2 priority resolver?

235

Day 30th in Microprocessor

Be triumph in cycle stealing (DMA)

236

Day 30
DMA Controller (8257)
To transfer data microprocessor has to do following tasks i) To fetch the instruction ii) iii) To decode the instruction To execute the instruction

Actually DMA hardware is

AD0-AD15 Microprocesso r 8085

Address Latches

Address bus Memory Data bus

Data bus Control bus IOR, IOW, MR, MW

B Control bus B

HLD0

HOLD

DMA Controller HLD 0 IOR, IOW, MR, MW DREU DACK It has Channel each channel can be programmed individually TTL Clock

Peripheral Device

237

The functional block diagram

Data bus buffer

CH0

16 bit addr CNTR

DRQ0 DACK0

IOR IO W Clk A0 . . A3 A4 . . A7 HR Q HLS MR MW

R/W Logic

CH1

16 bit addr CNTR

DRQ1 DACK1

CH2

Control logic and mode set register

16 bit addr CNTR

DRQ2 DACK2

CH3

16 bit addr CNTR

DRQ3 DACK3

Priority resolver

238

Interfacing 8257 to 8085 in I/O Mapped I/O: A0-A15 D0-D7 RD 8 WR 0 IO/M 8 5 Microprocessor Decoder IOR IOW MR MW

Dev0 MW MR IOU IOR HOLD 8257 HOLD A Clk CS

DRQ1 DACK1 DRQ0 DACK0

IOR IOW

Dev1
IOR IOW

Dev2
DRQ2 DACK2

IOR IOW

Dev3
DRQ3 DACK3

IOR IOW

A4 A5 A6 A7

CS

Similarly memory mapped I/O but address lines for CS is A4 .A15

239

Cascading DMA Controller:

D0-D7 A0-A15

MASTER DMA

8085 Microprocessor

DRQ3 DACK 3 . . . . DRQ0 DACK0

IOR IOW MR MW

SLAVE DMA

IOR IOW MR MW

DRQ3 DACK 3 . . . . DRQ0 DACK0

240

QUESTION AND ANSWERS Essay Questions: I. II. III. IV. Explain 8257 with block diagram? Discuss in 8257 I/O Mapped I/O interfacing with 8085? Discuss in 8257 Memory Mapped I/O interfacing with 8085? Explain cascading of 8275?

241

MODULE V

242

Unit V
Architecture of 8051 Microcontroller Signals I/O Ports Memory Counters and timers Serial data I/O interrupts. Interfacing keyboard, LCD, ADC and DAC

243

Day XXXI in Microprocessor

Adorning the microprocessor with 8051 micro controller.

Microcontroller (8051) (Intel)

244

 It is single chip computer 4k ROM program area 128 x 8 RAM data area Event counters 2 x 16 bit 5 interrupts 8051 has Microprocessor + built in ROM, RAM + I/O devices + timers + counters Access time is less So 8051 contains i) ii) iii) iv) CPU Two kinds of memory (RAM and ROM) I/O ports Special function register and control logic

245

Architecture is

Register A

S.P

Latch 0 Buffer 0

Port 0 O/P driv

Temp reg

Temp reg

P. Counter Latch 1 Buffer 1

. . .

PC Incrementer

Port 1 O/P driv

. . .

ALU

DPTR Latch 2 Buffer 2 Port 2 O/P driv

. . .

PSW

RAM Address register

Program Address register

Latch 3 Buffer 3

Port 3 O/P driv

. . .

ALE

RSP

Timing and Control

RAM

ROM Interrupt, serial port, timer and mr/mw control

- - CPU

OSC

IR

PCON TH0 SBUF

SCON TH1 IE

TMJD TL0 TP

TCON TL1

Special function register 5

246

c) On Chip program memory: d) I/O ports: 32 I/O pins

Port 0

. .

I/O, A0-A7, D0-D7

Port 1

. .

I/O

Port 2

. .

I/O, A8-A15

Port 3

. .

I/O Interrupt Counter Serial data RD - WR

e) Register set i) Accumulator ii) B register: GPR but not multiply (or) divide iii) PSW:

B7

B6

B5

B4

B3

B2

B1

B0

Carry flag AC Flag zero Bank 0 - 3

Over flow flag Reserved Parity

247

F Stack and Stack pointer G: - DPTR

DPH

DL1

( (HL)) H: p counter i) Special function register

Question and Answers

Two mark questions
1. What is 8051? Define: Ans: It is microcontroller. A single chip computer 2. 8051 Contain what? Ans: Microprocessor + built in ROM + RAM + I/O devices + timers + counters

248

Day 32
II) Memory organization in 8051:
ROM/EPROM FFFF RAM

0000 RD WR

PSEN

Each memory is different addressing, control signals and function (Register B, SP, PSW, DPP, DPL)

III) I/O Pins, ports and C lets

IV) External program memory:

P1

P0 8051
L A T C H

D0-D7 A0-A7 ROM

P3

PL

A8-A15

249

If freq = 1/12 freq If crystal frequency 12 MHz then clock frequency is 1 MHz. Serial port and their programming: 8051 Full duplex.

Mode 0:
8 bit transmitted

Mode 1:
10 bits transmitted Start + 8 bit + stop bits

Mode 2:
11 bits are transmitted Start + 8 data bit + programmable data bit + stop

Mode 3:
11 bits are transmitted Baudrade changes

ALE

WR

PORT 0

A0-A7

Data out

A0-A7

MOV X

A, @ RB Copy the contents of the external address in Rp to A

External data memory

250

VI Timers / Counters and their programming: 2 timer (Timer 0 & Timer 1) Timer is counting m/c cycles.

EA

ET2

ES

ET1

EX1

ET0

EX0

Enable all control bit

Reserved Enable serial port control bit Enable timer 1 Enable External interrupt Enable timer 0 Enable Internal interrupt 0 control bit

Prior 3:
I E0 TF0 IE1 TF1 RI+TI

Interrupt structure: 5 interrupt sources INTO and INT 1 level activated or transition activated.

251

0 IE0 INT0

TP0

IE1 INT1 1

Interrupt sources

TF1 T1 R1

IE0, IE1 Bits

252

RD WR

0803 Vcc

D0

8051 Port

Clk

D7

DAC:
V ref A1 A A A + 2 + 3 + ............... + 8 R ref 2 4 8 256

I0 =

A7

Rref

Vref

A8

V0

253

Interfacing kbd:

Return lines

1.4 Port 1.3 1.2 1.1

8051

Scon lines

ADC:
MSD . . . .

Clk

Digital output

LSB 8085 Interfacing:

D0 . . . . . D7

ADC 0804

Analog output

V0

DAC 0808
254

D0
. .

V0 DAC 0808

8085

. .

D7

QUESTION AND ANSWERS Essay questions: 1) Explain the memory organization in 8051? 2) Explain I/O pins, ports and circuits in 8051? 3) Explain Timer / Counter in 8051? 4) Explain interrupt structure in 8051? 5) Explain interfacing kbd with 8051? 6) Explain interfacing DAC with 8051? 7) Explain interfacing ADC with 8051?

255

Day 33 in Microprocessor

8051 vibrates.

256

Pin diagram 8051:

P 1.0 P 1.1 P 1.2 Port 1 P 1.3 P 1.4 P 1.5 P 1.6 P 1.7 RST P 3.0 P 3.1 P 3.2 Port 3 P 3.3 P 3.4 P 3.5 P 3.6 P 3.7 X1 X2 GND 8051

Vcc P 0.0 P 0.1 P 0.2 P 0.3 P 0.4 P 0.5 P 0.6 P 0.7 EA ALE PSEN P 2.7 P 2.6 P 2.5 P 2.4 P 2.3 P 2.2 P 2.1 P 2.0 Port 2 Port 0

a) CPU: ALU + A reg + B reg + PSW + SP + PC + DP + Special function register. On chip data memory and Register Bank: Internal RAM has: 1) Working register 2) Bit addressable 3) General purpose

257

7F

i) Working Register:

1F Bank 3 16 17 Bank 2 7F

0F Bank 1

08 07

R7 R6 R5

Bank 0

R4 R3 R2 R1 00 R0 00 16 Addressable byte memory 30

258

3) Draw PSW? Ans: B7 CY B6 AC B5 Z B4 B3 B2 O B1 B0 Parity

Reserved Base memory 00 11 (0 5)

Essay questions:
I) Draw the architecture of 8051 and pin diagram?

Objective questions:
1) 8051 is program area _________ a) 2KROM a) 128 x 8 a) 4 b) 4kROM b) 256 x 8 b) 5 2) 8051s RAMs data area _________ 3) 8051 has __________ interrupts 4) Internal RAM i) working register ii) Data addressable memory 3) ______________ a) GPR a) 4 b) Instruction decoder b) 7 5) 8051 has ___________ ports

259