11713233 Christopher Earnshaw Introduction to Digital Systems; Assignment 2; Pattern Shifting with Different Frequencies Introduction In this assignment

t we have been tasked with making up a digital electronic circuit with the aid of Xilinx Design Suite 14.1. The task itself is to create the programming for a seven segment display and use pattern shifting techniques to manipulate the display of a number, and move if from left to right at 4 different frequencies. These frequencies are (1Hz, 2Hz, 4Hz, and 8Hz) and should take no longer than 4 seconds to complete each cycle at the specific frequency. Then after completing the cycle at 8Hz, the cycle should return to 1Hz. In this Assignment each block has had to be demonstrated separately as there have been major issues with the software implementation of the top level program at the simulation stage, preventing an accurate overall readout. In the Assignment It was chosen to use computer written annotations over hand written ones due to the illegible hand writing of the Author. FREQUENCY DIVIDER CIRCUIT Frequency Dividers or Phase-locked Loop Frequency Synthesisers, Utilise a reference signal as an input and generate a reference frequency at half the input frequency. Here we will be using Sixteen Hertz input, and will be used as the input or Clock signal as well as a relevant output frequency. Edge triggered D Flip Flops will be used to achieve the desired result of division of 16Hz to 8Hz, 8Hz to 4Hz, 4Hz to 2Hz, 2Hz to 1Hz. By the Addition of an Inverter to the output of each Flip Flop, we can achieve a positive edge triggered output during the transition of the clock signal to the next frequency at the next Flip Flop. This means that as the first Flip Flop has completed one cycle the Flip Flop receiving that input has completed two full cycles triggered by the positive edge of the previous frequency, hence achieving frequency division.

MULTIPLEXER CIRCUIT A Multiplexer has been used in the Assignment to provide a number of functions. A Multiplexers function is to select a single or multiple binary input signals and forward it to a solitary output. In this assignment the Multiplexer has been utilised to provide the management of the various frequencies from the Frequency Divider and direct the appropriate output. The table below demonstrates the operation of the Multiplexer, As the Multiplexer is connected to select from all the frequencies, an And gate has been used to stop all the input frequencies from passing through at the same time, meaning that both inputs have to be (1) In order for that frequency to be selected. The table states that at an input of (00) from the Two Bit Counter, (AA both complimented, provided for by the AND Gates with inverted input) will turn positive, and will therefore select the base input of 8Hz and turn the second AND Gate to (1), sending a signal to the OR Gate which funnels the signal to pass through one output. Thus once the cycle for 8Hz has completed the Multiplexer is then fed the next input of (01) from the two bit counter, and will repeat the process for each frequency in order. The Simulation attachment demonstrates this sliding selection of states the Multiplexer performs. As shown in the Circuit Diagram, there are a number of outputs that are paralleled off each output. These are Four LEDs that will display the appropriate output for the selected frequency.

FOUR BIT COUNTER CIRCUIT The function of a Four Bit Counter is to receive a single input in the form of a clock signal and utilise the rising and falling edges of the signal to manipulate a combination of Flip Flops. The Flip Flops take the input and determine the next state conditions by the ability of the Flip Flop to store the present state value (e.g.0000) and complement the least significant bit with every new input signal from the Clock signal (changes to 0001). The Table below demonstrates the application of this into the Assignment; when the present state of (0000) is loaded into the Flip Flop, at the next pulse from the clock circuit, the present state changes to an output of (0001), on the next clock pulse ( changes to 0010), and so forth until the count reaches 15 in binary. We need this to occur to get the count up to 15 to cycle enough outputs for the Anode selection to complete one full cycle of the different states it performs at the selected frequency signal. After the present state reaches (1111) we want it to return the count back to (0000) hence the lack of outputs after (1111). The Reset column demonstrates the ability of the Reset button to clear the present state and return the count cycle back to (0000), as it operates under negative logic conditions.

*Foot Note* There Is a screenshot of the simulation of the Four Bit Counter, at the end of the report, however due to complications with the simulations, the visible range is from (0-8) in binary only, as the simulation will show, once a greater time frame is selected to show the latter numbers, the clock signal no longer follows the correct pattern, leading to the conclusion of a defect in the simulation software.

Below is the State Diagram for the Four Bit Counter. The State (0000) passes to (0001) with every pulse from the clock (1) as detailed in the truth table. With the return arrows to (0000) added, for the possibility that the reset button is pressed at any point of the count. There is no need for the state to count down or go to the pervious state as this is beyond the scope of the assignment.

The equations derived from the Karnaugh maps are detailed below, and assisted in the creation of the schematic for the Four Bit Counter; A+ = A+BCD B+ = BD+BC+BCD C+ = CD+CD D+ = D

TWO BIT COUNTER CIRCUIT The function of the two bit counter circuit, is to provide a similar function to the Four Bit Counter, except in the case of the assignment the function is to connect the external clock, to the clock input of the first Flip-Flop (A1) only. So, A1 deviates its own state at the falling edge of each clock pulse, but (A0) deviates only when triggered by the falling edge caused by the Q output of (A1). Due to the momentary delay caused by the flip-flop, the conversion of the input clock pulse and the conversion of the Q output of (A0) can always arise at closely the comparable time. Hence (00 turns to 01), the Flip-Flops cannot be triggered all together, fabricating an asynchronous clock circuit. In regards to the table below, The function of the Table suggests that the operation is similar to an XOR gate hence the usage of the particular gate, to achieve the desired outcome.

The equations derived from the Karnaugh maps are detailed below, and assisted in the creation of the schematic for the Two Bit Counter; A+ = AB B+ = AB The Sate Diagram for this Circuit is relatively straight forward to follow seen as there is only four states that need to be addressed, and the counter counts up and includes the reset function returning the present state to (00).

ANODE SELECTION CIRCUIT

The Anode Selection Circuit function is to simply display the number (0) on the Seven Segment display, which is physically mounted on the circuit board. The truth table below shows the various input positions from 1 to 15 in hexadecimal and the corresponding input from the decoder. Thus the output signal of (1) will illuminate the corresponding segment on the circuit board, reading from left to right. We will only require (0) for the Assignment, however we require all of the positions to be mapped in order to build an appropriate circuit for each segment. The Equations below the table show how the Karnaugh Maps are turned into an equation then after that, the corresponding circuit has been included to demonstrate how the equation is implemented.

A = (BD)+(ACD)+(ABC)+(AC)+(BC)+(ABC) B = (BD)+(ACD)+(ABC)+(ACD)+(AB) C = (BC)+(AB)+(CD)+(AB)+(AD) D = (AC)+(ABD)+(BCD)+(BCD)+(BCD)+(ABC) E = (BD)+(AB)+(CD)+(AC) F = (CD)+(ABC)+(BD)+(AC)+(AB) G = (CD)+(AB)+(ABC)+(AD)+(BC)

The blocks generated for the segments have been connected to the main four inputs (IA, IB, IC, ID) and have been grounded due to the need for the generation of one digit only, being (0). This way we have removed the ability of the segments to change or become affected by the operation of another part of the Anode & Segment Selection, whilst still projecting a (0) (Segment G is the only segment to remain at 0). The Diagram below shows the layout of the Seven Segment Display with Individual Segments.

ANODE & SEGMENT SELECTION CIRCUIT The purpose of the Anode & Segment Selection Circuit is to select the appropriate output display based on the incoming signal from the Four Bit Counter. For Example the Four Bit counter outputs (0000). The input signal of the Anode selection will then select (D8) and due to the independent operation of the segment display, the Zero will appear at position (D8). Subsequently when (0001) is input, the position of (D7) is selected, and the (0) will extinguish from (D8) and illuminate at (D7). With the arrangement of the Circuit, the appropriate input will then shift the output continually across the display then backward, completing one cycle at that given frequency, as the truth table shows below the shifting states. When the higher Frequency is selected by the Multiplexer, the clock cycles fed into the Anode & Segment Selection Circuit will get faster (or slower depending on the frequency) and the (0) will shift faster across the display. The Equations below the table, show how the Karnaugh Maps are turned into an equation from the Truth Table, then after that, the corresponding circuit has been included to demonstrate how the equation is implemented and their relation to the binary inputs.

D8 = ABCD + ABCD D7 = ABCD + ABCD D6 = ABCD + ABCD D5 = ABCD + ABCD D4 = ABCD + ABCD D3 = ABCD + ABCD D2 = ABCD + ABCD D1 = ABCD + ABCD

TOP LEVEL CIRCUIT Finally the Last Circuit to be implemented is the Top Level Circuit. Here all the circuits have been converted into blocks to be connected on a larger scale. There has been the addition of and AND gate at the start of the circuit to accommodate the Pause Button Function. With the negative logic operation of the buttons the input of both the pause button and clock signal will be (1, 1) respectively, meaning the AND gates output will be (1) and the circuit can function as described. When the button is pressed the logic of the button will go (0), resulting in the AND gate having (0, 1). This means that as long as the button is depressed, the circuit will cease functioning, the display will hold at the current location and the counters will hold at the current number. Once the button is released the circuit will resume its operation from that point. The addition of the LED Clock between the Multiplexer and the Four Bit counter means that the LED will show the current frequency that has been selected. As mentioned in the Introduction the inability of the software to correctly simulate the top level program has meant that only the simulation of each block has been possible. However attempts have been made to download the software to the kit in order to be able to demonstrate the process physically.