Am29F160D

Data Sheet

July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with Am and MBM. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

Publication Number 22288 Revision D

Amendment 0 Issue Date December 4, 2000

Am29F160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 Volt single power supply operation Minimizes system-level power requirements s High performance Access times as fast as 70 ns s Manufactured on 0.25 m process technology s CFI (Common Flash Interface) compliant Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices s Ultra low power consumption (typical values at 5 MHz) 15 mA typical active read current 35 mA typical erase/program current 300 nA typical standby mode current s Flexible sector architecture One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode) One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode) Supports full chip erase Sector Protection features: Hardware method of locking a sector to prevent program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Top boot or bottom boot configurations available s Minimum 1,000,000 write cycle guarantee per sector s 20-year data retention at 125C Reliable operation for the life of the system s Package options 48-pin TSOP s Compatibile with JEDEC standards Pinout and software compatible with singlepower supply Flash Superior inadvertent write protection s Embedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifies data at specified addresses s Erase Suspend/Erase Resume Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Data# Polling and toggle bits Provides a software method of detecting program or erase operation completion s Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences s Ready/Busy# pin (RY/BY#) Provides a hardware method of detecting program or erase cycle completion s Hardware reset pin (RESET#) Hardware method to reset the device for reading array data s WP# input pin At VIL, protects the 16 Kbyte boot sector, regardless of sector protect/unprotect status At VIH, allows removal of boot sector protection s Program and Erase Performance Sector erase time: 1 s typical for each 64 Kbyte sector Byte program time: 7 s typical

Publication# 22288 Rev: D Amendment/0 Issue Date: December 4, 2000

GENERAL DESCRIPTION
The Am29F160D is a 16 Mbit, 5.0 Volt-only Flash memory device organized as 2,097,152 bytes or 1,048,576 words. Data appears on DQ0-DQ7 or DQ0DQ15 depending on the data width selected. The device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. The device is offered in a 48-pin TSOP package. To eliminate bus contention each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Write Protect (WP#) feature protects the 16 Kbyte boot sector by asserting a logic low on the WP# pin, whether or not the sector had been previously protected. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The device offers a standby mode as a power-saving feature. Once the system places the device into the standby mode power consumption is greatly reduced. AMDs Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.

Am29F160D

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . Word/Byte Configuration .......................................................... Requirements for Reading Array Data ..................................... Writing Commands/Command Sequences .............................. Program and Erase Operation Status ...................................... Standby Mode .......................................................................... Automatic Sleep Mode ............................................................. RESET#: Hardware Reset Pin ................................................. Output Disable Mode................................................................ 4 4 5 6 6 7 8 8 8 9 9 9 9 9 9
Figure 5. Data# Polling Algorithm .................................................. 23

RY/BY#: Ready/Busy#............................................................ DQ6: Toggle Bit I .................................................................... DQ2: Toggle Bit II ................................................................... Reading Toggle Bits DQ6/DQ2............................................... DQ5: Exceeded Timing Limits ................................................ DQ3: Sector Erase Timer .......................................................

24 24 24 24 25 25

Table 1. Am29F160D Device Bus Operations .................................. 8

Figure 6. Toggle Bit Algorithm........................................................ 25 Table 10. Write Operation Status................................................... 26

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27

Figure 7. Maximum Negative Overshoot Waveform ...................... 27 Figure 8. Maximum Positive Overshoot Waveform........................ 27

Table 2. Am29F160DT Sector Address Table (Top Boot) .............. 10 Table 3. Am29F160DB Sector Address Table (Bottom Boot)......... 11

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28 TTL/NMOS Compatible .......................................................... 28 CMOS Compatible.................................................................. 29 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Test Setup....................................................................... 30 Table 11. Test Specifications ......................................................... 30

Autoselect Mode..................................................................... 12
Table 4. Am29F160D Autoselect Codes (High Voltage Method).... 12

Sector Protection/Unprotection............................................... 12 Write Protect (WP#)................................................................ 13 Temporary Sector Unprotect .................................................. 13

Figure 1. Temporary Sector Unprotect Operation........................... 13

Key to Switching Waveforms. . . . . . . . . . . . . . . . 30 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Read Operations Timings ............................................. Figure 11. RESET# Timings .......................................................... Figure 12. BYTE# Timings for Read Operations............................ Figure 13. BYTE# Timings for Write Operations............................ Figure 14. Program Operation Timings.......................................... Figure 15. Chip/Sector Erase Operation Timings .......................... Figure 16. Data# Polling Timings (During Embedded Algorithms). Figure 17. Toggle Bit Timings (During Embedded Algorithms)...... Figure 18. DQ2 vs. DQ6................................................................. Figure 19. Temporary Sector Unprotect Timing Diagram .............. Figure 20. Sector Protect/Unprotect Timing Diagram .................... Figure 21. Alternate CE# Controlled Write Operation Timings ...... 31 32 33 33 35 36 37 37 38 38 39 41

Common Flash Memory Interface (CFI) . . . . . . . 15

Table 5. CFI Query Identification String .......................................... 15 Table 6. System Interface String..................................................... 16 Table 7. Device Geometry Definition .............................................. 16 Table 8. Primary Vendor-Specific Extended Query ........................ 17

Hardware Data Protection ...................................................... 18

Low VCC Write Inhibit ...................................................................... 18 Write Pulse Glitch Protection ........................................................ 18 Logical Inhibit .................................................................................. 18 Power-Up Write Inhibit .................................................................... 18

Reading Array Data ................................................................ Reset Command..................................................................... Autoselect Command Sequence ............................................ Word/Byte Program Command Sequence .............................

18 18 19 19

Unlock Bypass Command Sequence.............................................. 19 Figure 3. Program Operation .......................................................... 20

Chip Erase Command Sequence ........................................... 20 Sector Erase Command Sequence ........................................ 20 Erase Suspend/Erase Resume Commands........................... 21
Figure 4. Erase Operation............................................................... 21

Command Definitions ............................................................. 22

Table 9. Am29F160D Command Definitions................................... 22

DQ7: Data# Polling................................................................. 23

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 42 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 42 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43 TSR04848-Pin Reverse Thin Small Outline Package......... 44 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision A (January 1999) ..................................................... 45 Revision B (June 14, 1999) .................................................... 45 Revision B+1 (July 7, 1999).................................................... 45 Revision B+2 (July 14, 1999).................................................. 45 Revision B+3 (July 30, 1999).................................................. 45 Revision B+4 (September 10, 1999) ...................................... 45 Revision C (November 16, 1999) ........................................... 45 Revision D (December 4, 2000) ............................................. 45

Am29F160D

PRODUCT SELECTOR GUIDE

Family Part Number Speed Option Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) VCC = 5.0 V 5% VCC = 5.0 V 10% 70 70 30 75 90 90 90 35 120 120 120 50 Am29F160D

Note:See AC Characteristics for full specifications.

BLOCK DIAGRAM
RY/BY# VCC VSS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0DQ15 (A-1)

WE# WP# BYTE#

State Control Command Register

PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch

CE# OE#

STB VCC Detector Timer Address Latch

Y-Decoder

Y-Gating

X-Decoder

Cell Matrix

A0A19

Am29F160D

CONNECTION DIAGRAMS

A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48-Pin TSOP Standard Pinout

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0

A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48-Pin TSOP Reverse Pinout

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1

Am29F160D

PIN CONFIGURATION
A0A19 = 20 address inputs DQ0DQ14 = 15 data inputs/outputs DQ15/A-1 BYTE# CE# OE# WE# WP# RESET# RY/BY# VCC = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Select input for 8-bit or 16-bit mode = Chip Enable input = Output Enable input = Write Enable input = Write Protect input = Hardware reset input = Ready/Busy# output = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) = Device ground = Pin not connected internally

LOGIC SYMBOL
20 A0A19 DQ0DQ15 (A-1) CE# OE# WE# WP# RESET# BYTE# RY/BY# 16 or 8

VSS NC

Am29F160D

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29F160D T 75 E C
TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (40C to +85C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION

Am29F160D 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Boot Sector Flash Memory 5.0 Volt-only Read, Program and Erase

Valid Combinations Order Number AM29F160DT75, AM29F160DB75 AM29F160DT90, AM29F160DB90 AM29F160DT120, AM29F160DB120 EC, EI, FC, FI

Valid Combinations
Speed (ns) 70
90

Voltage Range 5.0 V 5%

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

5.0 V 10%
120

Am29F160D

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1.

Am29F160D Device Bus Operations

DQ8DQ15 Addresses (Note 1) AIN AIN X X X Sector Address, A6 = L, A1 = H, A0 = L Sector Address, A6 = H, A1 = H, A0 = L AIN DQ0 DQ7 DOUT DIN High-Z High-Z High-Z DIN BYTE# = VIH DOUT DIN High-Z High-Z High-Z X BYTE# = VIL DQ8DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z X

Operation Read Write Standby Output Disable Reset Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect

CE# L L VCC 0.5 V L X L

OE# WE# L H X H X H H L X H X L

WP# X (Note 3) (Note 4) X X X

RESET# H H VCC 0.5 V H L VID

L X

H X

L X

X (Note 3)

VID VID

DIN DIN

X DIN

X High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the Sector Protection/Unprotection section. 3. The 16 Kbyte boot sector is protected when WP# = VIL. 4. In CMOS mode, WP# must be at VCC0.5 V or left floating.

Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data for more information. Refer to the AC Read Operations table for timing specifica-

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power 8

Am29F160D

tions and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. See the Command Definitions section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Automatic Sleep Mode

The automatic sleep mode minimizes flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and timing diagram.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status for more information, and to each AC Characteristics section for timing diagrams.

Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# are held at VCC 0.5 V. (Note that this is a more restricted voltage range than VIH.) WP# must also either be held at VCC 0.5 V or left floating. The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Am29F160D

Table 2.

Am29F160DT Sector Address Table (Top Boot)

Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address Range (in hexadecimal) Byte Mode (x8) 00000000FFFF 01000001FFFF 02000002FFFF 03000003FFFF 04000004FFFF 05000005FFFF 06000006FFFF 07000007FFFF 08000008FFFF 09000009FFFF 0A00000AFFFF 0B00000BFFFF 0C00000CFFFF 0D00000DFFFF 0E00000EFFFF 0F00000FFFFF 10000010FFFF 11000011FFFF 12000012FFFF 13000013FFFF 14000014FFFF 15000015FFFF 16000016FFFF 17000017FFFF 18000018FFFF 19000019FFFF 1A00001AFFFF 1B00001BFFFF 1C00001CFFFF 1D00001DFFFF 1E00001EFFFF 1F00001F7FFF 1F80001F9FFF 1FA0001FBFFF 1FC0001FFFFF Word Mode (x16) 0000007FFF 080000FFFF 1000017FFF 180001FFFF 2000027FFF 280002FFFF 3000037FFF 380003FFFF 4000047FFF 480004FFFF 5000057FFF 580005FFFF 6000067FFF 680006FFFF 7000077FFF 780007FFFF 8000087FFF 880008FFFF 9000097FFF 980009FFFF A0000A7FFF A8000AFFFF B0000B7FFF B8000BFFFF C0000C7FFF C8000CFFFF D0000D7FFF D8000DFFFF E0000E7FFF E8000EFFFF F0000F7FFF F8000FBFFF FC000FCFFF FD000FDFFF FE000FFFFF

Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34

A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1

A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1

A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1

A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1

A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1

A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration section.

10

Am29F160D

Table 3.

Am29F160DB Sector Address Table (Bottom Boot)

Sector Size (Kbytes/ Kwords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (in hexadecimal) Byte Mode (x8) 000000003FFF 004000005FFF 006000007FFF 00800000FFFF 01000001FFFF 02000002FFFF 03000003FFFF 04000004FFFF 05000005FFFF 06000006FFFF 07000007FFFF 08000008FFFF 09000009FFFF 0A00000AFFFF 0B00000BFFFF 0C00000CFFFF 0D00000DFFFF 0E00000EFFFF 0F00000FFFFF 10000010FFFF 11000011FFFF 12000012FFFF 13000013FFFF 14000014FFFF 15000015FFFF 16000016FFFF 17000017FFFF 18000018FFFF 19000019FFFF 1A00001AFFFF 1B00001BFFFF 1C00001CFFFF 1D00001DFFFF 1E00001EFFFF 1F00001FFFFF Word Mode (x16) 0000001FFF 0200002FFF 0300003FFF 0400007FFF 080000FFFF 1000017FFF 180001FFFF 2000027FFF 280002FFFF 3000037FFF 380003FFFF 4000047FFF 480004FFFF 5000057FFF 580005FFFF 6000067FFF 680006FFFF 7000077FFF 780007FFFF 8000087FFF 880008FFFF 9000097FFF 980009FFFF A0000A7FFF A8000AFFFF B0000B7FFF B8000BFFFF C0000C7FFF C8000CFFFF D0000D7FFF D8000DFFFF E0000E7FFF E8000EFFFF F0000F7FFF F8000FFFFF

Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34

A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A14 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

A13 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

A12 X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the Word/Byte Configuration section.

Am29F160D

11

Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are dont care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See Command Definitions for details on using the autoselect mode.

Table 4.

Am29F160D Autoselect Codes (High Voltage Method)

A19 A11 to to A12 A10 X X X X A8 to A7 X X A5 to A2 X X DQ8 to DQ15 X 22h VID L L H X 22h X X VID X L X L H X X D8h 01h (protected) 00h (unprotected) D2h D8h DQ7 to DQ0 01h D2h

Description

Mode

CE# L

OE# L L L L L

WE# H H H H H

A9 VID

A6 L

A1 L

A0 L

Manufacturer ID: AMD Device ID: Am29F160D (Top Boot Block) Device ID: Am29F160D (Bottom Boot Block) Word Byte Word Byte

L L L L

Sector Protection Verification

SA

VID

L X

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.

Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMDs ExpressFlash Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Sector protection/unprotection can be implemented via two methods.

The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 20 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 5.0 volt-only AMD flash devices. Details on this method are provided in a supplement, publication number 22289. Contact an AMD representative to request a copy.

12

Am29F160D

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the 16 Kbyte boot sector without using VID. If the system asserts VIL on the WP# pin, the device disables program and erase functions for the 16 Kbyte boot sector (SA34 for top boot device and SA0 for bottom boot device) independently of whether those sectors were protected or unprotected using the method described in Sector Protection/Unprotection. If the system asserts VIH on the WP# pin, the device reverts to whether the 16 Kbyte boot sector was previously set to be protected or unprotected using the method described in Sector Protection/Unprotection.
START

RESET# = VID (Note 1) Perform Erase or Program Operations

RESET# = VIH

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Note, however, that the boot sector will still be protected if WP# is asserted low. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure shows the algorithm, and Figure 19 shows the timing diagrams, for this feature.

Temporary Sector Unprotect Completed (Note 2)

Notes: 1. All protected sectors unprotected. Boot sector remains protected if WP# is low. 2. All previously protected sectors are protected once again.

Figure 1.

Temporary Sector Unprotect Operation

Am29F160D

13

START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address

START PLSCNT = 1 RESET# = VID Wait 1 s

Temporary Sector Unprotect Mode

No

First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No

No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0

Temporary Sector Unprotect Mode

Increment PLSCNT

Reset PLSCNT = 1

Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0

No No PLSCNT = 25? Yes Data = 01h?

Increment PLSCNT

Yes

No Yes No

Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address

Device failed

Protect another sector? No Remove VID from RESET#

PLSCNT = 1000? Yes

Data = 00h? Yes

Device failed Write reset command

Last sector verified? Yes

No

Sector Protect Algorithm

Sector Protect complete

Sector Unprotect Algorithm

Remove VID from RESET#

Write reset command Sector Unprotect complete

Figure 2.

In-System Sector Protect/Unprotect Algorithms

14

Am29F160D

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 58. In word mode, the upper address bits (A7MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 58. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.

Table 5.
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h

CFI Query Identification String

Description Query Unique ASCII string QRY

Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)

Am29F160D

15

Table 6.
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0045h 0055h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h

System Interface String

Description VCC Min. (write/erase) D7D4: volt, D3D0: 100 millivolt VCC Max. (write/erase) D7D4: volt, D3D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)

Table 7.
Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h

Device Geometry Definition

Description Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
N

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

16

Am29F160D

Table 8.
Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h

Primary Vendor-Specific Extended Query

Data Description Query-unique ASCII string PRI Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC Supply Minimum ACC Supply Maximum Top/Bottom Boot Sector Flag 02 = bottom, 03 = top

0050h 0052h 0049h 0031h 0031h 0000h 0002h 0001h 0001h

49h

92h

0004h

4Ah 4Bh 4Ch 4Dh 4Eh 4Fh

94h 96h 98h 9Ah 9Ch 9Eh

0000h 0000h 0000h 0000h 0000h 0002h, 0003h

Am29F160D

17

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than V LKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are dont care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Command section, next.

18

Am29F160D

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. When a read occurs at an address within the 16 Kbyte boot sector (SA34 for top boot devices and SA0 for bottom boot devices), the input on WP# may determine what code will be returned.
16Kb Sector Protection protected protected unprotected unprotected WP# input VIH VIL VIH VIL Autoselect Code 01 (protected) 01 (protected) 00 (unprotected) 01 (protected)

margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by byte or word, on depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell

Am29F160D

19

START

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC Characteristics for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.

Write Program Command Sequence

Embedded Program algorithm in progress

Data Poll from System

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the DQ3: Sector Erase Timer section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should

Verify Data?

No

Yes No

Increment Address

Last Address?

Yes Programming Completed

Note: See the appropriate Command Definitions table for program command sequence.

Figure 3.

Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.

20

Am29F160D

be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status for information on these status bits. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.

the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. The system must write the Erase Resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are dont-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine

START

Write Erase Command Sequence

Data Poll from System

Embedded Erase algorithm in progress

No

Data = FFh?

Yes Erasure Completed

1. See the appropriate Command Definitions table for erase command sequence. 2. See DQ3: Sector Erase Timer for more information.

Figure 4.

Erase Operation

Am29F160D

21

Command Definitions
Table 9.
Command Sequence (Note 1)
Read (Note 6) Reset (Note 7) Manufacturer ID Word Byte Word Byte Word Byte Word Sector Protect Verify (Note 9) Byte CFI Query (Note 10) Program Unlock Bypass Word Byte Word Byte Word Byte 4 AAA

Am29F160D Command Definitions

Bus Cycles (Notes 25) Second Addr Data
RD F0 AA AA AA 2AA 555 2AA 555 2AA 555 2AA AA 555 98 AA AA A0 90 AA AA B0 30 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 555 AAA 555 AAA A0 20 PA PD 55 AAA 55 55 55 555 AAA 555 AAA 555 AAA 555 90 (SA) X04 90 90 90 X00 X01 X02 X01 X02 (SA) X02 01 22D2 D2 22D8 D8 XX00 XX01 00 01

Cycles

First Addr
RA XXX 555 AAA 555 AAA 555 AAA 555

Third Addr

Fourth Data Addr Data

Fifth Addr Data

Sixth Addr Data

Data

1 1 4 4 4

Autoselect (Note 8)

Device ID, Top Boot Block Device ID, Bottom Boot Block

1
4

555 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX

3
2 2

Unlock Bypass Program (Note 11) Unlock Bypass Reset (Note 12) Chip Erase Sector Erase Erase Suspend (Note 13) Erase Resume (Note 14) Word Byte Word Byte

6 6 1 1

Legend: X = Dont care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19A12 uniquely select any sector.

Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ15DQ8 are dont cares for unlock and command cycles. 5. Address bits A19A11 are dont cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, CFI query mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence for more information. 10. Command is valid when device is ready to read array data or when device is in autoselect mode. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

14. The Erase Resume command is valid only during the Erase Suspend mode.

22

Am29F160D

WRITE OPERATION STATUS

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 10 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys tem whether an Embedded Algor ithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 2 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7 DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0DQ6 while Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in the AC Characteristics section illustrates this.
Read DQ7DQ0 Addr = VA

DQ7 = Data?

Yes

No No

DQ5 = 1?

Yes Read DQ7DQ0 Addr = VA

DQ7 = Data?

Yes

No FAIL PASS

Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

Figure 5.

Data# Polling Algorithm

Am29F160D

23

RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the relationship of RY/BY# to other signals.

The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 6 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the AC Characteristics section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II explains the algorithm. See also the DQ6: Toggle Bit I subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and

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Am29F160D

the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).

of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 shows the outputs for DQ3.

START

Read DQ7DQ0

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Under both these conditions, the system must issue the reset command to return the device to reading array data.
No Read DQ7DQ0
(Note 1)

Toggle Bit = Toggle? Yes

No

DQ5 = 1?

Yes

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also the Sector Erase Command Sequence section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status
Read DQ7DQ0 Twice
(Notes 1, 2)

Toggle Bit = Toggle?

No

Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete

Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.

Figure 6.

Toggle Bit Algorithm

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25

Table 10.
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program

Write Operation Status

DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 2) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 1) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0

DQ7 (Note 1) DQ7# 0 1 Data DQ7#

Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits for more information.

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Am29F160D

ABSOLUTE MAXIMUM RATINGS

Storage Temperature Plastic Packages . . . . . . . . . . . . . . . 65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . 55C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . .2.0 V to +7.0 V A9, OE#, and RESET# (Note 2). . . . . . . . . . . . 2.0 V to +12.5 V All other pins (Note 1) . . . . . . . . . 0.5 V to +7.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to 2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is 0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot VSS to 2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +13.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns +0.8 V 0.5 V 2.0 V 20 ns 20 ns 20 ns

Figure 7. Maximum Negative Overshoot Waveform

20 ns

Figure 8. Maximum Positive Overshoot Waveform

OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . 40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . 55C to +125C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

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27

DC CHARACTERISTICS TTL/NMOS Compatible

Parameter ILI ILIT ILO Description Input Load Current A9, OE#, RESET Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = OE# = RESET# = 12.5 V VOUT = VSS to VCC CE# = VIL, OE# = VIH, f = 5 MHz, Byte Mode CE# = VIL, OE# = VIH, 15 Min Typ Max 1.0 35 1.0 40 Unit A A A mA

ICC1

VCC Active Read Current (Notes 1, 2)

f = 5 MHz, Word Mode

ICC2 ICC3 VIL VIH VID VOL VOH VLKO VCC Active Write Current (Notes 2, 3 and 4) VCC Standby Current (Notes 2, 5) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary VCC = 5.0 V Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4) IOL = 5.8 mA, VCC = VCC min IOH = 2.5 mA, VCC = VCC min 2.4 3.2 CE# = VIL, OE# = VIH CE#, OE#, and RESET# = VIH 0.5 2.0 11.5

15

50

mA

35 0.4

50 1 0.8 VCC + 0.5 12.5 0.45

mA mA V V V V V

4.2

Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifcations are tested with VCC = VCCmax 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Not 100% tested. 5. ICC3 = 20 A max at extended temperature (>+85C)

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Am29F160D

DC CHARACTERISTICS CMOS Compatible

Parameter ILI ILIT ILO Description Input Load Current A9, OE#, RESET Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max, A9 = OE# = RESET = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, f = 5 MHz Byte Mode CE# = VIL, OE# = VIH, f = 5 MHz Word Mode CE# = VIL, OE# = VIH CE# and RESET# = VCC0.5 V, WP# = VCC0.5 V or floating, OE# = VIH 0.5 0.7 x VCC VCC = 5.0 V IOL = 5.8 mA, VCC = VCC min IOH = 2.5 mA, VCC = VCC min IOH = 100 A, VCC = VCC min Low VCC Lock-Out Voltage (Note 3) 0.85 VCC VCC0.4 3.2 4.2 11.5 15 Min Typ Max 1.0 35 1.0 Unit A A A

40

mA

ICC1

VCC Active Read Current (Note 2)

15

50

mA

ICC2

VCC Active Write Current (Notes 1, 2, 3) VCC Standby Current (Note 2) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage

35

50

mA

ICC3 VIL VIH VID VOL VOH1 VOH2 VLKO

0.3

5 0.8 VCC + 0.3 12.5 0.45

A V V V V V V V

Notes: 1. ICC active while Embedded Erase or Embedded Program is in progress. 2. Maximum ICC specifcations are tested with VCC = VCCmax 3. Not 100% tested.

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29

TEST CONDITIONS
Table 11.
5.0 V Test Condition Device Under Test CL 6.2 k 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels 30 5 0.03.0 1.5 1.5 75 90, 120 1 TTL gate 100 20 0.452.4 0.8, 2.0 0.8, 2.0 pF ns V V V Unit

Test Specifications

Note: Diodes are IN3064 or equivalents.

Output timing measurement reference levels

Figure 9.

Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Dont Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS

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Am29F160D

AC CHARACTERISTICS Read Operations

Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Enable Hold Time (Note 1) Read Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min 75 70 70 70 30 20 20 Speed Option 90 90 90 90 35 20 20 0 10 0 120 120 120 120 50 30 30 Unit ns ns ns ns ns ns ns ns ns

tOEH

tAXQX

tOH

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)

Notes: 1. Not 100% tested. 2. See Figure 9 and Table 11 for test specifications.

tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC

OE#

Figure 10.

Read Operations Timings

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31

AC CHARACTERISTICS Hardware Reset (RESET#)

Parameter JEDEC Std tREADY tREADY tRP tRH tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RY/BY# Recovery Time Test Setup Max Max Min Min Min All Speed Options 20 500 500 50 0 Unit s ns ns ns ns

Note: Not 100% tested.

RY/BY#

CE#, OE# tRH RESET# tRP tReady

Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms

tReady RY/BY# tRB CE#, OE#

RESET# tRP

Figure 11.

RESET# Timings

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Am29F160D

AC CHARACTERISTICS Word/Byte Configuration (BYTE#)

Parameter JEDEC Std. tELFL/tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min 20 70 Speed Options 75 90 5 20 90 30 120 120 Unit ns ns ns

CE#

OE#

BYTE# tELFL DQ0DQ14

BYTE# Switching from word to byte mode

Data Output (DQ0DQ14)

Data Output (DQ0DQ7) Address Input

DQ15/A-1

DQ15 Output tFLQZ tELFH

BYTE# BYTE# Switching from byte to word mode

DQ0DQ14

Data Output (DQ0DQ7) Address Input tFHQV

Data Output (DQ0DQ14) DQ15 Output

DQ15/A-1

Figure 12.

BYTE# Timings for Read Operations

CE# The falling edge of the last WE# signal WE#

BYTE#

tSET (tAS)

tHOLD (tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 13.

BYTE# Timings for Write Operations

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33

AC CHARACTERISTICS Erase/Program Operations

Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std. tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note 2) Word Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Typ Typ Min Min Min 30 12 1 50 0 35 50 sec s ns ns Min Min Min Min Min Min Min Min Min Min Min Typ 35 45 30 Speed Options 75 70 90 90 0 45 45 0 0 0 0 0 45 20 7 s 50 50 50 120 120 Unit ns ns ns ns ns ns ns ns ns ns ns

Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance section for more information.

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Am29F160D

AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles)

PA

PA

tCH

A0h

Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.

Figure 14.

Program Operation Timings

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35

AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase

Read Status Data

VA tAH

VA

CE#

OE# tWP WE# tCS tDS

tCH

tWPH

tWHWH2

tDH Data 55h 30h

10 for Chip Erase In Progress Complete

tBUSY RY/BY# tVCS VCC

tRB

Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status). 2. Illustration shows device in word mode.

Figure 15.

Chip/Sector Erase Operation Timings

36

Am29F160D

AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z

VA

VA

tOE tDF

Complement

Complement

True

Valid Data
High Z

DQ0DQ6 tBUSY RY/BY#

Status Data

Status Data

True

Valid Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 16.

Data# Polling Timings (During Embedded Algorithms)

tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY#
High Z

VA

VA

VA

tOE tDF

Valid Status (first read)

Valid Status (second read)

Valid Status (stops toggling)

Valid Data

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 17.

Toggle Bit Timings (During Embedded Algorithms)

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37

AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete

Erase Suspend Read

DQ6

DQ2

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.

Figure 18.

DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter JEDEC Std. tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s

Note: Not 100% tested.

12 V

RESET# 0 or 5 V tVIDR Program or Erase Command Sequence CE# tVIDR 0 or 5 V

WE# tRSP RY/BY#

Figure 19.

Temporary Sector Unprotect Timing Diagram

38

Am29F160D

AC CHARACTERISTICS
VID VIH

RESET#

SA, A6, A1, A0

Valid* Sector Protect/Unprotect

Valid* Verify 40h

Sector Protect: 150 s Sector Unprotect: 15 ms

Valid*

Data 1 s CE#

60h

60h

Status

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 20.

Sector Protect/Unprotect Timing Diagram

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39

AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations

Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std. tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 45 30 75 70 Speed Options 90 90 0 45 45 0 0 0 0 0 45 20 7 s 12 1 sec 50 50 50 120 120 Unit ns ns ns ns ns ns ns ns ns ns ns

Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance section for more information.

40

Am29F160D

AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase

Data# Polling PA

Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase

tAS tAH

tWHWH1 or 2

tBUSY

DQ7#

DOUT

RESET#

RY/BY#

Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 21.

Alternate CE# Controlled Write Operation Timings

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41

ERASE AND PROGRAMMING PERFORMANCE

Parameter Sector Erase Time Chip Erase Time (Note 2) Byte Programming Time Word Programming Time Chip Programming Time (Note 2) Byte Mode Word Mode Typ (Note 1) 1.0 25 7 11 15 12 300 360 45 35 Max (Note 3) 8 Unit s s s s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4)

Notes: 1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min 1.0 V 1.0 V 100 mA Max 12.5 V VCC + 1.0 V +100 mA

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF

Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.

DATA RETENTION
Parameter Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years

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Am29F160D

PHYSICAL DIMENSIONS TS 04848-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

Am29F160D

43

PHYSICAL DIMENSIONS TSR04848-Pin Reverse Thin Small Outline Package

Dwg rev AA; 10/99

44

Am29F160D

REVISION SUMMARY Revision A (January 1999)

Initial release. DC Characteristics

TTL/NMOS Compatible table: Changed the maximum current specification for ICC2 to 50 mA.

Revision B (June 14, 1999)

Global Expanded data sheet into document with full specifications. Deleted the 55 ns speed options. Distinctive Characteristics In the Ultra Low Power Consumption bullets, changed the typical current to match the DC specifications (CMOS Compatible) table.

Revision B+4 (September 10, 1999)

Device Bus Operations

Write Protect (WP#): Clarified explanatory text.

Command Definitions

Autoselect Command Sequence: Added text and table explaining effect of WP# input on autoselect code output for 16 Kbyte boot sector.

Revision C (November 16, 1999)

AC CharacteristicsFigure 14. Program Operations Timing and Figure 15. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations.

Revision B+1 (July 7, 1999)

Connection Diagrams Corrected the signals on pins 39 and 40 of the reverse TSOP package.

Revision B+2 (July 14, 1999)

Global Changed the VCC operating range of the 70 ns speed option to 5.0 V 5%. Deleted all references to uniform sector. Command Definitions table In Note 7, added a reference to CFI query mode.

Revision D (December 4, 2000)

Removed Advance Information status from document. Ordering Information Deleted optional processing. Table 9, Command Definitions In Note 5, changed the lower address bit in dont care range to A11. Table 11, Test Specifications Changed capacitive loading on 70 ns speed option to 30 pF

Revision B+3 (July 30, 1999)

Global Changed the part number designator for the 70 ns speed option to 75 (with VCC rated at 5.0 V 5%).

Trademarks Copyright 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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