Dr.

Abhijit RAsati EEEDepartment, BITS,Pilani

Placement Two types of heuristic algorithm are used to obtain a near optimal solution in reasonable amount of computational time. Constructive C t ti : Used to obtain initial solution Sequential, deterministic or probabilistic Iterative : Improve a solution by repeated modification Simulated annealing, simulated evolution, partitioning based

Problem statement :
Input: B1,B2,B3Bn are blocks to be placed on chip .The block Bi has height hi &width wi N={N { 1, ,N2, ,N3.Nm} are set of nets representing p g interconnections between different blocks. Output p : Q={Q1,Q2,Q3.Qk} represent rectangular empty area allocated for routing between blocks. L Li denote the estimated length of net Ni. Find iso-oriented rectangle for each block R={R1,R2.Rn} such that Ri has widthwi& height hi. The total area of the rectangle bounding R & Q is minimized & no two rectangles overlap. Total wire length i.e. Li (i=1...m) is minimized. The length of longest net i.e. i e max{Li|i=1..m} is minimized (performance driven placement). Placement is routable.

Constructive Algorithm: IOC method for Initial placement with minimum total routing length: IOC for each unplaced block is I-0. Where : I I=sum sum of signal net connectivity to all placed blocks. blocks O=sum of signal net connectivity to all unplaced blocks. Th blocks The bl k with ith the th highest hi h t IOC value l is i then th selected l t d for f placement. l t

Routing Regions in Different Design Styles:

Initial placement and Rout-ability Analysis : (Global Routing) Block are placed anywhere such that it should provide 100% routing. After placement if it is found that 100% routing is not possible we may y eve even alter e p placement. ce e .

A rough wiring analysis is performed for each placement refinement to determine : Weather the resulting layout will be routable or not. not Total routing length i.e. area occupied by routing

Grid-graph model: Each cell is given a vertex Vertices are joined by an edge if cells are adjacent Filled circles: Occupied cells Empty circles: Unoccupied cells present at location. Edge d weight i h represents channel h l capacity. i

Channel intersection model: Channels are represented p as edges. g Channel intersections and terminals are represented as vertices. Edge weight represents channel capacity.

Global routing problem: Input: Net-list N = {n1, n2, , nm} A routing graph G(V,E), where V is a set of vertices, and E is a set of edges g Output: Steiner tree Ti for each net 'n ni' such that : X(ej) C(ej) for all ej E where: ej = individual edge C(ej) = capacity of edge ej ( j) = number of wires p passing g through g ej j X(ej) The total length of all the steiner trees is minimized.

Area-Routing: Terminals are allowed anywhere in the routing area. area Take into account gate area & routing area.

The total Th t t l routing ti length l th can be b estimated ti t d using i following f ll i heuristic h i ti algorithms. Minimum spanning tree Steiner tree Half perimeter method Chain-Tree Chain Tree Complete Graph Source to Sink Connection

Design style specific placement problem :Full F ll Custom: C t Standard-cells: Gate-Arrays :

Classification of placement Algorithm: (1) Simulation-Based placement Algorithm: Simulated Annealing g Algorithm g Simulated Evolution Algorithm Force-Directed Force Directed placement Sequence-pair Technique (2) Partitioning-Based placement Algorithm:(Breuers Algorithm)

(2) Partitioning-Based placement Algorithm:(Breuers Algorithm) It performs the partitioning of the both i.e. given circuit and their simultaneous placement by partitioning layout area. C={c1,c2,c3.cn} =set of n cut-lines The order of cut lines which g gives minimum routing-length g g is the best order.

Such reduction of net-cuts in sequential-manner is GreedyApproach, may not yield optimal solution. Useful for standard-cell and gate-arrays.

Cut oriented min-cut placement : Alternate horizontal and vertical cut cut-lines lines. Easy to implement. Dose not always yield good results. Suitable S it bl for f the th unequal l size i blocks. bl k Blocks created by previous cut-line have to partitioned simultaneously therefore may require more space.

Quandrature placement procedure: Each region is partitioned into four regions of equal sizes by using horizontal and vertical cut lines. Most popular sequence of cut lines. Blocks Bl k of f equal l size. i (eg.GA) ( GA)

Bisection placement procedure : First Bisected by horizontal cut cut-lines lines until each sub sub-region region consist of one row. Then Bisected by vertical cut-lines to place all cells/blocks. Used U d for f standard t d d cell ll placement. l t Does not guarantee minimization of maximum net cut per channels .

Slice-Bisection placement : First Bisected by y horizontal cut-lines until each sub-region g consist of a row assigned to a component/block. Then Bisected by vertical cut-lines to place all bit-slice in a component. component Suitable for circuits which have a high degree of interconnection at the periphery.

A Data-Path Compiler: y:=0; for bit-position:=0 upto n_bits-1 do begin x:=0; for all data path elements (e) do begin ( , p ); cell:=selectDPEcell(e,bit-position); makeInstance (cell,x,y); y:=y + height of (cell); end; x:=x + width of (cell); end;