AN989

Using the MSSP Module to Interface I2C Serial EEPROMs with PIC18 Devices
This application note is intended to serve as a reference for communicating with Microchips 24XXX series serial EEPROM devices with the use of the MSSP module featured on many PIC18 family devices. Source code for common data transfer modes is also provided. Figure 1 describes the hardware schematic for the interface between Microchips 24XXX series devices and the PIC18F452 PICmicro microcontroller. The schematic shows the connections necessary between the microcontroller and the serial EEPROM as tested, and the software was written assuming these connections. The SDA and SCL pins are open-drain terminals, and therefore require pull-up resistors to VCC (typically 10 k for 100 kHz, and 2 k for 400 kHz and 1 MHz). Also, the WP pin is tied to ground because the writeprotect feature is not used in the examples provided. Author: Chris Parris Microchip Technology Inc.

INTRODUCTION
The 24XXX series serial EEPROMs from Microchip Technology are I2C compatible and have maximum clock frequencies ranging from 100 kHz to 1 MHz. The MSSP module available on many PICmicro microcontrollers provides a very easy-to-use interface for communicating with the 24XXX series devices. The largest benefit of using the MSSP module is that the signal timings are handled through hardware rather than software. This allows the firmware to continue executing while communication is handled in the background. This also means that an understanding of the timing specifications associated with the I2C protocol is not required in order to use the 24XXX series devices in designs.

FIGURE 1:

CIRCUIT FOR PIC18F452 AND 24XXX SERIES DEVICE

PDIP (600 MIL)
MCLR RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS OSC1 OSC2 RC0 RC1 RC2 RC3/SCL RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4/SDA RD3 RD2 Vcc

A0 A1 A2 Vss

1 2 3 4 24XXXXX

PIC18F452

8 7 6 5

Vcc WP SCL SDA 4.7K 4.7K

*SDA and SCL require pull-up resistors (10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). Note that pins A0, A1 and A2 are not internally connected in some devices.

2005 Microchip Technology Inc.

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AN989
FIRMWARE DESCRIPTION
The purpose of the firmware is to show how to generate specific I2C transactions using the MSSP module on a PICmicro microcontroller. The configuration required for I2C Master mode is explained, as well as some of the specific details of the I2C protocol. The focus is to provide the designer with a strong understanding of communication with the 24XXX series serial EEPROMs using the MSSP module and I2C, thus allowing for more complex programs to be written in the future. The firmware consists of a single assembly program, organized into five sections: Initialization Byte Write Byte Read Page Write Sequential Read

The program also illustrates the Acknowledge polling feature for detecting the completion of write cycles after the byte write and page write operations. Read operations are located directly after each write operation, thus allowing for verification that the data was properly written. No method of displaying the input data is provided, but an oscilloscope or a Microchip MPLAB ICD 2 could be used. The code was tested using the 24LC256 serial EEPROM. This device features 32K x 8 (256 Kbit) of memory and 64-byte pages. The 24LC256 also features a configurable, 3-bit address via the A2, A1 and A0 pins. For testing, these pins were all grounded for a chip address of 000. Oscilloscope screen shots are labeled for ease in reading. The data sheet versions of the waveforms are shown below the oscilloscope screen shots. All timings are designed to meet the 100 kHz specs, and a 10 MHz crystal oscillator is used to clock the PIC18F452. If a faster clock is used, the code must be modified for the MSSP module to generate the correct clock frequency. All values represented in this application note are hex values unless otherwise noted.

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AN989
INITIALIZATION
In order to configure the MSSP module for I2C Master mode, several key registers on the PICmicro microcontroller need to be properly initialized. Code examples are shown for each.

SSP Control Register 1 (SSPCON1)

SSPCON1 is one of the Configuration registers for the MSSP module. In I2C Master mode, the upper two bits of SSPCON1 are indicator bits and should be cleared initially. Also, while in Master mode, the SCL Release Control bit (CKP) is not used. The SSP Enable bit (SSPEN) must be set in order to enable the serial port. The mode is set using the SSPM3:SSPM0 bits, which need to be 1000 for I2C Master mode. This register is configured using the code shown in Example 3.

SSP Status Register (SSPSTAT)

SSPSTAT holds all of the Status bits associated with the MSSP module. In I2C mode, this includes indicators for Start/Stop bit detection, R/W information, etc. It also contains the Slew Rate Control bit (SMP) and the SMBus Select bit (CKE). The source code provided uses a 100 kHz clock for I2C, so the slew rate control is not used. Therefore, the SMP bit is set to disable slew rate control. Also, SMBus specific inputs are not being used, so the CKE bit is cleared to disable them. This is done as shown in Example 1.

EXAMPLE 3:
MOVLW MOVWF

SSPCON1 CONFIGURATION

b00101000 ; Load WREG with ; 0x28 SSPCON1 ; Copy value to ; SSPCON1

EXAMPLE 1:
CLRF BSF

SSPSTAT CONFIGURATION

; Disable SMBus ; inputs SSPSTAT,SMP ; Disable slew ; rate control

SSPSTAT

SSP Control Register 2 (SSPCON2)

SSPCON2 is the other Configuration register used for the MSSP module, and contains all of the sequence enable bits. These bits are used to initiate the different sequences associated with I2C operations. For example, to generate a Start condition, the Start Condition Enable bit (SEN) is set. All of the SSPCON2 register bits are cleared at POR, but not after other Resets. Therefore, it is good practice to clear the SSPCON2 register during the initialization routine, as shown in Example 4.

SSP Address Register (SSPADD)

In I2C Master mode, SSPADD acts as the baud rate generator reload value. Equation 1 shows how to calculate the value for SSPADD, based on a desired bit rate and a known FOSC. In testing the example code provided, a 10 MHz crystal oscillator was used, and the target bit rate was 100 kHz. Therefore, SSPADD needed to be set to 0x18. Example 2 shows how to do this in code.

EXAMPLE 4:
CLRF

SSPCON2 CONFIGURATION
; Clear control ; bits

SSPCON2

EQUATION 1:

SSPADD CALCULATION

F OSC ------------------ BitRate SSPADD = ------------------------- 1 4 EXAMPLE 2:

MOVLW MOVWF 0x18 SSPADD

TRISC Register
In order to be properly controlled by the MSSP module, both RC3 and RC4 must be configured as inputs. This is done by setting their respective bits in TRISC to 1, as shown in Example 5. The MSSP module will ensure that each pin is configured as an output when needed.

SSPADD CONFIGURATION
; Load WREG with ; 0x18 ; Copy value to ; SSPADD

EXAMPLE 5:
BSF BSF

TRISC CONFIGURATION
; Configure SCL ; as an input ; Configure SDA ; as an input

TRISC,RC3 TRISC,RC4

2005 Microchip Technology Inc.

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AN989
BYTE WRITE
The Byte Write operation has been broken down into the following components: the Start condition and control byte, the word address, and the data byte and Stop condition. Note that, due to the size of the 24LC256, two bytes are used for the word address. However, 16 Kb and smaller 24XXX series devices use only a single byte for the word address. All I2C commands must begin with a Start condition. This consists of a high-to-low transition of the SDA line while the clock (SCL) is high. After the Start condition, the 8 bits of the control byte are clocked out, with data being latched in on the rising edge of SCL. The device code (0xA for the 24LC256), the chip address (3 bits), and the R/W bit make up the control byte. Next, the EEPROM device must respond with an Acknowledge bit by pulling the SDA line low for the ninth clock cycle. Before initiating the Start condition, the SSP Interrupt Flag (SSPIF, PIR1<3>) must be cleared. Once this is done, the Start condition can be initiated by setting the SEN bit (SSPCON2<0>). Before continuing with the I2C operation, the PICmicro microcontroller must wait for the SSPIF bit to be set by hardware, thus indicating that the Start condition has been successfully generated. After the Start bit has been sent, the control byte can be transmitted. To do so, first clear the SSPIF flag again, then simply write the control byte to SSPBUF. The MSSP module will automatically begin transferring the data to the EEPROM device. The module will also detect whether or not the device responded with an ACK bit, and will set the ACKSTAT bit (SSPCON2<6>) accordingly. Again, the PICmicro microcontroller must wait until the SSPIF bit has been set, indicating that the MSSP module has finished, before continuing.

Start Bit and Control Byte Transmission

Figure 2 shows the details of the Start condition and the control byte. The left marker shows the position of the Start bit, whereas the right marker shows the ACK bit.

FIGURE 2:

START BIT AND CONTROL BYTE

BUS ACTIVITY MASTER

S T A R T

Control Byte

SDA LINE BUS ACTIVITY

AA S1 0 1 0A 2 10 0 A C K

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AN989
Sending the Word Address
After the EEPROM device has acknowledged receipt of the control byte, the master (PIC18F452) begins to transmit the word address. For the 24LC256, this is a 15-bit value, so two bytes must be transmitted for the entire word address (the MSb of the high byte is a dont care), with the Most Significant Byte sent first (note that 16 Kb and smaller 24XXX series devices only use a 1-byte word address). These bytes can be sent via the MSSP module using the same method described above for the control byte. After each byte of the word address has been transmitted, the device must respond with an Acknowledge bit. Figure 3 shows the two address bytes and corresponding ACK bits. For reference, the previous ACK bit (in response to the control byte) is shown by the left marker. Note that the word address chosen for this application note is 0x5A00.

FIGURE 3:

WORD ADDRESS

BUS ACTIVITY MASTER

Address High Byte x A C K

Address Low Byte

SDA LINE BUS ACTIVITY x = dont care bit

A C K

2005 Microchip Technology Inc.

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AN989
Data Byte and Stop Bit Transmission
Once the word address has been transmitted and the last ACK bit has been received, the data byte can be sent. Once again, the EEPROM device must respond with another ACK bit. After this has been received, the master generates a Stop condition. This consists of a low-to-high transition of SDA while the clock (SCL) is high. Initiating a Stop condition using the MSSP module is similar to initiating a Start condition, except that the PEN bit (SSPCON2<2>) is used for the Stop condition. As with the Start condition, the PICmicro microcontroller first clears the SSPIF bit, sets the PEN bit and then waits for the SSPIF bit to be set by hardware. Figure 4 shows the transmission of the data byte, as well as the Stop condition indicating the end of the operation. Again, the left marker shows the previous ACK bit (that of the word address). The right marker denotes the Stop condition.

FIGURE 4:

DATA BYTE AND STOP BIT

BUS ACTIVITY MASTER

Data

S T O P P A C K

SDA LINE BUS ACTIVITY

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AN989
ACKNOWLEDGE POLLING
The data sheets for the 24XXX series devices specify a write cycle time (TWC), but the full time listed is not always required. Because of this, using a measured write cycle delay is not always accurate, which leads to wasted time. Therefore, in order to transfer data as efficiently as possible, it is highly recommended to use the Acknowledge Polling feature. Since the 24XXX series devices will not acknowledge during a write cycle, the device can continuously be polled until an Acknowledge is received. This is done after the Stop condition takes place to initiate the internal write cycle of the device.

Acknowledge Polling Routine

The process of acknowledge polling consists of sending a Start condition and then a Write command to the EEPROM device, then simply checking the ACKSTAT bit to see if the ACK bit was received. If it was not received (i.e., if ACKSTAT is high), then the device is still performing its write cycle. Figure 5 shows an example of acknowledge polling to check if a write operation has finished. In this example, the device did not acknowledge the poll (the ACK bit is high), which indicates that the write cycle has not yet completed.

FIGURE 5:

ACKNOWLEDGE POLLING ROUTINE (SHOWING NO ACK BIT)

BUS ACTIVITY MASTER

S T A R T

Control Byte

SDA LINE BUS ACTIVITY

AA S1 0 1 0A 2 10 0 N O A C K

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AN989
Response to Acknowledge Polling
Figure 6 shows the final acknowledge poll after a write operation, in which the device responds with an ACK bit, indicating that the write cycle has completed and the device is ready to continue.

FIGURE 6:

ACKNOWLEDGE POLLING FINISHED (SHOWING ACK BIT)

BUS ACTIVITY MASTER

S T A R T

Control Byte

SDA LINE BUS ACTIVITY

AA S1 0 1 0A 2 10 0 A C K

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AN989
BYTE READ
The byte read operation can be used to read data from the 24XXX series devices in a random access manner. It is similar to the byte write operation, but slightly more complex. The word address must still be transmitted, and to do this, a control byte with the R/W bit set low must be sent first. However, this conflicts with the desired operation, which is to read data. Therefore, after the word address has been sent, a new Start condition and a control byte with R/W set high must be transmitted. Note that a Stop condition is not generated after sending the word address. Using the MSSP module, transmitting the first control byte and the word address is done in the same fashion as for a byte write.

Writing Word Address for Read

Figure 7 shows an example of the first control byte and the word address of a byte read operation. The left marker indicates the Start bit and the right marker indicates the ACK bit after receipt of the word address (0x5A00 in this example). Once again, the R/W bit must be low in order to transmit the word address.

FIGURE 7:

BYTE READ (CONTROL BYTE AND ADDRESS)

BUS ACTIVITY S T MASTER A R T SDA LINE BUS ACTIVITY

Control Byte x A C K

Address High Byte

S1 0 1 0 AAA0 2 1 0

A C K

2005 Microchip Technology Inc.

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AN989
Reading Data Byte Back
After the word address has been transmitted, the Restart Enable bit (RSEN) is used to initiate a Restart condition. Note that a Restart is very similar to a Start, except that a Restart does not first check for a valid bus condition (this is important since either SCL or SDA may be low at this point, which would cause an error during an attempted Start condition). Also, as with initiating other bus conditions with the MSSP module, the SSPIF flag must be properly cleared and monitored during the sequence. The second control byte (with the R/W bit set) is transmitted as normal. In order to read the data byte, the ACKDT bit is first set to indicate that a NO ACK should be sent. Then (after clearing SSPIF), the RCEN bit is set to initiate the read. Once SSPIF is set by hardware, the data byte can be copied from SSPBUF. Once the data byte has been read back from the 24XXX series device, the master must respond back with a NO ACK bit. To do this, SSPIF is cleared once more and the ACKEN bit is set, sending out the NO ACK bit. This indicates to the device that no more data will be read. Finally, the master generates a Stop condition to end the operation. Figure 8 shows the control byte and data byte during the actual read part of the operation. A Restart condition is generated immediately after receipt of the previous ACK bit and is marked with the left marker. At the end of the transfer, the master indicates that no more data will be read by the use of the NO ACK bit (holding SDA high in place of an ACK bit); this is shown by the right marker. After the NO ACK bit has been sent, the master generates a Stop condition to end the operation.

FIGURE 8:

BYTE READ (CONTROL BYTE AND DATA)

BUS ACTIVITY MASTER

S T A R T

Control Byte

Data Byte

S T O P P

SDA LINE BUS ACTIVITY

S 1 0 1 0 A A A1 2 1 0 A C K N O A C K

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AN989
PAGE WRITE
A very useful method for increasing throughput when writing large blocks of data is to use page write operations. All of the 24XXX series devices, with the exception of the 24XX00, support page writes, and the page size varies from 8 bytes to 128 bytes. Using the page write feature, up to 1 full page of data can be written consecutively with the control and word address bytes being transmitted only once. It is very important to point out, however, that page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses which are integer multiples of the page size, and end at addresses which are [integer multiples of the page size] minus 1. Any attempts to write across a page boundary will result in the data being wrapped back to the beginning of the current page, thus overwriting any data previously stored there. The page write operation is very similar to the byte write operation. However, instead of generating a Stop condition after the first data byte has been transmitted, the master continues to send more data bytes, up to 1 page total. The 24XXX will automatically increment the internal Address Pointer with receipt of each byte. As with the byte write operation, the internal write cycle is initiated by the Stop condition.

Sending Multiple Bytes Successively

Figure 9 shows two consecutive data bytes during a page write operation. The entire transfer cannot be shown legibly due to length, but this screen shot shows the main difference between a page write and a byte write. Notice that after the device acknowledges the first data byte (0x10 in this example), the master immediately begins transmitting the second data byte (0x0F in this example).

FIGURE 9:

PAGE WRITE (TWO CONSECUTIVE DATA BYTES)

BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY A C K

Data (n)

Data (n + 1)

A C K

A C K

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AN989
SEQUENTIAL READ
Just as the page write operation exists to allow for more efficient write operations, the sequential read operation exists to allow for more efficient read operations. While the page write is limited to writing within a single physical page, the sequential read operation can read out the entire contents of memory in a single operation. The sequential read operation is very similar to the byte read operation, except that the master must pull SDA low after receipt of each data byte to send an Acknowledge bit back to the 24XXX series device. This ACK bit indicates that more data is to be read. As long as this ACK bit is transmitted, the master can continue to read back data without the need for generating Start/Stop conditions or for sending more control/word address bytes. In order to do this with the MSSP module, the ACKDT bit must be properly set up before initiating the Acknowledge via the ACKEN bit. Clearing the ACKDT bit produces an ACK bit, whereas setting the ACKDT bit produces a NO ACK bit.

Reading Data Bytes Successively

Figure 10 shows the last two bytes of a 16-byte sequential read operation. Note that the master pulls SDA low to transmit an ACK bit after the first data byte, but leaves SDA high to transmit a NO ACK bit after the final data byte. And as with all other operations, a Stop condition is generated to end the operation.

FIGURE 10:

SEQUENTIAL READ (LAST TWO DATA BYTES)

BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY

Data n + (x-1)

Data n + x

S T O P P

A C K

N O A C K

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AN989
CONCLUSION
When communicating with the 24XXX series EEPROM devices, there are many benefits of using the PICmicro MSSP module over bit-banging through software. The designer does not have to be familiar with the I2C timing specifications, nor is the designer required to write full software routines to provide I2C functionality. This results in much shorter development time. This application note illustrated the main characteristics of I2C communications with Microchips 24XXX series serial EEPROM devices with the use of the PICmicro MSSP module. The assembly code provided is highly portable and can be used with only minor modifications on many PIC18 family PICmicro microcontrollers equipped with the MSSP module. The code was tested on Microchips PICDEM 2 Plus Demonstration Board with the connections shown in Figure 1.

2005 Microchip Technology Inc.

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AN989
NOTES:

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2005 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Companys quality system processes and procedures are for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

2005 Microchip Technology Inc.

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2005 Microchip Technology Inc.